EDK : FSL macros defined by Xilinx are wrong

[Jonathan Bromley]

On 28 Sep 2005 06:45:10 -0700, amyler@eircom.net wrote:

Can anyone recommend a 16-bit microprocessor core to use in an Actel
ProAsic+ device.

Actel just announced availability of ARM7 in ProASIC3.
There will be a small price premium on the parts - the bitstream
(or fusemap or config image or whatever Actel call it) is
encrypted so that there's no risk of ARM's jealously-guarded
IP leaking out, and the ARM-enabled devices have some kind of
internal security key, and you get to pay for that.

Software support is, obviously, rather good. Debug support
is less clear right now - can they do tracing, single-step etc?

Any Actel gurus/AEs/sales-droids out there care to comment?
I don't know the devices too well, and the people on the
Actel booth at ARM DevCon last week weren't exactly crystal-
clear about it all.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Fri, 30 Sep 2005 15:53:03 -0400, "geoffrey wall"
<wallge@eng.fsu.edu> wrote:

I would like to write a parameterizeable component in vhdl
that would do an N element fixed point dot product. I was wondering if there
was a (synthesizable) way to generate a first stage of multiplies (ceil(N/2)
multiply blocks), and
then ceil(log2(N)) - 1 add stages.

Forgive my ignorance and/or stupidity, but how can you get away with
only N/2 multipliers and logN adders? Is there something special
about the values you're processing, or is there some cool math
I don't know about?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Antti Lukats]

"Jonathan Bromley" <jonathan.bromley@doulos.com> schrieb im Newsbeitrag
news:ev9kk1h98br6a0t1nf1jed4073vuijs864@4ax.com...

On 28 Sep 2005 06:45:10 -0700, amyler@eircom.net wrote:

Can anyone recommend a 16-bit microprocessor core to use in an Actel
ProAsic+ device.

Actel just announced availability of ARM7 in ProASIC3.
There will be a small price premium on the parts - the bitstream
(or fusemap or config image or whatever Actel call it) is
encrypted so that there's no risk of ARM's jealously-guarded
IP leaking out, and the ARM-enabled devices have some kind of
internal security key, and you get to pay for that.

Software support is, obviously, rather good. Debug support
is less clear right now - can they do tracing, single-step etc?

rather good? nothing=good ?

to my knowledge Actel is saying that their tools support the ARM7 for some
time already, but if you download and install them, then there is nothing
about ARM7 at all. also its nothing on the website as well. - so whatever
they have announced today or earlier, nothing of it is available as of
today.

so in this case I would say seeing is believing, and currently there is
nothing to see

Antti

 

Why do you not use a PLL within the FPGA ?

You could use the output C0 or C1 of the PLL for FPGA "inner" purposes
and
the output E to route the clock to an output pin.

Rgds
André

 

[Waage]

Let me clarify why I am looking for a 3rd party JTAG programming
solution.
Being relatively new to FPGA design, I am trying to determine if there
is a vendor
non-specific option available. In other words are there solutions out
there that support
JTAG programming for Xilinx, Altera, and others?

Thanks, Chris

 

[Sylvain Munaut]

Eli Hughes wrote:

Hello All:

Jsut an update on my efforts on using the Xilinx IPIF for a PLB master.

Per another user's recommendation (thanks Alan Nishioka), I looked at
the PLB spec from IBM and wrote my own interface.

After several days of messing with the Xilinx IPIF fucntions, I could
not get the master functionality to work correctly.

I did, however, get my own to work pretty much on the first try.

I wrote a simple peripheral that updated the contents of DDR memory
every second with an increasing value (address zero got a 0; address 1
got a 1, etc.)


Moral of the story: Read the PLB datasheet and you will be able to make
whatever you want very quickly. It took me a total of 8 hours of
reading through the datasheet and coding up my own state machine.

If anyone wants to see my code (in Verilog), let me know.

Yes, I'd like to. To get my real email, just do a 'endian swap' on my
email
I was just about to start using the IPIF for PLB master but if I can
interface to the PLB myself and save some slices (the IPIF is 1000
slices with DMA!)

thanks,

Sylvain

 

[Andrew FPGA]

I'm not exactly sure what the original poster was asking, but I use an
SRL16(xilinx) initialised to X"FFFF", configured as 16 bit shift reg,
and a '0' at the D input. Once Done goes high, GWE, GSR, etc are
released(order of these dependent on bitgen options), the shift reg
shifts in the '0' and after 16 clock cycles it appears at the SRL16 Q
output. The Q output drives the reset I code into my design(active
high). This insures my design reset is removed synchronous to my clock
and the path is covered by my clock period timing constraint.

(beware that the GSR net is high fanout and can have significant
delay/skew depending on your clock frequency. I never found any timing
specs for the GSR net in the Sparatan 3 FPGA datahseet...but there are
plenty of posts about it. There is also a good tech exclusive(ken
chapman) on the xilinx site talking about the use of resets in your
FPGA design.)

Regards
Andrew

 

[johnp]

Bill -

What if d is not a 1 or a 0, then what does your logic do?

Remember, when a signal goes metastable, it may have an
indeterminate value, ie, it may hover in the transition region
somewhere between a 0 and a 1.

Also - since you're using the d signal as input to multiple
flops, because of routing and gate delays some flip-flops might
see the d signal after it transitions, others might miss the
transition.

I think you're fighting a losing battle here. Synchronize the signal!

John Providenza

 

[news.hinet.net]

Yes it comes with a linux and solaris cd too

<aholtzma@gmail.com> wrote in message
news:1128618734.597166.265290@g43g2000cwa.googlegroups.com...

Newman wrote:
aholt...@gmail.com wrote:
The Xilinx website isn't too clear with respect to the evaluation EDK
included with the Spartan-3 starter kit. Does anyone know if it is time
limited or feature limited? Can I run the reference microblaze designs
with it? Also, does anyone know if the starter kit will ship with
ISE/EDK 8.1i when it itself ships? Thanks!

cheers,
aaron

Aaron,
IIRC, the Spartan 3 Eval kit shipped with a 60 day eval EDK 6_3 back
in Feb 2005. It also came with a 60 day ISE6_3 eval. I have no
information what they ship now.

-Newman

Thanks. One other thing, do the discs come with the linux binaries as
well?

cheers,
aaron

 

[Bill]

OK. I will go with this instead. The signals a and b is left to settle for 2
clock cycles to minimize the meta stable risk.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sync_to_new_clock is
Port ( new_clk : in std_logic;
d : in std_logic;
q : out std_logic);
end sync_to_new_clock;

architecture beh of sync_to_new_clock is

signal a, b, t : std_logic := '0';
attribute maxdelay: string;
attribute maxdelay of a: signal is "1 ns";
attribute maxdelay of b: signal is "1 ns";
begin
process(new_clk)
begin
if rising_edge(new_clk) then
if t = '0' then
q <= a;
a <= d;
t <= '1';
else
q <= b;
b <= d;
t <= '0';
end if;
end if;
end process;
end beh;



"johnp" <johnp3+nospam@probo.com> skrev i meddelandet
news:1128979682.817345.163290@g49g2000cwa.googlegroups.com...

Bill -

What if d is not a 1 or a 0, then what does your logic do?

Remember, when a signal goes metastable, it may have an
indeterminate value, ie, it may hover in the transition region
somewhere between a 0 and a 1.

Also - since you're using the d signal as input to multiple
flops, because of routing and gate delays some flip-flops might
see the d signal after it transitions, others might miss the
transition.

I think you're fighting a losing battle here. Synchronize the signal!

John Providenza

 

[Bill]

"johnp" <johnp3+nospam@probo.com> skrev i meddelandet
news:1128979682.817345.163290@g49g2000cwa.googlegroups.com...

Bill -

What if d is not a 1 or a 0, then what does your logic do?
Remember, when a signal goes metastable, it may have an
indeterminate value, ie, it may hover in the transition region
somewhere between a 0 and a 1.

The idea was that the state machine wolud jump to the other state or stay at
the present state.

I think you're fighting a losing battle here. Synchronize the signal!

:-(

I know, but it's an interesting topic

 

[Phil Hays]

"Bill" wrote:

I new idea?

Not new.

For example (sampled values)



d: 00000X111111X00000X111111X00000 (X = meta stable bit-level)
State: 000000X111111X00000X111111X0000

Q: 0000000X111111X00000X111111X000

From the initial state it need to interpret two neighbor samples as ones,
only then it gives a one on the q output. Then after that to get a zero on
the q output it must interpret two neighbor samples as zeros, then it gives
a zero on the q output.

But if the state is not one or zero, then with a zero input it might
output a zero, and it might output a one. And with a one input it
might output a zero, and it might output a one.

when others => null;

While this case doesn't exist for binary logic, it does exist if
"state" is not at '1' or '0', or metastable. The problem is that null
isn't a physically realistic choice. The circuit is going to do
something.


--
Phil Hays to reply solve: phil_hays at not(coldmail) dot com
If not cold then hot

 

[Peter Alfke]

Haven't we beaten this to death?
Just keep it simple, double-synchronize the asynchronous input in two
cascaded flip-flops, and keep the delay between the two flip-flops to a
minimum.
At 24 MHz you will have more than 30 ns slack, and the MTBF will be
more than 10e180 years. Call it an eternity. What more do you want ?
Peter Alfke

 

[wiggs]

I have noted that the problem seems to vary with temperature but not
completely depend on it.

It does not seem to be possible to eliminate occurrences of the problem
on our worst samples no matter how much they are blasted with cold
spray.

Likewise on our best boards were the problem rarely (or seemingly never
occurs) under normal operating conditions, it will usually show at
higher temps.

We did not connect the temp diodes on our boards but we attached one to
the metal casing of the FPGA package during tests to get some rough
idea of temperature. Some of our boards seem to have a temp threshold
where the problem starts occurring above a certain temp. It's not a
binary work/not work situation. Even at the high temps the board will
still work from time to time, it just fails more frequently.

As indicated by our 'best' and 'worst' boards, there is no magic
temperature number that exists across different chips, it seems to vary
quite widely.

We have at least two date codes for FX20s. I've seen the problem on
both. As I mentioned on my reply to Chris I've also seen the problem on
an FX12 development board which I presume is a different die
altogether.

I have tried bumping up Vcc a little. No notable change in the problem.

 

[Simon Peacock]

ahhh.. one of the problems with the concept is the market is too small so it
limits the availability.
The other is each company has its downloader program... part of the IDE so
you really need to integrate to that. Most of the JTAG money is spent on
production test which tends not to focus on this market.

There are a few hobby versions the price is sharp but the support is based
upon what they want to use.

I think the integration factor tends to make the vendor specific versions a
little more friendly. If you shop around, you can sometimes get a demo
board that comes with a programmer ... I got a free-bee parallel Altera one
doing just that.

Simon

"Waage" <chris@ednainc.com> wrote in message
news:1128961788.990405.9620@g47g2000cwa.googlegroups.com...

Let me clarify why I am looking for a 3rd party JTAG programming
solution.
Being relatively new to FPGA design, I am trying to determine if there
is a vendor
non-specific option available. In other words are there solutions out
there that support
JTAG programming for Xilinx, Altera, and others?

Thanks, Chris

 

[Simon Peacock]

lpm_widthu will be a generic in the scfifo .. if you look at the entity for
the scfifo it should show the available generics.

<pinod01@sympatico.ca> wrote in message
news:1129005330.788003.36580@g47g2000cwa.googlegroups.com...

To all,

I have been attempting to load a lpm component into a Modelsim
project and when I get my test bench compiled and I try to simulate, I
get the following error. Note that vosq0_prestore_fifo (my own name)
is an instantiated VHDL LPM component from Altera Quartus software
using their scfifo function. Below shows the log window. The fatal
error is shown below and is detailed because for some reaoson I don't
know where to declare a value for the LPM_WIDTHU variable? I had
thought that this was already defined? Your help would be appreciated.

Cheers
Pino

# Loading work.vosq0_prestore_fifo(rtl)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components
# Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl)
# Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior)
# Refreshing

C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
# Loading

C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated)
# Loading
C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated)
# Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl)
# Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl)
# Loading
C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body)
# Loading
C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn)
# Refreshing
C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
# Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior)
# ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a
value.
# Time: 0 ns Iteration: 0 Instance:

/tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp

onent/scfifo14

File:

QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/alte

ra_mf.vhd)

# FATAL ERROR while loading design

 

[Sandro]

Sylvain Munaut wrote:

I'm looking for some example on how to use the USER1,2 functions in a
spartan 3 (examples on virtex2/4 or others are welcomed). I know how to
instanciate the component but that's about it. I searched xilinx site
but didn't found any real example ...
...

I think this TechXclusive can help You:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=krs_blockRAM

Regards
Sandro

 

[John_H]

Even if your design runs very slow, the SDRAM module has high current
demands.

Since all the VSS and VDD pins are connected, you still need to connect
all the pins on the module. Would you consider it safe to ride in a
hot-air balloon where the basket is attached by one small rope? It may
be all that's "needed" but things will get nasty at the first stress on
that rope. The many VSS and VDD pins are primarily 1) to avoid ground
bounce where the large changes in current create a voltage differential
between the ground on your board and the ground on your module, and 2)
to keep the return currents close to the signals in order to keep
crosstalk low - if you have poor return current paths, your signals
will crosstalk significantly and your clocks will no longer be
monotonic.

Don't try for a single sided board. If you're working with
pre-manufactured SDRAM modules that aren't designed for extremely slow
slew rates, spend the money and do a *4-layer* board. If you want to
design the SDRAMs onto your own board, you have a chance at operation
with RIGOROUS design attention to reduce crosstalk and ground bounce
effects. It sounds like you don't understand the problems you face so
it would take a great deal of learning to start to apply that rigor.

A 4 layer board that connects to a solid ground plane and (mostly)
solid power planes will allow a reasonable design without the world
falling apart. It's nice to have a board where all the signals are
connected but it's even nicer if the board will work when clocked.

Bite the bullet. Spend the money.

- John_H
(posting from google at the moment)

 

[Jeff Cunningham]

Claudio wrote:

Because I have to estimate the area of different Functional Units,
using the same parameter.
For example,if I can choose from a FU that uses two 2:1 multiplexer and
four FF and another FU that uses four 2:1 multiplexer and two FF, I'd
like to prefer FU that occupies less area.

Not sure what you mean by "using the same parameter". Usually with FPGAs
you want to estimate a designs by:

LUTS
FFs
RAM
multipliers, PLLs, etc.

Having a single scalar number (like gates) to measure how much of the
FPGA a functional unit consumes is a bad idea. It's best to think of
functional unit size as a vector such as: (LUTs, FFs, blockRAM, multipliers)

You will run out of one resource before the others, depending on your
design. You will typically run out of LUTs or RAM first, and FF's last.
So in your example, the 2-LUT, 4-FF implementation is probably best.

-Jeff

 

[Ray Andraka]

Nial Stewart wrote:

"Duane Clark" <dclark@junkmail.com> wrote in message
news:knd%e.1804$Fi3.669@newssvr29.news.prodigy.net...


praveen.kantharajapura@gmail.com wrote:


Hi all,

I have a question on POR(Power on reset generation ) using FPGA.
My FPGA does not have a external Power ON reset , i am planning to
generate a Power ON reset in the FPGA only.Is it really feasible to
do this in an FPGA, and use this as the reset for my logic.
Any suggestions appreciated??


As Antti mentions, most FPGAs nowdays have an asynchronous power on reset built in. Assuming you
want an internal synchronous reset, just create a large counter which is will count down once
after an asynchronous reset. A synchronous reset would be held until the counter finishes (of
course, don't apply the synchronous reset to the countdown counter




I'd suggest not using "1111...11"s or "000...0"s as the terminal count. If
you've no external asynch reset to intiialise this counter you can't be
sure what state it'll be configured to power up in. I'd suggest that
all '1's or all '0's are the two most likely power up states.

Use "101010...1010" as your termninal count and the odds are the flip-flops
won't power up to match it.


Nial


-------------------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Actually, the power up state on most FPGAs is determined by the bit

stream. For Xilinx, flip-flops that have a set or preset input default
to '1' on power up, all others default to '0'. You can change
individual flip-flops by using the INIT attribute and generic. In any
event, the power up state is deterministic. And get this: If you have
an externally applied asynchronous reset, you can actually make that
non-deterministic if you are not careful to have the design come
synchronously out of reset. Consider the case where you have a
free-running binary counter that gets reset to all '1's by an async
reset. The next state of the counter is all zeros, however if you
release your async reset close to the active clock edge, some of the
counter bits will get thier reset released at that clock edge, and some
won't, and will therefore remain reset for one more clock cycle. The
result is your initial count is not consistently all '1's depending on
where the falling edge of reset occured with respect to the clock edge
and the differences in the routing delays and set-up times to the
individual flip-flops in the counter. An asynchronous reset is an
ansynchronous signal and must be properly synchronized by your design in
order to obtain consistent results. This is an alarmingly frequent
design error (and it is not due to metastability as some have
suggested). Generally speaking, asynchronous resets are a very bad idea
in FPGAs. Not only does this design error often trap the unwary, the
async reset also slows down the fabric of the FPGA because of the design
concessions that were made in the flip-flops to include the async reset.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759