EAGLE Netlist conversion

Active8 · Sep 29, 2004

On Tue, 21 Oct 2003 12:52:17 +0100, Paul Burridge said,

On Tue, 21 Oct 2003 02:43:12 GMT, Active8
mTHISREMOVEcolasono@earthlink.net.invalid> wrote:

Ft of the 3904 he's using is 100MHz and he's already getting a gain of 4
out of it, which is what he wants.

Fo for this deal is 96MHz min and it presents a load of 112.5 ohms to
the amp.

i was thinking in terms of stickin a choke in there so RF doesn't see
the 1k Rc and making the RF load look bigger than 50 ohms.

Thanks to all who've replied to this query. I've noted all the
responses and will be sifting through them in fine detail later today.
I've managed to find my copy of Bowick's excellent book, BTW (bottom
of my suitcase). I'm going to refresh my memory on a few things from
it before I go inquire further of the Panel.
However, I do wish to continue running simulations and need a bit of
clarification on the following final point:-
If I place a coil and capacitor in parallel in a Spice simulation, the
resulting circuit will end up with infinite impedance at resonance,
will it not? This must invalidate any results I obtain. So I need to
know what amount of resistance to add and where it should go in order
to mimic the real world losses such a tuned circuit would give rise
to. I want to get the maximum degree of accuracy, obviously. So chaps,
what's the best way of going about this? And rather more difficult;
how would one accurately model the mutual inductance of close coupling
a collector load coil to a separate coil feeding the next stage?

heh, heh. 10000000 sims. take a stab at the wire resistance of the coil

and add a few ohms.

spice syntax for k includes coupling coefficient and coils involved, so
any coils with a mutual k will do. close coupling can be k=1 or less.

use acmi or solnoid3 (notice solenoid is misspelled, so search on that)
to get a feel for how couplings (k, M) work and just guestimate your
coupling for different geometries and cores.

BTW k= M/sqrt(L1.L2) and if you use your spice program to renumber your
parts and everything goes south, change the ref designators in your k
part.

mike

Active8 · Sep 29, 2004

On Tue, 21 Oct 2003 18:02:22 +0000 (UTC), Joe McElvenney said,

Hi,

Oh, and I should have said. It isn't easy to come up with a
figure for the series loss resistance as it doesn't have much of
a relationship to the DC value except that it will be greater.
The easiest approach is to try various values of resistance in
parallel with the primary to simulate it. So when you come to the
breadboard stage you will be able to tailor the bandwidth by
fiddling it to suit; if there is sufficient gain to play with
that is.

I think the relationship is Rp x Rs = (2.pi.f.L)^2 but don't
quote me.

Cheers - Joe

i think loose coupling is the answer here, also, since that tank might

send his gain through the roof compared to what he has now. that and the
reflected impedance from the secondary.

Paul. go to coilcraft and get their spice model data. it'll give you a
bit of a clue as to how to model a coil. it even accounts for skin
effect. that and those 2 programs i recommended should get you close.

set up a parametric sweep in SS to vary your values so you can see the
difference in the what's kevin call it, waveform display? probe view?
whatever. mainly, i'd get a rough idea of the coil model and sweep the
k. kevin's transformer model might just be better than 2 coils with a k.
never looked at it, but he wrote that SS thingy to make things easier on
designers, so it's worth a look. otherwise, that coilcraft model is a
good place to start if you want a better model. but with a home-brew
coil, once you're in the ballpark via the sim, you might as well just
built it then tweak and peak.

get some rough idea of what you need and build it. make your coil
tweakable so you can add/subtract turns and vary the relation of the
secondary WRT...

mike

Joe McElvenney · Sep 29, 2004

Hi,

A coupling coefficient (k) of about 0.05 would be a fair
starting point but don't put your beer money on it. The tighter
the coupling, the greater will be the resistance coupled into the
primary, the lower the gain and the greater the bandwidth.
Alternatively the looser the coupling, the greater the gain until
you hit a critical value when it goes downhill again.

It is really like herding cats - get one parameter right and
all the rest do exactly as they wish. Mostly what works well with
RF comes from experience and pinching other peoples ideas (it is
called research.) So have a stab at what you think is reasonable,
try it and then go round and round the loop until it gets you
somewhere. Simulating something is fine but it isn't a substitute
for building it though.

Best of luck - Joe

Joe McElvenney · Sep 29, 2004

Hi,

Oh, and I should have said. It isn't easy to come up with a
figure for the series loss resistance as it doesn't have much of
a relationship to the DC value except that it will be greater.
The easiest approach is to try various values of resistance in
parallel with the primary to simulate it. So when you come to the
breadboard stage you will be able to tailor the bandwidth by
fiddling it to suit; if there is sufficient gain to play with
that is.

I think the relationship is Rp x Rs = (2.pi.f.L)^2 but don't
quote me.

Cheers - Joe

Chaos Master · Sep 29, 2004

Paul Burridge(pb@osiris1.notthisbit.co.uk) spoke, er, wrote:

I'd sooner take a chance on an unknown program than the singer
herself. From what I've seen of her pop videos, there's a far greater
chance of catching something nasty from the whore in question than
some downloaded piece of software bearing her name.

LOL

[and thankfully, news.cis.dfn.de deletes all binary messages]

--
Chaos MasterŽ - From Porto Alegre - Brazil.
Please ask for e-mail address, or even better, REPLY TO THE GROUP.
xpevo.anare@ibestvip.com.brazil - Do ROT13 to the text before the @ and replace
..brazil with .br

Paul Burridge · Sep 29, 2004

On 20 Dec 2003 17:20:58 -0800, Winfield Hill
<Winfield_member@newsguy.com> wrote:

As we explain in AoE page 83, a common-emitter-stage gain is
g_m times the load resistance. The transconductance g_m is
proportional to current (page 81), and is therefore highest
when the stage load resistor is pulled all the way down to the
emitter. Hence the gain is maximum near saturation (page 83).

Thanks, Win. That certainly figures. I'll check out the reference in a
jiffy.
Incidentally, is there a single identifiable parameter in the Spice
model of a transistor that would show up its susceptibility of going
into saturation and the criticality of correct biasing? Sorry if that
sounds like a load of bollocks but I'm still recovering from a
hangover.
--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

Jim Thompson · Sep 29, 2004

On Sun, 21 Dec 2003 12:41:29 +0000, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

On 20 Dec 2003 17:20:58 -0800, Winfield Hill
Winfield_member@newsguy.com> wrote:

As we explain in AoE page 83, a common-emitter-stage gain is
g_m times the load resistance. The transconductance g_m is
proportional to current (page 81), and is therefore highest
when the stage load resistor is pulled all the way down to the
emitter. Hence the gain is maximum near saturation (page 83).

Thanks, Win. That certainly figures. I'll check out the reference in a
jiffy.
Incidentally, is there a single identifiable parameter in the Spice
model of a transistor that would show up its susceptibility of going
into saturation and the criticality of correct biasing? Sorry if that
sounds like a load of bollocks but I'm still recovering from a
hangover.

480)460-2350 | |
| E-mail Address at Website Fax

John Woodgate · Sep 29, 2004

I read in sci.electronics.design that Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote (in <n94buvsf309frgui5od1r50uhp065ih
saa@4ax.com&gt

about 'Are small signal npn transistors really so
different from one another?', on Sun, 21 Dec 2003:

Incidentally, is there a single identifiable parameter in the Spice
model of a transistor that would show up its susceptibility of going
into saturation and the criticality of correct biasing? Sorry if that
sounds like a load of bollocks but I'm still recovering from a
hangover.

You need to keep Vce above 1 V to prevent the capacitance's getting too
big, even if Vce(sat) is only 200 mV.

Forget your Spice model and look at the device parameters that *humans*
can understand. Beta, rbb', Icmax, Vceo, Vce(sat), Rtheta, Tjmax ....
(;-)

RC amplifier stages are quite easy, if you are not pushing for really
maximum performance. I think you have a 9 V supply. OK, I'm not even
going to specify the device, beyond 'small-signal silicon, RF rather
than audio', and the operating frequency is well below fbeta. If it
isn't, common-emitter is the wrong circuit configuration anyway.

[This is an example of the 'all transistors are the same' rule of
circuit design. It takes experience to know when to apply it, and when
you must apply the 'all transistors are different' rule.]

We'll assume that you want to get 1 V peak-to-peak out; you may want
much less, but if so you could eliminate a normally important design
step. vce (the instantaneous value) mustn't go below 1 V, so we set Vce
= 1.7 V to give a bit of margin for device variations. We set Ve = 1 V
for biasing. Vc is then 2.7 V. We want as much gain as we can
reasonably get, so we'll set the Ic at 5 mA (check if possible with the
data sheet that gm or yfe hasn't dropped off at this current; it should
be approximately 39 x 5 mA = 195 mS (millisiemens).

To drop (9 - 2.7) V at 5 mA we need Rc = 1.25 kohms (nearly). If this is
the only load on the stage, the gain is gmRc = 244 times. It might not
be stable at this gain, due to feedback effects in the device and
circuit; if so, reduce Ic until it is stable. If the stage feeds a 50
ohm load, the gain is 195 x 0.05 = 9.75.

To make Ve = 1 V at Ic = 5 mA, we need Re = 200 ohms. Take beta = 50
nominal (it's an RF device; an audio device would have much higher
beta). We set the base divider current at 0.2 times Ic, i.e. 1 mA, so
that it's a good bit larger than Ib = 5mA/50. If current drain and input
impedance are not critical, we could make the current higher, so that Ic
varies less with beta.

With Ve = 1 V, Vb needs to be 1.7 V. The total base divider resistance
is 9/1 = 9 kohms. So the resistors are 1.7 kohms and 6.3 kohms.

I've left the resistor values as the non-preferred numbers that come off
the calculator. If you want to use 220 ohms, 1.8 k and 6.8 k, just
calculate back what that does to Vc. It probably won't make much
difference, but if it does, just tweak the three values until satisfied.

The input resistance is 26 x beta/Ic = 260 ohms. Maybe add 5 ohms for
rbb'; I hope that's OK for your application. AC-couple across the input
a resistor of value (265 x 50)/(265 - 50) = 62 ohms to get a 50 ohm
input resistance.

You see what happens if you try to cascade two such stages? The low
input impedance of stage 2 reduces the gain of stage 1 to 195 x 0.26 =
51. You'd probably win a bit more if you ran stage 2 at a lower current.
There is a formula for optimising the collector currents in such a
2-stage amplifier for maximum gain. Maybe you can do the mathematics.

Yes, this is a crude analysis, but it's easy and it puts you in the
right ball-park. There are lots of ways of refining it without getting
into difficult calculations. Personally, I'd build it and measure it at
this stage! But you could SPICE it first, if the lab is too cold at this
time of year.

I just hope I didn't make any stupid mistakes in the arithmetic, which I
often do.(8-(
--
Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk
Interested in professional sound reinforcement and distribution? Then go to
http://www.isce.org.uk
PLEASE do NOT copy news posts to me by E-MAIL!

Jim Thompson · Sep 29, 2004

On Sun, 21 Dec 2003 12:41:29 +0000, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

[snip]

Sorry if that
sounds like a load of bollocks but I'm still recovering from a
hangover.

480)460-2350 | |
| E-mail Address at Website Fax

Paul Burridge · Sep 29, 2004

On Sun, 21 Dec 2003 10:20:46 -0700, Jim Thompson
<invalid@invalid.invalid> wrote:

Please post your schematic and I'll write up an analysis, plus fix
your bias.

Thanks for the offer, Jim, but I'll never learn anything if other
people fix my problems for me. I know now where I went wrong (thanks
to the good folks here) and will sort the problem out for myself. That
way I won't use up too much goodwill I might yet need to call upon!

--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

Paul Burridge · Sep 29, 2004

On Sun, 21 Dec 2003 18:06:17 +0000, John Woodgate
<jmw@jmwa.demon.contraspam.yuk> wrote:

You need to keep Vce above 1 V to prevent the capacitance's getting too
big, even if Vce(sat) is only 200 mV.

Forget your Spice model and look at the device parameters that *humans*
can understand. Beta, rbb', Icmax, Vceo, Vce(sat), Rtheta, Tjmax ....
(;-)

RC amplifier stages are quite easy, if you are not pushing for really
maximum performance. I think you have a 9 V supply. OK, I'm not even
going to specify the device, beyond 'small-signal silicon, RF rather
than audio', and the operating frequency is well below fbeta. If it
isn't, common-emitter is the wrong circuit configuration anyway.

[This is an example of the 'all transistors are the same' rule of
circuit design. It takes experience to know when to apply it, and when
you must apply the 'all transistors are different' rule.]

We'll assume that you want to get 1 V peak-to-peak out; you may want
much less, but if so you could eliminate a normally important design
step. vce (the instantaneous value) mustn't go below 1 V, so we set Vce
= 1.7 V to give a bit of margin for device variations. We set Ve = 1 V
for biasing. Vc is then 2.7 V. We want as much gain as we can
reasonably get, so we'll set the Ic at 5 mA (check if possible with the
data sheet that gm or yfe hasn't dropped off at this current; it should
be approximately 39 x 5 mA = 195 mS (millisiemens).

To drop (9 - 2.7) V at 5 mA we need Rc = 1.25 kohms (nearly). If this is
the only load on the stage, the gain is gmRc = 244 times. It might not
be stable at this gain, due to feedback effects in the device and
circuit; if so, reduce Ic until it is stable. If the stage feeds a 50
ohm load, the gain is 195 x 0.05 = 9.75.

To make Ve = 1 V at Ic = 5 mA, we need Re = 200 ohms. Take beta = 50
nominal (it's an RF device; an audio device would have much higher
beta). We set the base divider current at 0.2 times Ic, i.e. 1 mA, so
that it's a good bit larger than Ib = 5mA/50. If current drain and input
impedance are not critical, we could make the current higher, so that Ic
varies less with beta.

With Ve = 1 V, Vb needs to be 1.7 V. The total base divider resistance
is 9/1 = 9 kohms. So the resistors are 1.7 kohms and 6.3 kohms.

I've left the resistor values as the non-preferred numbers that come off
the calculator. If you want to use 220 ohms, 1.8 k and 6.8 k, just
calculate back what that does to Vc. It probably won't make much
difference, but if it does, just tweak the three values until satisfied.

The input resistance is 26 x beta/Ic = 260 ohms. Maybe add 5 ohms for
rbb'; I hope that's OK for your application. AC-couple across the input
a resistor of value (265 x 50)/(265 - 50) = 62 ohms to get a 50 ohm
input resistance.

You see what happens if you try to cascade two such stages? The low
input impedance of stage 2 reduces the gain of stage 1 to 195 x 0.26 =
51. You'd probably win a bit more if you ran stage 2 at a lower current.
There is a formula for optimising the collector currents in such a
2-stage amplifier for maximum gain. Maybe you can do the mathematics.

Yes, this is a crude analysis, but it's easy and it puts you in the
right ball-park. There are lots of ways of refining it without getting
into difficult calculations. Personally, I'd build it and measure it at
this stage! But you could SPICE it first, if the lab is too cold at this
time of year.

I just hope I didn't make any stupid mistakes in the arithmetic, which I
often do.(8-(

Thanks, John. I'm not bothered about arithmetical mistakes; it's the
design process that's relevant. Your posting contains a fair bit for
me to digest, so I'll need to take some time to do it justice. There
are a couple of issues it throws up that I'll need to address in due
course...

--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

Jim Thompson · Sep 29, 2004

On Sun, 21 Dec 2003 21:06:41 +0000, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

On Sun, 21 Dec 2003 10:20:46 -0700, Jim Thompson
invalid@invalid.invalid> wrote:

Please post your schematic and I'll write up an analysis, plus fix
your bias.

Thanks for the offer, Jim, but I'll never learn anything if other
people fix my problems for me. I know now where I went wrong (thanks
to the good folks here) and will sort the problem out for myself. That
way I won't use up too much goodwill I might yet need to call upon!

480)460-2350 | |
| E-mail Address at Website Fax

Helmut Sennewald · Sep 29, 2004

"Paul Burridge" <pb@osiris1.notthisbit.co.uk> schrieb im Newsbeitrag
news:n94buvsf309frgui5od1r50uhp065ihsaa@4ax.com...

On 20 Dec 2003 17:20:58 -0800, Winfield Hill
Winfield_member@newsguy.com> wrote:

As we explain in AoE page 83, a common-emitter-stage gain is
g_m times the load resistance. The transconductance g_m is
proportional to current (page 81),

Hello Paul,
it seems for me that you have misinterpreted the last sentence.

...and is therefore highest
when the stage load resistor is pulled all the way down to the
emitter. Hence the gain is maximum near saturation (page 83).

The small signal gain is not high in saturation, it is awfully
low and distortion will also be bad.
The intention was to say that the maximum gain can be achieved if
the load resistor volaue is choosen as high as possible.
You have it at its highest value if the transistor reaches
a Vce of let's say 1V if driven with the highest intended input voltage.

Thanks, Win. That certainly figures. I'll check out the reference in a
jiffy.
Incidentally, is there a single identifiable parameter in the Spice
model of a transistor that would show up its susceptibility of going
into saturation and the criticality of correct biasing?

If you want a linear amplifier, then you avoid saturation anyway.
Spice simulation will do the job here wihout any saturation parameters.

Best Regards,
Helmut

Paul Burridge · Sep 29, 2004

On Sun, 21 Dec 2003 14:08:06 -0700, Jim Thompson
<invalid@invalid.invalid> wrote:

On Sun, 21 Dec 2003 21:06:41 +0000, Paul Burridge
pb@osiris1.notthisbit.co.uk> wrote:

On Sun, 21 Dec 2003 10:20:46 -0700, Jim Thompson
invalid@invalid.invalid> wrote:

Please post your schematic and I'll write up an analysis, plus fix
your bias.

Thanks for the offer, Jim, but I'll never learn anything if other
people fix my problems for me. I know now where I went wrong (thanks
to the good folks here) and will sort the problem out for myself. That
way I won't use up too much goodwill I might yet need to call upon!

But you'll also not learn the right way to do it.

Yeah, but I'll also look *really* stoopid. You wouldn't believe the
collector currents I was expecting to get away with. Gimme a break
will you? Everyone has to have a sense of pride - even if in my case
it's misplaced.

--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

Paul Burridge · Sep 29, 2004

On Sun, 21 Dec 2003 23:50:37 +0100, "Helmut Sennewald"
<HelmutSennewald@t-online.de> wrote:

"Paul Burridge" <pb@osiris1.notthisbit.co.uk> schrieb im Newsbeitrag
news:n94buvsf309frgui5od1r50uhp065ihsaa@4ax.com...
On 20 Dec 2003 17:20:58 -0800, Winfield Hill
Winfield_member@newsguy.com> wrote:

As we explain in AoE page 83, a common-emitter-stage gain is
g_m times the load resistance. The transconductance g_m is
proportional to current (page 81),

Hello Paul,
it seems for me that you have misinterpreted the last sentence.

...and is therefore highest
when the stage load resistor is pulled all the way down to the
emitter. Hence the gain is maximum near saturation (page 83).

The small signal gain is not high in saturation, it is awfully
low and distortion will also be bad.
The intention was to say that the maximum gain can be achieved if
the load resistor volaue is choosen as high as possible.
You have it at its highest value if the transistor reaches
a Vce of let's say 1V if driven with the highest intended input voltage.

Thanks, Win. That certainly figures. I'll check out the reference in a
jiffy.
Incidentally, is there a single identifiable parameter in the Spice
model of a transistor that would show up its susceptibility of going
into saturation and the criticality of correct biasing?

If you want a linear amplifier, then you avoid saturation anyway.
Spice simulation will do the job here wihout any saturation parameters.

Best Regards,
Helmut

--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

Paul Burridge · Sep 29, 2004

On Sun, 21 Dec 2003 23:50:37 +0100, "Helmut Sennewald"
<HelmutSennewald@t-online.de> wrote:

Hi Helmut,

The small signal gain is not high in saturation, it is awfully
low and distortion will also be bad.

I'm actually more interested in just pure gain at any expense in this
application; distortion and noise are inconsequential (it's for a
field strength meter).

The intention was to say that the maximum gain can be achieved if
the load resistor volaue is choosen as high as possible.

Yes, but that's *voltage* gain, presumably? Mind you, with a 380 ohm
100uA FSD moving coil meter as a load I don't need that much power, I
guess!

If you want a linear amplifier, then you avoid saturation anyway.
Spice simulation will do the job here wihout any saturation parameters.

I don't think Mike E. includes saturation parameters in his LTSpice
models, does he?

Anyway, Helmut, have a zer gluckliche Weinachten!
--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

Jim Thompson · Sep 29, 2004

On Sun, 21 Dec 2003 23:00:25 +0000, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

On Sun, 21 Dec 2003 14:08:06 -0700, Jim Thompson
invalid@invalid.invalid> wrote:

[snip]
But you'll also not learn the right way to do it.

Yeah, but I'll also look *really* stoopid. You wouldn't believe the
collector currents I was expecting to get away with. Gimme a break
will you? Everyone has to have a sense of pride - even if in my case
it's misplaced.

But there are no "*really* stoopid" questions. That's the way you
learn. When I was a young buck I threw away more pieces of paper than
you know ever existed.

Don't let the egotistical "bad-mouthers" scare you off.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

Chaos Master · Sep 29, 2004

Paul Camilleri said those words of wisdom from the arcane mages in
sci.electronics.cad:

That's strange. About two years ago I was looking to purchase a low cost
schematic capture and autorouter and settled on Circuit Creator Pro
(actually Visual Spice Pro from Island Logix who license the code from AMS -
or the other way round I couldn't care less).

In short, I own this product (version 5.12) amongst others. The different
components making up the suite have been written without regard to user
interface consistency, in fact, whilst the schematic capture and simulation
module has a modern look and feel about it, the auto-routing module is a
throw back to Windows 3.1 standards. But this is trivial compared to what
follows.

Look for '"simulation program" chaos master' in sci.electronics.design to see
another example of SPAM from AMS, and the spammer claimed "I am not doing spam. I
am commenting about my product".

OR just click

http://groups.google.com/groups?q=%22simulation+program%22+chaos+master&hl=pt-
BR&lr=&ie=UTF-8&selm=MPG.19fb8e5de62327d9896b8%40news.cis.dfn.de&rnum=1

(link may wrap)

--
ChaosŽ - posting from Brazil
wizard_of_yendor.666@hotmail.com
remove the number of the beast - 666

Paul Camilleri · Sep 29, 2004

Why am I not surprised?

"Chaos Master" <chaos.master_THIS.IS.A.FAKE.EMAIL.ADDRESS@pop.com.br> wrote
in message news:MPG.1a6a1fe99c7e2db798992c@news.cis.dfn.de...

Paul Camilleri said those words of wisdom from the arcane mages in
sci.electronics.cad:
That's strange. About two years ago I was looking to purchase a low cost
schematic capture and autorouter and settled on Circuit Creator Pro
(actually Visual Spice Pro from Island Logix who license the code from
AMS -
or the other way round I couldn't care less).

In short, I own this product (version 5.12) amongst others. The
different
components making up the suite have been written without regard to user
interface consistency, in fact, whilst the schematic capture and
simulation
module has a modern look and feel about it, the auto-routing module is a
throw back to Windows 3.1 standards. But this is trivial compared to
what
follows.

Look for '"simulation program" chaos master' in sci.electronics.design to
see
another example of SPAM from AMS, and the spammer claimed "I am not doing
spam. I
am commenting about my product".

OR just click

http://groups.google.com/groups?q=%22simulation+program%22+chaos+master&hl=pt-
BR&lr=&ie=UTF-8&selm=MPG.19fb8e5de62327d9896b8%40news.cis.dfn.de&rnum=1

(link may wrap)

--
ChaosŽ - posting from Brazil
wizard_of_yendor.666@hotmail.com
remove the number of the beast - 666

Jim Thompson · Sep 29, 2004

On 16 Jan 2004 13:06:00 -0800, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Jim Thompson wrote...

Not one single person has answered my MC1530 posting correctly :-(

Which post was that?

Thanks,
- Win

whill_at_picovolt-dot-com

480)460-2350 | |
| E-mail Address at Website Fax

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