EAGLE Netlist conversion

[Martin Whybrow]

"Mathew Orman" <orman@nospam.com> wrote in message
news:bhubmp$slf$1@news.onet.pl...

The first commercial sample ever built of the FTL data transmission line
will be offered on Ebay auction.
20m long 10MBit/sec performs 10x FTL data transfer and completely
falsifies
the Einstein-Lorentz space speed limit of c.
The sample will carry 200% money back guarantee of the FTL performance.

See if you can spot it at: http://www.ebay.com

Sincerely,

Mathew Orman
www.radio-faster-than-light.com
www.radio-faster-than-light.com




Mathew

Back in March I suggested why your test method gives "FTL" performance
http://www.google.co.uk/groups?q=group:sci.electronics.components+author:martin+author:whybrow&hl=en&lr=&ie=UTF-8&oe=UTF-8&selm=OsNfa.995%24wi1.654%40newsfep4-winn.server.ntli.net&rnum=4
You didn't respond to the thread; seeing as you're still hawking these
cables, how about responding now.
Martin.

--
martin<dot here>whybrow<at here>ntlworld<dot here>com

 

[Mathew Orman]

"Martin Whybrow" <a_hole_in_the_ground@ntlworld.com> wrote in message
news:sSd1b.1337$L15.619@newsfep4-winn.server.ntli.net...

"Mathew Orman" <orman@nospam.com> wrote in message
news:bhubmp$slf$1@news.onet.pl...
The first commercial sample ever built of the FTL data transmission line
will be offered on Ebay auction.
20m long 10MBit/sec performs 10x FTL data transfer and completely
falsifies
the Einstein-Lorentz space speed limit of c.
The sample will carry 200% money back guarantee of the FTL performance.

See if you can spot it at: http://www.ebay.com

Sincerely,

Mathew Orman
www.radio-faster-than-light.com
www.radio-faster-than-light.com




Mathew

Back in March I suggested why your test method gives "FTL" performance

http://www.google.co.uk/groups?q=group:sci.electronics.components+author:martin+author:whybrow&hl=en&lr=&ie=UTF-8&oe=UTF-8&selm=OsNfa.995%24wi1.654%40newsfep4-winn.server.ntli.net&rnum=4
You didn't respond to the thread; seeing as you're still hawking these
cables, how about responding now.
Martin.

--
martin<dot here>whybrow<at here>ntlworld<dot here>com

No problem.

//--------------------------------------------------------------------------
--------
Mathew

If you stick a 1Mhz signal into an unterminated transmission line, you'll
get a standing wave; your experiment proves the point neatly with the 50 Ohm
load on the coaxial line giving a 10ns delay, but what you erroneously
measured as an 800ps delay without the termination.

Martin.
//--------------------------------------------------------------------------
--------

You are describing the case where the reflected signal coincided with the
source after one full period of
360 deg phase shift.
In such case the there is no difference in relative phase between input and
output.

For such phenomena to take place in 50 Ohm coax cable at 1MHz the cable
length must be at least
on full wavelength long.
And that is 5.2 ns/m nominal, 1MHz period is 1000 ns, about 192 meters.

So as you can see it is impossible to get 1MHz standing wave in 50 Ohm coax
segment that is only 2m long.



Sincerely,

Mathew Orman
www.ultra-faster-than-light.com
www.radio-faster-than-light.com

 

[Mathew Orman]

"Martin Whybrow" <a_hole_in_the_ground@ntlworld.com> wrote in message
news:b9V1b.2047$MS5.37939@newsfep4-glfd.server.ntli.net...

"Mathew Orman" <orman@nospam.com> wrote in message
news:bi4rkq$s4k$1@news.onet.pl...

"Martin Whybrow" <a_hole_in_the_ground@ntlworld.com> wrote in message
news:sSd1b.1337$L15.619@newsfep4-winn.server.ntli.net...

"Mathew Orman" <orman@nospam.com> wrote in message
news:bhubmp$slf$1@news.onet.pl...
The first commercial sample ever built of the FTL data transmission
line
will be offered on Ebay auction.
20m long 10MBit/sec performs 10x FTL data transfer and completely
falsifies
the Einstein-Lorentz space speed limit of c.
The sample will carry 200% money back guarantee of the FTL
performance.

See if you can spot it at: http://www.ebay.com

Sincerely,

Mathew Orman
www.radio-faster-than-light.com
www.radio-faster-than-light.com




Mathew

Back in March I suggested why your test method gives "FTL" performance



http://www.google.co.uk/groups?q=group:sci.electronics.components+author:martin+author:whybrow&hl=en&lr=&ie=UTF-8&oe=UTF-8&selm=OsNfa.995%24wi1.654%40newsfep4-winn.server.ntli.net&rnum=4
You didn't respond to the thread; seeing as you're still hawking these
cables, how about responding now.
Martin.

--
martin<dot here>whybrow<at here>ntlworld<dot here>com



No problem.



//--------------------------------------------------------------------------
--------
Mathew

If you stick a 1Mhz signal into an unterminated transmission line,
you'll
get a standing wave; your experiment proves the point neatly with the 50
Ohm
load on the coaxial line giving a 10ns delay, but what you erroneously
measured as an 800ps delay without the termination.

Martin.


//--------------------------------------------------------------------------
--------

You are describing the case where the reflected signal coincided with
the
source after one full period of
360 deg phase shift.
In such case the there is no difference in relative phase between input
and
output.

For such phenomena to take place in 50 Ohm coax cable at 1MHz the cable
length must be at least
on full wavelength long.
And that is 5.2 ns/m nominal, 1MHz period is 1000 ns, about 192
meters.

So as you can see it is impossible to get 1MHz standing wave in 50 Ohm
coax
segment that is only 2m long.



Sincerely,

Mathew Orman
www.ultra-faster-than-light.com
www.radio-faster-than-light.com



Mathew

To get a standing wave, the transmission line does not need to be a
multiple
of 0.5 lambda, a much shorter line will still show a standing wave. Your
coax experiment actually demonstrates a phase difference, which will only
be
the case if the line length is not a multiple of 0.5 lambda. To really
prove
your point with this experiment, you must use a pulse generator with a
short
pulse width, < 1ns with a much longer period between pulses, perhaps 1us.
I
would be really interested to see how your experiment works under these
conditions.
Sincerely,
Martin.

--
martin<dot here>whybrow<at here>ntlworld<dot here>com

I has been published at my web-site at:
http://www.ultra-faster-than-light.com/ftlspeed.htm
Also read the patent specification showing signal spectrum requirements.
You can download free LTspice at:
http://ltspice.linear.com/software/swcadiii.exe

Have fun!

Sincerely,

Mathew Orman
www.ultra-faster-than-light.com
www.radio-faster-than-light.com

 

[Chaos Master]

tel screamed:

ALTERA ...
*PlonKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK*. Even if the program is

original(which I doubt), this isn't the right place to post it.

--
E-mail address is fake. Please reply to the group!

 

[Charles Edmondson]

Active8 wrote:

hi:

this is screwed.

i added a PSpice parameter to the Capture property sheet (with PSpice
filter selected) for a component and now that property (row/column)
won't delete and all new parts end up with the same property even in
another design/project. i can delete the value, but not the property/row
(column if i change orientation (pivot).)

if i right click the property row and select filters | hide, optional,
or undefined, it goes away, but i don't know if this is the right way to
do this. "Hide" implies that it's still there. "Optional" implies that i
don't need to give it a value. "Undefined" implies that it means
nothing. The "Value" (1k, 2u, whatever) is checked as being optional,
but it's always there.

how *should* i get rid of it and how *should* i prevent it from
happening like that again?

then we have this statement in the help on

"Add New Column/Row dialog box" for that checkbox for:

Always show this column/row in this filter

Select the checkbox to save the new column/row in the current filter.
You cannot save a new column or row in the <Current properties> filter

what the hell is "save"? every property row i create seems to become a
part of Capture itself regardless of what i do with this checkbox.

unchecking it doesn't make the new property not show up for every part
in every design/project.

look at it this way, i have to create a property "C" or whatever to use
it as a PARAMETER - according to the manual. the value would be entered
as {C}. for all i know, i should just use "Value" (nope - all parts have
a Value property) or put @C (as in DC = @DCBias for an indep V source)
or something in the property sheet for the "Value" value.

why would anyone want a property named "C" for a resistor? and no,
parasitics don't work that way. you either add another part or model the
parasitics in a subcircuit containing the primitive(?) part.

as it turns out, hiding a part property does make it *not* appear in the
current properties> filter except for a PARAMETERS part. hiding a
PARAMETERS part property did not remove it from <current properties>.
well, it didn't, but now it's gone. i added a property called "f*%$off"
to PARAMETERS and used it for a part value and it works. so the manual
is hosed (we knew that) because i didn't need to add the same property
to the part like it said.

can anyone (i bet Jim can) elucidate me regarding these "features"?

thanks,
mike

Hi Mike,
Welcome to the wonderful world of Capture. There is a logic to it, but
since I am not sure I understand it, I won't even try to explain it!

The basic idea is that if you have a filter selected, and you add a
property, then you must want that property to be added to the filter.
If you are in <current properties>, this only has the properties that
have actually been defined for this part. If you look at any of the
filters, you will often see properties that have not been defined
listed, with of course, empty contents.

The basic truth is, if you are defining a new property, go to <current
properties> to do it, and then add it to a particular filter if you need
it for all your parts in that design flow.

Confused enough, yet?

By the way, Jim wouldn't be much help. He only uses PSpice Schematics.
I expect to hear from him (audibly, without a telephone) as soon as the
next release hits him.

Charlie
Edmondson Engineering
Unique Solutions to Unusual Problems

 

[Boris Mohar]

On Mon, 25 Aug 2003 08:24:26 -0700, Charles Edmondson
<edmondson.ns@ieee.nw.org.invalid> wrote:

Hi Mike,
Welcome to the wonderful world of Capture. There is a logic to it, but
since I am not sure I understand it, I won't even try to explain it!

The basic idea is that if you have a filter selected, and you add a
property, then you must want that property to be added to the filter.
If you are in <current properties>, this only has the properties that
have actually been defined for this part. If you look at any of the
filters, you will often see properties that have not been defined
listed, with of course, empty contents.

The basic truth is, if you are defining a new property, go to <current
properties> to do it, and then add it to a particular filter if you need
it for all your parts in that design flow.

Confused enough, yet?

By the way, Jim wouldn't be much help. He only uses PSpice Schematics.
I expect to hear from him (audibly, without a telephone) as soon as the
next release hits him.

Charlie
Edmondson Engineering
Unique Solutions to Unusual Problems

What is really silly is that the filter settings are not design
specific. When I load a design form a specific customer I need their
filter loaded also.

--

Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs http://www3.sympatico.ca/borism/
Aurora, Ontario

 

[Active8]

In article <uchkkvojlgj0fu9h9fhr2gu6cria537hbb@4ax.com>,
borism@sympatico.ca says...

On Mon, 25 Aug 2003 08:24:26 -0700, Charles Edmondson
edmondson.ns@ieee.nw.org.invalid> wrote:




Hi Mike,
Welcome to the wonderful world of Capture. There is a logic to it, but
since I am not sure I understand it, I won't even try to explain it!

The basic idea is that if you have a filter selected, and you add a
property, then you must want that property to be added to the filter.
If you are in <current properties>, this only has the properties that
have actually been defined for this part. If you look at any of the
filters, you will often see properties that have not been defined
listed, with of course, empty contents.

The basic truth is, if you are defining a new property, go to <current
properties> to do it, and then add it to a particular filter if you need
it for all your parts in that design flow.

Confused enough, yet?

By the way, Jim wouldn't be much help. He only uses PSpice Schematics.
I expect to hear from him (audibly, without a telephone) as soon as the
next release hits him.

Charlie
Edmondson Engineering
Unique Solutions to Unusual Problems

What is really silly is that the filter settings are not design
specific. When I load a design form a specific customer I need their
filter loaded also.

great! and we do this how?

brs,
mike

 

[Active8]

In article <3f4a2a2b$1@news.cadence.com>,
edmondson.ns@ieee.nw.org.invalid says...

Active8 wrote:

hi:

this is screwed.

i added a PSpice parameter to the Capture property sheet (with PSpice
filter selected) for a component and now that property (row/column)
won't delete and all new parts end up with the same property even in
another design/project. i can delete the value, but not the property/row
(column if i change orientation (pivot).)

if i right click the property row and select filters | hide, optional,
or undefined, it goes away, but i don't know if this is the right way to
do this. "Hide" implies that it's still there. "Optional" implies that i
don't need to give it a value. "Undefined" implies that it means
nothing. The "Value" (1k, 2u, whatever) is checked as being optional,
but it's always there.

how *should* i get rid of it and how *should* i prevent it from
happening like that again?

then we have this statement in the help on

"Add New Column/Row dialog box" for that checkbox for:

Always show this column/row in this filter

Select the checkbox to save the new column/row in the current filter.
You cannot save a new column or row in the <Current properties> filter

what the hell is "save"? every property row i create seems to become a
part of Capture itself regardless of what i do with this checkbox.

unchecking it doesn't make the new property not show up for every part
in every design/project.

look at it this way, i have to create a property "C" or whatever to use
it as a PARAMETER - according to the manual. the value would be entered
as {C}. for all i know, i should just use "Value" (nope - all parts have
a Value property) or put @C (as in DC = @DCBias for an indep V source)
or something in the property sheet for the "Value" value.

why would anyone want a property named "C" for a resistor? and no,
parasitics don't work that way. you either add another part or model the
parasitics in a subcircuit containing the primitive(?) part.

as it turns out, hiding a part property does make it *not* appear in the
current properties> filter except for a PARAMETERS part. hiding a
PARAMETERS part property did not remove it from <current properties>.
well, it didn't, but now it's gone. i added a property called "f*%$off"
to PARAMETERS and used it for a part value and it works. so the manual
is hosed (we knew that) because i didn't need to add the same property
to the part like it said.

can anyone (i bet Jim can) elucidate me regarding these "features"?

thanks,
mike


Hi Mike,
Welcome to the wonderful world of Capture. There is a logic to it, but
since I am not sure I understand it, I won't even try to explain it!

don't blame you in this case. i've seen both logic *and* lack of logical
explanation in my life.

The basic idea is that if you have a filter selected, and you add a
property, then you must want that property to be added to the filter.
If you are in <current properties>, this only has the properties that
have actually been defined for this part. If you look at any of the
filters, you will often see properties that have not been defined
listed, with of course, empty contents.

The basic truth is, if you are defining a new property, go to <current
properties> to do it, and then add it to a particular filter if you need
it for all your parts in that design flow.

Confused enough, yet?

just a bit. that help file quote i pasted in says i can't save to
<current properties>. also, i wouldn't know how to save it from there to
a filter. also, what's the proper way to get rid of it and why is the
property getting assigned to all parts whether they're resistors or
caps, etc.

i'm also wondering about examples of properties i'd want to add for
PSpice, Capture, Layout... as i said, i found out i don't need a
property like C as long as it's in a PARAMETERS part or .PARAM
statement. no sense just using it to assign a capacitance value when i
can just double click the value on the schem. alternate part numbers?
alt footprints? help me out here...

By the way, Jim wouldn't be much help. He only uses PSpice Schematics.
I expect to hear from him (audibly, without a telephone) as soon as the
next release hits him.

heh, heh... yeah i remembered his confucius quote about orcad users
having their heads up their arses *after* i posted.

thanks,
mike

Charlie
Edmondson Engineering
Unique Solutions to Unusual Problems

 

[The real Andy]

DUH... Polygon plane - track size=grid size = solid plane.... I need some
sleep....


"The real Andy" <ihatehifitrolls@yahoo.com.au> wrote in message
news:3f4b3667$0$6528$afc38c87@news.optusnet.com.au...

I have a board, double sided, that requires a solid ground plane on the
top
layer. The hatched plane is ok, but i really need all the capacitance i
can
get so a solid plane would be just lovely. I have a few tracks routed on
the
top side so I cant really use a power plane, or can I??

TAI,

Andy

 

[Brad Velander]

Andy,
just a bit knowledge for you on the polygons in Protel. First I am
assuming you're using P99SE. To do a solid polygon you can enter "0" (zero)
for your grid size. This will precisely space your tracks according to the
width you specified, reduces database size by reducing overlap of all those
tracks. While you may see some pinholes once in a while on your monitor, I
have never found any pinholes in my Gerbers doing it in this manner for
years now.
--
Sincerely,
Brad Velander

"The real Andy" <ihatehifitrolls@yahoo.com.au> wrote in message
news:3f4b3b42$0$28119$afc38c87@news.optusnet.com.au...

DUH... Polygon plane - track size=grid size = solid plane.... I need some
sleep....

 

[The real Andy]

Many thanks Brad. You are correct in assuming I am using 99se. I am tossing
around the idea of upgrading to DXP at the moment, but its a lot of money to
upgrade to a new product when the old one works fine. I have the DXP trial
CD, but am yet to install it - or should I say, yet to find the time to
install it.

Funny you know, been using Protel since the DOS days and never needed to
pour a solid polygon plane.

Thanks again.


"Brad Velander" <spam_this@nowhere.com> wrote in message
news:kPW2b.14828$_5.370945@news1.telusplanet.net...

Andy,
just a bit knowledge for you on the polygons in Protel. First I am
assuming you're using P99SE. To do a solid polygon you can enter "0"
(zero)
for your grid size. This will precisely space your tracks according to the
width you specified, reduces database size by reducing overlap of all
those
tracks. While you may see some pinholes once in a while on your monitor, I
have never found any pinholes in my Gerbers doing it in this manner for
years now.
--
Sincerely,
Brad Velander

"The real Andy" <ihatehifitrolls@yahoo.com.au> wrote in message
news:3f4b3b42$0$28119$afc38c87@news.optusnet.com.au...
DUH... Polygon plane - track size=grid size = solid plane.... I need
some
sleep....

 

[Mark]

I've used Protel 98 on previous jobs. We use to set the polygon track
width to a value greater than the grid spacing (for example, 12 mil
tracks on a 10 mil grid) which caused the tracks to overlap during the
pour. This ensured that a solid polygon was formed and we didn't run
into the screen "pinholes" that were mentioned.

Mark

--
On Wed, 27 Aug 2003 04:53:36 GMT, "Brad Velander"
<spam_this@nowhere.com> wrote:

Andy,
just a bit knowledge for you on the polygons in Protel. First I am
assuming you're using P99SE. To do a solid polygon you can enter "0" (zero)
for your grid size. This will precisely space your tracks according to the
width you specified, reduces database size by reducing overlap of all those
tracks. While you may see some pinholes once in a while on your monitor, I
have never found any pinholes in my Gerbers doing it in this manner for
years now.
--
Sincerely,
Brad Velander

"The real Andy" <ihatehifitrolls@yahoo.com.au> wrote in message
news:3f4b3b42$0$28119$afc38c87@news.optusnet.com.au...
DUH... Polygon plane - track size=grid size = solid plane.... I need some
sleep....

 

[Active8]

In article <sZ33b.368$ED1.5@newssvr23.news.prodigy.com>,
youx@somehost.somedomain says...

What is the best way to learn PCB design and layout? I found what looks like
an awesome course offered at the U. of Wisconsin but it won't be offered until
late spring 2004 at the earliest.

Check it out: http://epdwww.engr.wisc.edu/onsite/courses/eeps20.lasso

Does anyone know of a similar program offered elsewhere in the U.S.? I'm
willing to relocate temporarily to take the course.

Regards,
AD

*Please respond to this newsgroup.


offer to hang out a few hours and help a drafting shop in exchange for

knowlege.

mike

 

[George Patrick]

Ignore wrote:

What is the best way to learn PCB design and layout? I found what looks like
an awesome course offered at the U. of Wisconsin but it won't be offered until
late spring 2004 at the earliest.

Check it out: http://epdwww.engr.wisc.edu/onsite/courses/eeps20.lasso

Does anyone know of a similar program offered elsewhere in the U.S.? I'm
willing to relocate temporarily to take the course.

Regards,
AD

*Please respond to this newsgroup.



Palomar Community College in San Diego

--
+--------------------------------+----------------------------------+
| George H. Patrick, III | Resources for PCB Designers on |
| george@pcb-designer.com | the Web - The Designer's Den |
| George.H.Patrick@tektronix.com | http://www.pcb-designer.com |
+--------------------------------+----------------------------------+
| Take what you like and leave the rest... My opinion ONLY. |
+-------------------------------------------------------------------+

 

[Jim Thompson]

On Tue, 02 Sep 2003 00:11:55 +0100, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

Hi all,

I'm a bit stumped, having had no luck whatsoever trying to find Spice
models for these two devices: 2N5109 (a BJT) and an FD700 (a diode.)
I *have* tried Googling (before anyone suggests it) and have only
found less than 2 dozen references over the last 5 years (all to other
people asking for the same thing without success.) If anyone's got the
gen on these two, then that would be splendid. Many thanks indeed.

p.

Here you go....

*$
..model Q2N5109 NPN(Is=5f Ise=10n Ne=4 Isc=10n Nc=4 Bf=90 Ikf=.2
+ Vaf=240 Cjc=5p Cje=10p Rb=.25 Re=.25 Rc=1.5 Tf=.1n Tr=20n Kf=1f)
* Texas Inst. pid=2N5109 case=TO39
* Original Library
*$

FD700 = 1N914 according to some web references:

*$
..model D1N914 D(Is=168.1E-21 N=1 Rs=.1 Ikf=0 Xti=3 Eg=1.11 Cjo=4p
+ M=.3333 Vj=.75 Fc=.5 Isr=100p Nr=2 Bv=100 Ibv=100u Tt=11.54n)
*$

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Paul Burridge]

On Mon, 01 Sep 2003 16:27:51 -0700, Jim Thompson
<Jim-T@golana-will-get-you.com> wrote:

Here you go....

[snip]

Thanks Jim, ol' buddy.
--

"I believe history will be kind to me, since I intend
to write it." - Winston Churchill

 

[Leo Sahlsten]

"Paul Burridge" <pb@osiris1.notthisbit.co.uk> wrote in message
news:0vj7lv8lq0uml8lr1rjgaq3ncc57udl08e@4ax.com...

Hi all,

I'm a bit stumped, having had no luck whatsoever trying to find Spice
models for these two devices: 2N5109 (a BJT) and an FD700 (a diode.)
I *have* tried Googling (before anyone suggests it) and have only
found less than 2 dozen references over the last 5 years (all to other
people asking for the same thing without success.) If anyone's got the
gen on these two, then that would be splendid. Many thanks indeed.

p.
--

"I believe history will be kind to me, since I intend
to write it." - Winston Churchill

* MOTOROLA 2N5109 15 V 35 MA
..SUBCKT QN5109 1 2 3
* c b e
LC 1 4 0.875E-9
LB 2 6 1.590E-9
LE 5 3 2.650E-9
CC 4 3 1.410E-12
CB 4 6 0.561E-12
Q1 4 6 5 QR33
..MODEL QR33 NPN ( BF=44 VAF=160 VAR=16.0 RC=0.69 RB=1.57
+RE=2.75 IKF=0.28E+00 ISE=0.36E-13 TF=0.111E-09
+TR=0.80E-08 ITF=0.82E-01 VTF=0.66E+01 CJC=2.758E-12
+CJE=1.822E-12 XTI=3.0 NE=1.5 ISC=0.12E-13 EG=1.11
+XTB=1.5 BR=1.14 VJC=0.75 VJE=0.75 IS=0.40E-14
+MJC=0.33 MJE=0.33 XTF=4.0 IKR=0.28E+00 KF=0.1E-14
+NC=1.7 FC=0.50 RBM=1.1 IRB=0.40E-01 XCJC=0.5 )
..ENDS
*

Rgds,
Leo

 

[Kevin Aylward]

Paul Burridge wrote:

On Mon, 01 Sep 2003 16:27:51 -0700, Jim Thompson
Jim-T@golana-will-get-you.com> wrote:

Here you go....

*$
.model Q2N5109 NPN(Is=5f Ise=10n Ne=4 Isc=10n Nc=4 Bf=90 Ikf=.2
+ Vaf=240 Cjc=5p Cje=10p Rb=.25 Re=.25 Rc=1.5 Tf=.1n Tr=20n Kf=1f)
* Texas Inst. pid=2N5109 case=TO39
* Original Library
*$

Something's amiss here. There seem to be several parameters missing
from the above model. AIUI, Spice uses default values in such
instances. However, LT don't like it and is generating error messages
citing this transistor for some reason. I've edited the control
characters from the above to conform to those LT 'expects to see' but
still no luck. :-(

FD700 = 1N914 according to some web references:

*$
.model D1N914 D(Is=168.1E-21 N=1 Rs=.1 Ikf=0 Xti=3 Eg=1.11 Cjo=4p
+ M=.3333 Vj=.75 Fc=.5 Isr=100p Nr=2 Bv=100 Ibv=100u Tt=11.54n)
*$

Is looks way to small, its the reverse leakage current after all.

LT actually comes with a model for this diode. Here it is:

.model 1N914 D(Is=2.52n Rs=0.568 N=1.752 Cjo=4p M=.4 Tt=20n Iave=200m
Vpk=75 mfg=Motorola type=silicon )

Again, it's a case of some significant differences between this one
and the one you've posted. Any ideas why? I'm baffled (as usual).

The larger N and bigger Is will act to keep the same Vd as the first
model, cant be bothered to check the exact value though. Its a common
error to set Is small to try and get a bigger diode voltage.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

 

[Mike Engelhardt]

Paul ,

.model Q2N5109 NPN(Is=5f Ise=10n Ne=4 Isc=10n Nc=4 Bf=90 Ikf=.2
+ Vaf=240 Cjc=5p Cje=10p Rb=.25 Re=.25 Rc=1.5 Tf=.1n Tr=20n Kf=1f)
* Texas Inst. pid=2N5109 case=TO39
* Original Library
*$

Something's amiss here. There seem to be several parameters missing
from the above model. AIUI, Spice uses default values in such
instances. However, LT don't like it and is generating error messages
citing this transistor for some reason. I've edited the control
characters from the above to conform to those LT 'expects to see' but
still no luck. :-(

LTspice doesn't complain about this model. Try the deck below.
It's a very generic model that doesn't use any advanced BJT options.

*
Q1 N001 N002 0 0 Q2N5109
V1 N001 0 0
I1 0 N002 0
..dc V1 0 5 1m I1 10u 100u 10u
..model Q2N5109 NPN(Is=5f Ise=10n Ne=4 Isc=10n Nc=4 Bf=90 Ikf=.2
+ Vaf=240 Cjc=5p Cje=10p Rb=.25 Re=.25 Rc=1.5 Tf=.1n Tr=20n Kf=1f)
* Texas Inst. pid=2N5109 case=TO39
* Original Library
..end

FD700 = 1N914 according to some web references:
.model D1N914 D(Is=168.1E-21 N=1 Rs=.1 Ikf=0 Xti=3 Eg=1.11 Cjo=4p
+ M=.3333 Vj=.75 Fc=.5 Isr=100p Nr=2 Bv=100 Ibv=100u Tt=11.54n)

LT actually comes with a model for this diode. Here it is:

.model 1N914 D(Is=2.52n Rs=0.568 N=1.752 Cjo=4p M=.4 Tt=20n Iave=200m
Vpk=75 mfg=Motorola type=silicon )

Again, it's a case of some significant differences between this one
and the one you've posted. Any ideas why? I'm baffled (as usual).

My guess is that the LTspice model does a better job at the forward
drop. At least its model was actually fit the the forward drop given
in a datasheet. However, breakdown is not modeled.

--Mike

 

[Brad Velander]

Jeremy,
Check on Yahoo Groups, the group name is "protel-users-resale"

--
Sincerely,
Brad Velander

"Jeremy" <allieddatasystems@yahoo.com> wrote in message
news:vnkalvosd683i40lhpqksn69inggj2m9sp@4ax.com...

I am after a Protel 99se license. Any offers? Anyone moved on and got
a license now collecting dust?

allieddatasystems _at_ yahoo _dot_ com