Driver to drive?

[Michael A. Terrell]

bitrex wrote:

WB Jim, we have our, ah, "philosophical differences" but this NG
wouldn't be the same without you.

Who else would tell me my circuits were junk?

Everyone!


--
Never piss off an Engineer!

They don't get mad.

They don't get even.

They go for over unity! ;-)

 

[Michael A. Terrell]

Jim Thompson wrote:

Well the docs tried to kill me, but I survived a very unpleasant trip.

They put a stent in my bile duct, but in recovery they discovered my
kidneys couldn't cope, and went into failure

So a one-day outpatient "procedure" ended up being a nasty 6-day
battle with helping the kidneys to recover.

Thanks to all for your good wishes!

I missed your first post, but I'll be praying for a full recovery
for you.


--
Never piss off an Engineer!

They don't get mad.

They don't get even.

They go for over unity! ;-)

 

On Thu, 23 Mar 2017 14:58:23 -0400, "Michael A. Terrell"
<mike.terrell@earthlink.net> wrote:

krw@notreal.com wrote:
On Sun, 19 Mar 2017 14:19:57 -0000 (UTC), Cursitor Doom
curd@notformail.com> wrote:

On Sat, 18 Mar 2017 20:03:50 -0400, krw wrote:

That's impossible, which is the whole "reasonable" thing.

Nothing whatsoever impossible about it!

Not at all. There is always doubt. It may be an unreasonable doubt
but there is _always_ doubt (what if the Earth was really flat?).
Hence, "beyond reasonable doubt".


What do you think of this sorry piece of work?

http://www.wftv.com/news/local/ayala-to-explain-why-she-wont-seek-death-penalty-against-murder-suspect-markeith-loyd/503151996

She should *immediately* be removed from office for violating her oath
of office to follow the constitution and laws of the state of Florida.
That decision isn't hers to make.

 

On Thu, 23 Mar 2017 15:49:28 -0400, "Michael A. Terrell"
<mike.terrell@earthlink.net> wrote:

Kevin Aylward wrote:
"Cursitor Doom" wrote in message newsaruc8$b5u$4@dont-email.me...

On Mon, 20 Mar 2017 20:23:37 -0400, krw wrote:

It's obvious you're illiterate.

no point in reading further

I feel I should at this point apologise for the remarks made by my fellow
countryman, Kev. He and the poster "tabbypurr" are both singularly ill-
informed on this issue. Their ignorance is only matched by their
indefatigable ability to repeat the same dogma over and over and over
again. You will never win an argument against them; they simply won't
listen to reason. Do yourself a big favour and mark the thread "ignore"
in your newsreader. You'll save yourself from a huge amount of wasted
time.

I appreciate the support.

I did find the word "illiterate" somewhat amusing in as much as that it
is typically the "intellectuals" that present the reasoned arguments on
ethical issues rather than the redneck southerners.


I would rather have a 'redneck' on my side in a fight, than an
'ineffectual' intellectual.

Kevin is just another leftist bigot.

 

[amdx]

On 3/23/2017 6:48 PM, dagmargoodboat@yahoo.com wrote:

On Thursday, March 23, 2017 at 2:52:11 PM UTC-4, amdx wrote:
On 3/21/2017 9:28 AM, dagmargoodboat@yahoo.com wrote:
On Tuesday, March 21, 2017 at 8:27:51 AM UTC-4, amdx wrote:
On 3/21/2017 2:19 AM, dagmargoodboat@yahoo.com wrote:
On Monday, March 20, 2017 at 9:49:55 PM UTC-4, dagmarg...@yahoo.com wrote:
On Monday, March 20, 2017 at 6:15:37 PM UTC-4, amdx wrote:

Can I tell this is working if my 1X gain increases?
The 17 to 1 divider of the input cap and the gate capacitance and the 17
times gain of the amplifier equals 1X.

Say I get 80% T1 gate cancellation (by moving the 20Meg), now we have
effectively 1pf.
1pf/0.3pf = 3.33 and the amp gain 17 / 3.33 = 5.1
So I would think my total circuit gain would increase to 5.1.
Or do I not get it?

You've got it perfectly. I don't expect a very large improvement from
bootstrapping the 20M alone though--a resistor's capacitance is pretty
low already, and two in series, even lower.

Your author's figures are inconsistent. He starts saying the input
capacitance is 1.4pF and the input coupling cap is 0.3pF, but then he
says the 0.3pF and FET T1's capacitances form a 17:1 divider. That can't
all be true--0.3pF should form a 5.7:1 divider with a 1.4pF input, not
17:1.

When I guesstimate a 5x improvement, I'm banking on the 17:1 being true,
c.in(eff) being 5pF, and getting that down to 1pF, roughly, with the
circuit I sketched.

If you're already really at 1.4pF the improvement will only be 1.0pF/1.4pF,
and not 1.0pF/5pF.

As I said before, a better buffer could do better--you could tweak the
bootstrap to perfect null--but then chances are you'd have an oscillator.

What I posted seemed like a reasonable compromise for a first try.

I thought about this a bit and came up with an improved follower.

The main limitation of the previous circuit was the FET's poor performance
as a voltage-follower. Unaided, the T1 has a gain of about 0.6. That hits
our bootstrapping from all sides. First, c(gs) (the largest capacitance)
is only bootstrapped by 60%, leaving 40% of the BC547C's ~5pF c(gs). Next,
we use that voltage to drive our less-than-unity Q2, which drives less-than-
unity Q1. This all adds up.

Changing T1's load to a current sink makes T1 into a much better follower,
increasing voltage gain from 0.6 to about 0.95. The better 'follower'
action now bootstraps away nearly all of c(gs) (T1's largest capacitance),
and gives us a better signal to drive the drain bootstrap as well. Good,
good, and good. And not terribly much trouble to do, either.

Vdd Vdd
-+- -+-
| |
| [22k] R5
Q1 \| |
BC547B |---+-------.
.<| | |
| [47k] R6 |
(shield) T1 |--' | |
------ BF256C | === |
----------+----->|--. |
---+-- | | Vdd --- C2
| | | -+- ---100n
| | | | |
| R1 [10M] | |/ Q2 |
| | +---| BC547B |
| | | |>. |
| | R3 [470] | |
| | | | | C3
| | | | | 100n
| +----||---+-----+-------+-----||---> to ampl.
| | C1 | |
| R2 [10M] 100pF R4 [470] --- C4
| | | --- 100n
| === === |
| |
'------------------------------+
|
Cin ~200fF [2.2k] R7
|
===

Cheers,
James Arthur

Thanks for the time.
As it is now constructed the enclosure is the shield.
Is that good or bad? ie. Should the enclosure be isolated from the shield?

The enclosure should be grounded! Let's not confuse that with
bootstrapping the input coax's shield (which you'll only do _if_
you use coax).

So yes, the enclosure should be isolated from the driven shield that is
shown in the schematic.

(My shield-driver is pretty wimpy, only suitable for a very short, low-
capacitance run. Might need beefing up.)

If you build it, it'll be fun to hear what output voltage you get from
this stage when you drive your 0.3pF input cap with, say, 50mV AC. If
you put 50mV into the 0.3pF and get 25mV out the back end, that means
our net input capacitance after bootstrapping is about the same as your
series 0.3pF.

Cheers,
James Arthur


OK, The circuit is built, I haven't tested it. I'm testing just the
circuit just the circuit posted.
I want to know how to drive the input.
Say I connect a 9 inch piece of RG58, that's 19pf, is that to much?
I want to drive it with a 50 ohm sig/gen.
Can I terminate the RG58 with 50 ohms or do I need to feed the RG58 with
a high impedance? Maybe a series 1Mohm.
I don't see how to separate the sig/gen cable from the input cable.
May I just need to connect it to the LC and see what I get.
Thank, Mikek


How about one step at a time? First, calibrate your input cap:

C1
.---. 0.3pF
| ~ |--------||----+----> A
'---' |
10V --- C2
--- 100pF
|
===

Measure V(A), calculate (don't forget to add your measuring instrument's
c.in to C2).

Easier said than done.
I have a pretty good capacitance tester. I made a .3pf cap :-/
and used an 82pf cap plus the probe, together they measured 106.7pf.
I applied 16Vpp and measured 0.06Vpp at A.
16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4
That makes my cap look like 0.4pf

I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I
make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in.
My cap is 1/8" diameter or 0.01227 sq in.
So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia.
So fringing and lead to lead capacitance, I'm in the ballpark, just not
sure what field.
If you have any suggestions, I'm willing.
Way past my bedtime, good night.
Mikek

PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in
number online.

Then no coax:

T1 |--
.---. 0.3pF |
| ~ |--------||------>|--.
'---' | T1.s
1V
Put a known voltage into the 0.3pF, then measure the voltage at T1.s.

Kleijer says his gain at that node is 1/17th.

If things are good this far, add a short piece of coax to the input with
the shield grounded, and try. Then try with the shield driven. Then Bob's
yer Grandma. Or something.

Cheers,
James Arthur

---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus

 

[rickman]

On 3/24/2017 12:58 AM, amdx wrote:

On 3/23/2017 6:48 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, March 23, 2017 at 2:52:11 PM UTC-4, amdx wrote:
On 3/21/2017 9:28 AM, dagmargoodboat@yahoo.com wrote:
On Tuesday, March 21, 2017 at 8:27:51 AM UTC-4, amdx wrote:
On 3/21/2017 2:19 AM, dagmargoodboat@yahoo.com wrote:
On Monday, March 20, 2017 at 9:49:55 PM UTC-4,
dagmarg...@yahoo.com wrote:
On Monday, March 20, 2017 at 6:15:37 PM UTC-4, amdx wrote:

Can I tell this is working if my 1X gain increases?
The 17 to 1 divider of the input cap and the gate capacitance
and the 17
times gain of the amplifier equals 1X.

Say I get 80% T1 gate cancellation (by moving the 20Meg), now we
have
effectively 1pf.
1pf/0.3pf = 3.33 and the amp gain 17 / 3.33 = 5.1
So I would think my total circuit gain would increase to 5.1.
Or do I not get it?

You've got it perfectly. I don't expect a very large improvement
from
bootstrapping the 20M alone though--a resistor's capacitance is
pretty
low already, and two in series, even lower.

Your author's figures are inconsistent. He starts saying the input
capacitance is 1.4pF and the input coupling cap is 0.3pF, but
then he
says the 0.3pF and FET T1's capacitances form a 17:1 divider.
That can't
all be true--0.3pF should form a 5.7:1 divider with a 1.4pF
input, not
17:1.

When I guesstimate a 5x improvement, I'm banking on the 17:1
being true,
c.in(eff) being 5pF, and getting that down to 1pF, roughly, with the
circuit I sketched.

If you're already really at 1.4pF the improvement will only be
1.0pF/1.4pF,
and not 1.0pF/5pF.

As I said before, a better buffer could do better--you could
tweak the
bootstrap to perfect null--but then chances are you'd have an
oscillator.

What I posted seemed like a reasonable compromise for a first try.

I thought about this a bit and came up with an improved follower.

The main limitation of the previous circuit was the FET's poor
performance
as a voltage-follower. Unaided, the T1 has a gain of about 0.6.
That hits
our bootstrapping from all sides. First, c(gs) (the largest
capacitance)
is only bootstrapped by 60%, leaving 40% of the BC547C's ~5pF
c(gs). Next,
we use that voltage to drive our less-than-unity Q2, which drives
less-than-
unity Q1. This all adds up.

Changing T1's load to a current sink makes T1 into a much better
follower,
increasing voltage gain from 0.6 to about 0.95. The better
'follower'
action now bootstraps away nearly all of c(gs) (T1's largest
capacitance),
and gives us a better signal to drive the drain bootstrap as
well. Good,
good, and good. And not terribly much trouble to do, either.

Vdd Vdd
-+- -+-
| |
| [22k] R5
Q1 \| |
BC547B |---+-------.
.<| | |
| [47k] R6 |
(shield) T1 |--' | |
------ BF256C | === |
----------+----->|--. |
---+-- | | Vdd --- C2
| | | -+- ---100n
| | | | |
| R1 [10M] | |/ Q2 |
| | +---| BC547B |
| | | |>. |
| | R3 [470] | |
| | | | | C3
| | | | | 100n
| +----||---+-----+-------+-----||---> to ampl.
| | C1 | |
| R2 [10M] 100pF R4 [470] --- C4
| | | --- 100n
| === === |
| |
'------------------------------+
|
Cin ~200fF [2.2k] R7
|
===

Cheers,
James Arthur

Thanks for the time.
As it is now constructed the enclosure is the shield.
Is that good or bad? ie. Should the enclosure be isolated from the
shield?

The enclosure should be grounded! Let's not confuse that with
bootstrapping the input coax's shield (which you'll only do _if_
you use coax).

So yes, the enclosure should be isolated from the driven shield that is
shown in the schematic.

(My shield-driver is pretty wimpy, only suitable for a very short, low-
capacitance run. Might need beefing up.)

If you build it, it'll be fun to hear what output voltage you get from
this stage when you drive your 0.3pF input cap with, say, 50mV AC. If
you put 50mV into the 0.3pF and get 25mV out the back end, that means
our net input capacitance after bootstrapping is about the same as your
series 0.3pF.

Cheers,
James Arthur


OK, The circuit is built, I haven't tested it. I'm testing just the
circuit just the circuit posted.
I want to know how to drive the input.
Say I connect a 9 inch piece of RG58, that's 19pf, is that to much?
I want to drive it with a 50 ohm sig/gen.
Can I terminate the RG58 with 50 ohms or do I need to feed the RG58 with
a high impedance? Maybe a series 1Mohm.
I don't see how to separate the sig/gen cable from the input cable.
May I just need to connect it to the LC and see what I get.
Thank, Mikek


How about one step at a time? First, calibrate your input cap:

C1
.---. 0.3pF
| ~ |--------||----+----> A
'---' |
10V --- C2
--- 100pF
|
===

Measure V(A), calculate (don't forget to add your measuring instrument's
c.in to C2).


Easier said than done.
I have a pretty good capacitance tester. I made a .3pf cap :-/
and used an 82pf cap plus the probe, together they measured 106.7pf.
I applied 16Vpp and measured 0.06Vpp at A.
16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4
That makes my cap look like 0.4pf

I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I
make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in.
My cap is 1/8" diameter or 0.01227 sq in.
So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia.
So fringing and lead to lead capacitance, I'm in the ballpark, just not
sure what field.
If you have any suggestions, I'm willing.
Way past my bedtime, good night.
Mikek

PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in
number online.

Don't they give a dielectric constant? That is important in RF work as
it impacts signal speed, impedance, etc. From that you can calculate
the capacitance (ignoring fringe effects). I'm not familiar with
calculating fringe effects, but it's hard to imagine there wouldn't be a
simple way to figure that out for a pair of round disks separated by a
dielectric. But I don't know for sure, even this might best be done
with a 3D field solver. lol

I think the parasitic capacitance of the other parts of the circuit
would be in this same ballpark, so I don't know how you would be able to
get close to the true value other than by measuring.

I will say I am impressed with what you have done so far. As Edison
said, "invention is 1% inspiration and 99% perspiration".

--

Rick C

 

On Thursday, 23 March 2017 06:42:41 UTC, Kevin Aylward wrote:

wrote in message news:0v46dc9bgb5pjf6lpc3jej19tl97qpu4db@4ax.com...

model, Jesus, emphatically instructing them that "thou shall not kill".
More, stunningly the xtians claim that it is they that there the
morally
righteous ones.

The perp gave up his right to life by taking that of another. End of
story.

Ok. After the Jury, judge and executioners have killed the
aforementioned,
we can now kill said Jury, judge and executioners because they have now
killed someone, or taken deliberate action that resulted in the death of
someone. i.e. murdered someone.

It's obvious you're illiterate.

Its obvious that you can't understand the issues involved.



Ho humm.

OK, you're not interested in the facts. Therefore, the only
conclusion possible is that you're trolling. Meet Slowman.

I gave you facts.

Fact: a Jury/Judge/executioner orders/kills someone not in defence of a
life.

Appropriate definition of Murder: premeditated killing/ordering of killing
of someone not in protection of a life

As I said, it is pretty stunning that anyone, if even if they wanted to add
weasel words around the definition to enable disagreement of my point, is
utterly incapable of understanding the essence of the point being made.

I read your continuing ad-hominem attacks, yet you have failed to produce
any argument, let alone an intellectual argument as to why "The perp gave up
his right to life by taking that of another" does not apply to to the
state's Jury/Judge/executioner. It satisfies your claim.

Defend you arguments, or go away. You are only embarrassing yourself.

You're wasting your time with him. I'm all for sensible discussion but once k & CD resort to stupid bs I don't see the point.


NT

 

On Thursday, 23 March 2017 19:49:33 UTC, Michael Terrell wrote:

Kevin Aylward wrote:
"Cursitor Doom" wrote in message newsaruc8$b5u$4@dont-email.me...
On Mon, 20 Mar 2017 20:23:37 -0400, krw wrote:

It's obvious you're illiterate.

no point in reading further

I feel I should at this point apologise for the remarks made by my fellow
countryman, Kev. He and the poster "tabbypurr" are both singularly ill-
informed on this issue. Their ignorance is only matched by their
indefatigable ability to repeat the same dogma over and over and over
again. You will never win an argument against them; they simply won't
listen to reason. Do yourself a big favour and mark the thread "ignore"
in your newsreader. You'll save yourself from a huge amount of wasted
time.

I appreciate the support.

He's offering bs not support. In case there's any confusion I agree with kevin's conclusions.


NT

 

On Friday, 24 March 2017 11:58:28 UTC, tabby wrote:

On Thursday, 23 March 2017 06:42:41 UTC, Kevin Aylward wrote:

Defend you arguments, or go away. You are only embarrassing yourself.

You're wasting your time with him. I'm all for sensible discussion but once k & CD resort to stupid bs I don't see the point.


NT

* krw I mean.


NT

 

[Jeroen Belleman]

On 2017-03-23 20:49, Michael A. Terrell wrote:

I would rather have a 'redneck' on my side in a fight, than an
'ineffectual' intellectual.

A redneck can help you win a fight, but you need the intellectuals
to have a chance to win the war.

Jeroen Belleman

 

On Saturday, March 25, 2017 at 12:07:48 AM UTC+11, Michael Terrell wrote:

Jeroen Belleman wrote:
On 2017-03-23 20:49, Michael A. Terrell wrote:


I would rather have a 'redneck' on my side in a fight, than an
'ineffectual' intellectual.


A redneck can help you win a fight, but you need the intellectuals
to have a chance to win the war.

How many intellectuals put their lives on the line, to win that war?
They sit in offices and decide what are acceptable levels of casualties
among the actual fighters.

Not all of them

https://en.wikipedia.org/wiki/Alan_Blumlein

He was one of the British radar experts (amongst his numerous achievements) and he died in 1942 when the Halifax bomber that was carrying him and an H2S radar system which he and his crew were live-testing crashed on landing.

When I was working at EMI Central Research I met one of the guys - Bill Percival - who had worked with him then and before WW2. I didn't make a fuss about it but the historical significance did register.

A few years earlier, at Plessey Pacific in Australia, W.A.S. Butement was my boss. He'd done interesting stuff when he was younger, but wasn't all that impressive in 1970.

https://en.wikipedia.org/wiki/W._A._S._Butement

--
Bill Sloman, Sydney

 

[amdx]

On 3/24/2017 12:13 AM, rickman wrote:

On 3/24/2017 12:58 AM, amdx wrote:
On 3/23/2017 6:48 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, March 23, 2017 at 2:52:11 PM UTC-4, amdx wrote:
On 3/21/2017 9:28 AM, dagmargoodboat@yahoo.com wrote:
On Tuesday, March 21, 2017 at 8:27:51 AM UTC-4, amdx wrote:
On 3/21/2017 2:19 AM, dagmargoodboat@yahoo.com wrote:
On Monday, March 20, 2017 at 9:49:55 PM UTC-4,
dagmarg...@yahoo.com wrote:
On Monday, March 20, 2017 at 6:15:37 PM UTC-4, amdx wrote:

Can I tell this is working if my 1X gain increases?
The 17 to 1 divider of the input cap and the gate capacitance
and the 17
times gain of the amplifier equals 1X.

Say I get 80% T1 gate cancellation (by moving the 20Meg), now we
have
effectively 1pf.
1pf/0.3pf = 3.33 and the amp gain 17 / 3.33 = 5.1
So I would think my total circuit gain would increase to 5.1.
Or do I not get it?

You've got it perfectly. I don't expect a very large improvement
from
bootstrapping the 20M alone though--a resistor's capacitance is
pretty
low already, and two in series, even lower.

Your author's figures are inconsistent. He starts saying the input
capacitance is 1.4pF and the input coupling cap is 0.3pF, but
then he
says the 0.3pF and FET T1's capacitances form a 17:1 divider.
That can't
all be true--0.3pF should form a 5.7:1 divider with a 1.4pF
input, not
17:1.

When I guesstimate a 5x improvement, I'm banking on the 17:1
being true,
c.in(eff) being 5pF, and getting that down to 1pF, roughly, with
the
circuit I sketched.

If you're already really at 1.4pF the improvement will only be
1.0pF/1.4pF,
and not 1.0pF/5pF.

As I said before, a better buffer could do better--you could
tweak the
bootstrap to perfect null--but then chances are you'd have an
oscillator.

What I posted seemed like a reasonable compromise for a first try.

I thought about this a bit and came up with an improved follower.

The main limitation of the previous circuit was the FET's poor
performance
as a voltage-follower. Unaided, the T1 has a gain of about 0.6.
That hits
our bootstrapping from all sides. First, c(gs) (the largest
capacitance)
is only bootstrapped by 60%, leaving 40% of the BC547C's ~5pF
c(gs). Next,
we use that voltage to drive our less-than-unity Q2, which drives
less-than-
unity Q1. This all adds up.

Changing T1's load to a current sink makes T1 into a much better
follower,
increasing voltage gain from 0.6 to about 0.95. The better
'follower'
action now bootstraps away nearly all of c(gs) (T1's largest
capacitance),
and gives us a better signal to drive the drain bootstrap as
well. Good,
good, and good. And not terribly much trouble to do, either.

Vdd Vdd
-+- -+-
| |
| [22k] R5
Q1 \| |
BC547B |---+-------.
.<| | |
| [47k] R6 |
(shield) T1 |--' | |
------ BF256C | === |
----------+----->|--. |
---+-- | | Vdd --- C2
| | | -+- ---100n
| | | | |
| R1 [10M] | |/ Q2 |
| | +---| BC547B |
| | | |>. |
| | R3 [470] | |
| | | | | C3
| | | | | 100n
| +----||---+-----+-------+-----||---> to ampl.
| | C1 | |
| R2 [10M] 100pF R4 [470] --- C4
| | | --- 100n
| === === |
| |
'------------------------------+
|
Cin ~200fF [2.2k] R7
|
===

Cheers,
James Arthur

Thanks for the time.
As it is now constructed the enclosure is the shield.
Is that good or bad? ie. Should the enclosure be isolated from the
shield?

The enclosure should be grounded! Let's not confuse that with
bootstrapping the input coax's shield (which you'll only do _if_
you use coax).

So yes, the enclosure should be isolated from the driven shield
that is
shown in the schematic.

(My shield-driver is pretty wimpy, only suitable for a very short,
low-
capacitance run. Might need beefing up.)

If you build it, it'll be fun to hear what output voltage you get from
this stage when you drive your 0.3pF input cap with, say, 50mV AC. If
you put 50mV into the 0.3pF and get 25mV out the back end, that means
our net input capacitance after bootstrapping is about the same as
your
series 0.3pF.

Cheers,
James Arthur


OK, The circuit is built, I haven't tested it. I'm testing just the
circuit just the circuit posted.
I want to know how to drive the input.
Say I connect a 9 inch piece of RG58, that's 19pf, is that to much?
I want to drive it with a 50 ohm sig/gen.
Can I terminate the RG58 with 50 ohms or do I need to feed the RG58
with
a high impedance? Maybe a series 1Mohm.
I don't see how to separate the sig/gen cable from the input cable.
May I just need to connect it to the LC and see what I get.
Thank, Mikek


How about one step at a time? First, calibrate your input cap:

C1
.---. 0.3pF
| ~ |--------||----+----> A
'---' |
10V --- C2
--- 100pF
|
===

Measure V(A), calculate (don't forget to add your measuring instrument's
c.in to C2).


Easier said than done.
I have a pretty good capacitance tester. I made a .3pf cap :-/
and used an 82pf cap plus the probe, together they measured 106.7pf.
I applied 16Vpp and measured 0.06Vpp at A.
16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4
That makes my cap look like 0.4pf

I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I
make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in.
My cap is 1/8" diameter or 0.01227 sq in.
So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia.
So fringing and lead to lead capacitance, I'm in the ballpark, just not
sure what field.
If you have any suggestions, I'm willing.
Way past my bedtime, good night.
Mikek

PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in
number online.

Don't they give a dielectric constant? That is important in RF work as
it impacts signal speed, impedance, etc. From that you can calculate
the capacitance (ignoring fringe effects).

Yes the dielectric constant is 2.20. I don't know how to figure the
capacitance from that, so it was easier to measure it than search out
how to calculate it.

I'm not familiar with calculating fringe effects, but it's hard to imagine
there wouldn't be a simple way to figure that out for a pair of round disks

separated by a dielectric. But I don't know for sure, even this might
best be done

with a 3D field solver. lol

Over my pay grade.

I think the parasitic capacitance of the other parts of the circuit
would be in this same ballpark, so I don't know how you would be able to
get close to the true value other than by measuring.

I thought of a different way physically to connect this up for
measurement, basically just tightening up the circuit. It should
eliminate the 60 Hz I had on the measurement, and maybe eliminate
some parasitic capacitance.

I will say I am impressed with what you have done so far. As Edison
said, "invention is 1% inspiration and 99% perspiration".

Let's not get carried away, all I did was build someone else's circuit.
Now that I'm mostly retired, I get a chance to do these things. The
real stumbling block is getting off the computer and doing them.
By the time I check my email, read the usenet groups check stock
futures, check my homepage, read a financial guru's page, check a
crystal radio forum and read another financial forum, 4 hours are gone
from my day. OK, going to the bench now. Well, after I check the market
futures!
Mikek



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On Friday, March 24, 2017 at 10:13:18 AM UTC-4, amdx wrote:

On 3/24/2017 8:44 AM, amdx wrote:
On 3/23/2017 11:58 PM, amdx wrote:
On 3/23/2017 6:48 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, March 23, 2017 at 2:52:11 PM UTC-4, amdx wrote:

OK, The circuit is built, I haven't tested it. I'm testing just the
circuit just the circuit posted.
I want to know how to drive the input.
Say I connect a 9 inch piece of RG58, that's 19pf, is that to much?
I want to drive it with a 50 ohm sig/gen.
Can I terminate the RG58 with 50 ohms or do I need to feed the RG58
with
a high impedance? Maybe a series 1Mohm.
I don't see how to separate the sig/gen cable from the input cable..
May I just need to connect it to the LC and see what I get.
Thank, Mikek


How about one step at a time? First, calibrate your input cap:

C1
.---. 0.3pF
| ~ |--------||----+----> A
'---' |
10V --- C2
--- 100pF
|
==
Measure V(A), calculate (don't forget to add your measuring instrument's
c.in to C2).


Easier said than done.
I have a pretty good capacitance tester. I made a .3pf cap :-/
and used an 82pf cap plus the probe, together they measured 106.7pf.
I applied 16Vpp and measured 0.06Vpp at A.
16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4
That makes my cap look like 0.4pf

Yes.

I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I
make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in.
My cap is 1/8" diameter or 0.01227 sq in.
So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia.
So fringing and lead to lead capacitance, I'm in the ballpark, just not
sure what field.
If you have any suggestions, I'm willing.
Way past my bedtime, good night.
Mikek

You're close enough for our purposes. The first measurement may be being
affected by stray capacitances, dunno. In the end all we'll care about
(when you use this thing) is getting 100mV out for 100mV in.

PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in
number online.


I got out my better probe (Tek 6122 11pf) and made curly cues for the
probe tip.
Here's a picture of the tightened up circuit.
https://www.dropbox.com/s/sixe91dvxs40f1z/P1010193.JPG?dl=0


The new total capacitance, probe plus 82pf cap is 94pf. (measured)
16Vpp input, V(A) is 0.068Vpp. Then 16/0.068 = 235.3
235.3 / 94 = 2.5pf.

No, that should be 94pF * (.068V / 16V) = 0.4 pF.

This is a tighter measurement and also agrees with my calculation of
0.253 that I calculated for the pcb capacitance per sq in.
Rather than fight with a new piece of pcb material just slightly over
1/8" in diameter.
I'm going to go with a new value input cap of 0.25pf.
If you see this as a bad idea, let me know and I'll fumble around
and make a larger cap. I used a 1/8' paper punch to make this cap,
I could use a 1/4" and grind it down, but it's a chore.

It looks to me like your input cap is good, and 0.4pF. No need to change
it.

Now for the next measurement.
Is this with a T1 in the completed circuit?
Or, do I add the probe + 82pf back in to get a ratio?
Ya, I'm now confused.

Yes, it's time to use your calibrated in the completed, working circuit.
We'll want to measure the a.c. signal at the FET source first, then the
FET's drain.

I think we might want the voltage at the gate, but I
think that would be an impossible measurement. ie putting 11pf
probe across a 0.3pf cap ?
Thanks, Mikek



Ok, I tried this, out of circuit, just the FET.



T1 |--
.---. 0.3pF |
| ~ |--------||------>|--.
'---' | T1.s = 0.06Vpp
16Vpp |
|---probe tip
82pf –--
--- 12pf
|---probe ground
|
---
///

So, 16Vpp / 0.6Vpp = 266.6
266.6 / 94 = 2.84pf
2.84pf - 0.3pf = 2.54pf for the Cgs.
I think that's to low, I thought it was 5pf,
but I'm looking for your thoughts.

Thanks Mikek

Sorry, I wasn't clear enough. We're measuring in-circuit.

To check the effective input capacitance we want to know the attenuation
of the input a.c. voltage, as measured at point (A).

Rationale: The input voltage will be divided across your 0.40pF input
capacitor and the circuit's input capacitance:

Ccoupling
0.40pF .. .. ..
Vin >---||----:--+--o V(A)
: |
: --- Ceff
: ---
: |
: == '.. .. ..

We can't measure at the gate--that's too high impedance--so we're measuring
at FET T1's source terminal, point (A).

If 63% of the voltage is lost across the 0.40pF series cap, then the
effective input capacitance is dropping 37%, which means the series
cap is 63% of the total reactance and Ceff is 37% of the total reactance.

More formally, Ceff = 0.40pF * (Vin - V(A)) / V(A).

(We're trying to measure Ceff.)

You can measure Vac at the FET source on the original circuit for comparison,
too. That's a good way to assess the relative performance of the new circuit
vs. the original (after correcting for any differences in the input coupling
caps, of course.)

(Kleijer said his input division ratio was 17:1, indicating his circuit's
input capacitance (Ceff) was 16 units, and his coupling cap was 1 unit of
capacitance, or Ceff = 16 x Ccoupling.)

We want to know the a.c. voltage @ (B) just to gauge how well our drain
portion of the bootstrap is working. The closer Vac(B) is to Vac(A), the
better we're doing. 1:1 would be ideal. 0.9 would be okay, less than 0.9
indicates a problem.

Here's the circuit, for reference, with probe points (A) and (B) marked:

(Remember, I'm showing a boot-strapped coax on the input, but we're not
using that yet. We want to keep the comparisons apples-to-apples, and
change only one thing at a time.)

+12V +12V
-+- -+-
| |
| [22k] R5
Q1 \| |
BC547B |---+-------.
.<| | |
| | |
(B)| [47k] R6 |
(shield) T1 |--' | |
----- BF256C | === |
>----------||-+----->|--. |
---+- .4pF| (A)| Vdd --- C2
| | | -+- ---100n
| | | | |
| R1 [10M] | |/ Q2 |
| | +---| BC547B |
| | | |>. |
| | R3 [470] | |
| | | | | C3
| | | | | 100n
| +----||---+-----+-------+-----||---> to ampl.
| | C1 | |
| R2 [10M] 100pF R4 [470] --- C4
| | | --- 100n
| === === |
| |
'------------------------------+
|
Cin ~200fF [2.2k] R7
|
==HTH,
James Arthur

 

[Michael A. Terrell]

krw@notreal.com wrote:

On Thu, 23 Mar 2017 14:58:23 -0400, "Michael A. Terrell"
mike.terrell@earthlink.net> wrote:

krw@notreal.com wrote:
On Sun, 19 Mar 2017 14:19:57 -0000 (UTC), Cursitor Doom
curd@notformail.com> wrote:

On Sat, 18 Mar 2017 20:03:50 -0400, krw wrote:

That's impossible, which is the whole "reasonable" thing.

Nothing whatsoever impossible about it!

Not at all. There is always doubt. It may be an unreasonable doubt
but there is _always_ doubt (what if the Earth was really flat?).
Hence, "beyond reasonable doubt".


What do you think of this sorry piece of work?

http://www.wftv.com/news/local/ayala-to-explain-why-she-wont-seek-death-penalty-against-murder-suspect-markeith-loyd/503151996

She should *immediately* be removed from office for violating her oath
of office to follow the constitution and laws of the state of Florida.
That decision isn't hers to make.

The Governor has removed her from the case, but she want to sue over it.

Disbar the jackass.


--
Never piss off an Engineer!

They don't get mad.

They don't get even.

They go for over unity! ;-)

 

[Michael A. Terrell]

Jeroen Belleman wrote:

On 2017-03-23 20:49, Michael A. Terrell wrote:


I would rather have a 'redneck' on my side in a fight, than an
'ineffectual' intellectual.


A redneck can help you win a fight, but you need the intellectuals
to have a chance to win the war.

How many intellectuals put their lives on the line, to win that war?
They sit in offices and decide what are acceptable levels of casualties
among the actual fighters.


--
Never piss off an Engineer!

They don't get mad.

They don't get even.

They go for over unity! ;-)

 

[Michael A. Terrell]

tabbypurr@gmail.com wrote:

On Thursday, 23 March 2017 19:49:33 UTC, Michael Terrell wrote:
Kevin Aylward wrote:
"Cursitor Doom" wrote in message newsaruc8$b5u$4@dont-email.me...
On Mon, 20 Mar 2017 20:23:37 -0400, krw wrote:

It's obvious you're illiterate.

no point in reading further

I feel I should at this point apologise for the remarks made by my fellow
countryman, Kev. He and the poster "tabbypurr" are both singularly ill-
informed on this issue. Their ignorance is only matched by their
indefatigable ability to repeat the same dogma over and over and over
again. You will never win an argument against them; they simply won't
listen to reason. Do yourself a big favour and mark the thread "ignore"
in your newsreader. You'll save yourself from a huge amount of wasted
time.

I appreciate the support.

He's offering bs not support. In case there's any confusion I agree with kevin's conclusions.

In that case, you have my pity.


--
Never piss off an Engineer!

They don't get mad.

They don't get even.

They go for over unity! ;-)

 

[amdx]

On 3/23/2017 11:58 PM, amdx wrote:

On 3/23/2017 6:48 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, March 23, 2017 at 2:52:11 PM UTC-4, amdx wrote:
On 3/21/2017 9:28 AM, dagmargoodboat@yahoo.com wrote:
On Tuesday, March 21, 2017 at 8:27:51 AM UTC-4, amdx wrote:
On 3/21/2017 2:19 AM, dagmargoodboat@yahoo.com wrote:
On Monday, March 20, 2017 at 9:49:55 PM UTC-4,
dagmarg...@yahoo.com wrote:
On Monday, March 20, 2017 at 6:15:37 PM UTC-4, amdx wrote:

Can I tell this is working if my 1X gain increases?
The 17 to 1 divider of the input cap and the gate capacitance
and the 17
times gain of the amplifier equals 1X.

Say I get 80% T1 gate cancellation (by moving the 20Meg), now we
have
effectively 1pf.
1pf/0.3pf = 3.33 and the amp gain 17 / 3.33 = 5.1
So I would think my total circuit gain would increase to 5.1.
Or do I not get it?

You've got it perfectly. I don't expect a very large improvement
from
bootstrapping the 20M alone though--a resistor's capacitance is
pretty
low already, and two in series, even lower.

Your author's figures are inconsistent. He starts saying the input
capacitance is 1.4pF and the input coupling cap is 0.3pF, but
then he
says the 0.3pF and FET T1's capacitances form a 17:1 divider.
That can't
all be true--0.3pF should form a 5.7:1 divider with a 1.4pF
input, not
17:1.

When I guesstimate a 5x improvement, I'm banking on the 17:1
being true,
c.in(eff) being 5pF, and getting that down to 1pF, roughly, with the
circuit I sketched.

If you're already really at 1.4pF the improvement will only be
1.0pF/1.4pF,
and not 1.0pF/5pF.

As I said before, a better buffer could do better--you could
tweak the
bootstrap to perfect null--but then chances are you'd have an
oscillator.

What I posted seemed like a reasonable compromise for a first try.

I thought about this a bit and came up with an improved follower.

The main limitation of the previous circuit was the FET's poor
performance
as a voltage-follower. Unaided, the T1 has a gain of about 0.6.
That hits
our bootstrapping from all sides. First, c(gs) (the largest
capacitance)
is only bootstrapped by 60%, leaving 40% of the BC547C's ~5pF
c(gs). Next,
we use that voltage to drive our less-than-unity Q2, which drives
less-than-
unity Q1. This all adds up.

Changing T1's load to a current sink makes T1 into a much better
follower,
increasing voltage gain from 0.6 to about 0.95. The better
'follower'
action now bootstraps away nearly all of c(gs) (T1's largest
capacitance),
and gives us a better signal to drive the drain bootstrap as
well. Good,
good, and good. And not terribly much trouble to do, either.

Vdd Vdd
-+- -+-
| |
| [22k] R5
Q1 \| |
BC547B |---+-------.
.<| | |
| [47k] R6 |
(shield) T1 |--' | |
------ BF256C | === |
----------+----->|--. |
---+-- | | Vdd --- C2
| | | -+- ---100n
| | | | |
| R1 [10M] | |/ Q2 |
| | +---| BC547B |
| | | |>. |
| | R3 [470] | |
| | | | | C3
| | | | | 100n
| +----||---+-----+-------+-----||---> to ampl.
| | C1 | |
| R2 [10M] 100pF R4 [470] --- C4
| | | --- 100n
| === === |
| |
'------------------------------+
|
Cin ~200fF [2.2k] R7
|
===

Cheers,
James Arthur

Thanks for the time.
As it is now constructed the enclosure is the shield.
Is that good or bad? ie. Should the enclosure be isolated from the
shield?

The enclosure should be grounded! Let's not confuse that with
bootstrapping the input coax's shield (which you'll only do _if_
you use coax).

So yes, the enclosure should be isolated from the driven shield that is
shown in the schematic.

(My shield-driver is pretty wimpy, only suitable for a very short, low-
capacitance run. Might need beefing up.)

If you build it, it'll be fun to hear what output voltage you get from
this stage when you drive your 0.3pF input cap with, say, 50mV AC. If
you put 50mV into the 0.3pF and get 25mV out the back end, that means
our net input capacitance after bootstrapping is about the same as your
series 0.3pF.

Cheers,
James Arthur


OK, The circuit is built, I haven't tested it. I'm testing just the
circuit just the circuit posted.
I want to know how to drive the input.
Say I connect a 9 inch piece of RG58, that's 19pf, is that to much?
I want to drive it with a 50 ohm sig/gen.
Can I terminate the RG58 with 50 ohms or do I need to feed the RG58 with
a high impedance? Maybe a series 1Mohm.
I don't see how to separate the sig/gen cable from the input cable.
May I just need to connect it to the LC and see what I get.
Thank, Mikek


How about one step at a time? First, calibrate your input cap:

C1
.---. 0.3pF
| ~ |--------||----+----> A
'---' |
10V --- C2
--- 100pF
|
===

Measure V(A), calculate (don't forget to add your measuring instrument's
c.in to C2).


Easier said than done.
I have a pretty good capacitance tester. I made a .3pf cap :-/
and used an 82pf cap plus the probe, together they measured 106.7pf.
I applied 16Vpp and measured 0.06Vpp at A.
16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4
That makes my cap look like 0.4pf

I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I
make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in.
My cap is 1/8" diameter or 0.01227 sq in.
So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia.
So fringing and lead to lead capacitance, I'm in the ballpark, just not
sure what field.
If you have any suggestions, I'm willing.
Way past my bedtime, good night.
Mikek

PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in
number online.

I got out my better probe (Tek 6122 11pf) and made curly cues for the
probe tip.
Here's a picture of the tightened up circuit.
https://www.dropbox.com/s/sixe91dvxs40f1z/P1010193.JPG?dl=0


The new total capacitance, probe plus 82pf cap is 94pf. (measured)
16Vpp input, V(A) is 0.068Vpp. Then 16/0.068 = 235.3
235.3 / 94 = 2.5pf.
This is a tighter measurement and also agrees with my calculation of
0.253 that I calculated for the pcb capacitance per sq in.
Rather than fight with a new piece of pcb material just slightly over
1/8" in diameter.
I'm going to go with a new value input cap of 0.25pf.
If you see this as a bad idea, let me know and I'll fumble around
and make a larger cap. I used a 1/8' paper punch to make this cap,
I could use a 1/4" and grind it down, but it's a chore.


Now for the next measurement.
Is this with a T1 in the completed circuit?
Or, do I add the probe + 82pf back in to get a ratio?
Ya, I'm now confused.
I think we might want the voltage at the gate, but I
think that would be an impossible measurement. ie putting 11pf
probe across a 0.3pf cap ?
Thanks, Mikek

Then no coax:

T1 |--
.---. 0.3pF |
| ~ |--------||------>|--.
'---' | T1.s
1V
Put a known voltage into the 0.3pF, then measure the voltage at T1.s.

Kleijer says his gain at that node is 1/17th.

If things are good this far, add a short piece of coax to the input with
the shield grounded, and try. Then try with the shield driven. Then
Bob's
yer Grandma. Or something.

Cheers,
James Arthur



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[amdx]

On 3/24/2017 8:44 AM, amdx wrote:

On 3/23/2017 11:58 PM, amdx wrote:
On 3/23/2017 6:48 PM, dagmargoodboat@yahoo.com wrote:
On Thursday, March 23, 2017 at 2:52:11 PM UTC-4, amdx wrote:
On 3/21/2017 9:28 AM, dagmargoodboat@yahoo.com wrote:
On Tuesday, March 21, 2017 at 8:27:51 AM UTC-4, amdx wrote:
On 3/21/2017 2:19 AM, dagmargoodboat@yahoo.com wrote:
On Monday, March 20, 2017 at 9:49:55 PM UTC-4,
dagmarg...@yahoo.com wrote:
On Monday, March 20, 2017 at 6:15:37 PM UTC-4, amdx wrote:

Can I tell this is working if my 1X gain increases?
The 17 to 1 divider of the input cap and the gate capacitance
and the 17
times gain of the amplifier equals 1X.

Say I get 80% T1 gate cancellation (by moving the 20Meg), now we
have
effectively 1pf.
1pf/0.3pf = 3.33 and the amp gain 17 / 3.33 = 5.1
So I would think my total circuit gain would increase to 5.1.
Or do I not get it?

You've got it perfectly. I don't expect a very large improvement
from
bootstrapping the 20M alone though--a resistor's capacitance is
pretty
low already, and two in series, even lower.

Your author's figures are inconsistent. He starts saying the input
capacitance is 1.4pF and the input coupling cap is 0.3pF, but
then he
says the 0.3pF and FET T1's capacitances form a 17:1 divider.
That can't
all be true--0.3pF should form a 5.7:1 divider with a 1.4pF
input, not
17:1.

When I guesstimate a 5x improvement, I'm banking on the 17:1
being true,
c.in(eff) being 5pF, and getting that down to 1pF, roughly, with
the
circuit I sketched.

If you're already really at 1.4pF the improvement will only be
1.0pF/1.4pF,
and not 1.0pF/5pF.

As I said before, a better buffer could do better--you could
tweak the
bootstrap to perfect null--but then chances are you'd have an
oscillator.

What I posted seemed like a reasonable compromise for a first try.

I thought about this a bit and came up with an improved follower.

The main limitation of the previous circuit was the FET's poor
performance
as a voltage-follower. Unaided, the T1 has a gain of about 0.6.
That hits
our bootstrapping from all sides. First, c(gs) (the largest
capacitance)
is only bootstrapped by 60%, leaving 40% of the BC547C's ~5pF
c(gs). Next,
we use that voltage to drive our less-than-unity Q2, which drives
less-than-
unity Q1. This all adds up.

Changing T1's load to a current sink makes T1 into a much better
follower,
increasing voltage gain from 0.6 to about 0.95. The better
'follower'
action now bootstraps away nearly all of c(gs) (T1's largest
capacitance),
and gives us a better signal to drive the drain bootstrap as
well. Good,
good, and good. And not terribly much trouble to do, either.

Vdd Vdd
-+- -+-
| |
| [22k] R5
Q1 \| |
BC547B |---+-------.
.<| | |
| [47k] R6 |
(shield) T1 |--' | |
------ BF256C | === |
----------+----->|--. |
---+-- | | Vdd --- C2
| | | -+- ---100n
| | | | |
| R1 [10M] | |/ Q2 |
| | +---| BC547B |
| | | |>. |
| | R3 [470] | |
| | | | | C3
| | | | | 100n
| +----||---+-----+-------+-----||---> to ampl.
| | C1 | |
| R2 [10M] 100pF R4 [470] --- C4
| | | --- 100n
| === === |
| |
'------------------------------+
|
Cin ~200fF [2.2k] R7
|
===

Cheers,
James Arthur

Thanks for the time.
As it is now constructed the enclosure is the shield.
Is that good or bad? ie. Should the enclosure be isolated from the
shield?

The enclosure should be grounded! Let's not confuse that with
bootstrapping the input coax's shield (which you'll only do _if_
you use coax).

So yes, the enclosure should be isolated from the driven shield
that is
shown in the schematic.

(My shield-driver is pretty wimpy, only suitable for a very short,
low-
capacitance run. Might need beefing up.)

If you build it, it'll be fun to hear what output voltage you get from
this stage when you drive your 0.3pF input cap with, say, 50mV AC. If
you put 50mV into the 0.3pF and get 25mV out the back end, that means
our net input capacitance after bootstrapping is about the same as
your
series 0.3pF.

Cheers,
James Arthur


OK, The circuit is built, I haven't tested it. I'm testing just the
circuit just the circuit posted.
I want to know how to drive the input.
Say I connect a 9 inch piece of RG58, that's 19pf, is that to much?
I want to drive it with a 50 ohm sig/gen.
Can I terminate the RG58 with 50 ohms or do I need to feed the RG58
with
a high impedance? Maybe a series 1Mohm.
I don't see how to separate the sig/gen cable from the input cable.
May I just need to connect it to the LC and see what I get.
Thank, Mikek


How about one step at a time? First, calibrate your input cap:

C1
.---. 0.3pF
| ~ |--------||----+----> A
'---' |
10V --- C2
--- 100pF
|
===

Measure V(A), calculate (don't forget to add your measuring instrument's
c.in to C2).


Easier said than done.
I have a pretty good capacitance tester. I made a .3pf cap :-/
and used an 82pf cap plus the probe, together they measured 106.7pf.
I applied 16Vpp and measured 0.06Vpp at A.
16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4
That makes my cap look like 0.4pf

I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I
make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in.
My cap is 1/8" diameter or 0.01227 sq in.
So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia.
So fringing and lead to lead capacitance, I'm in the ballpark, just not
sure what field.
If you have any suggestions, I'm willing.
Way past my bedtime, good night.
Mikek

PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in
number online.


I got out my better probe (Tek 6122 11pf) and made curly cues for the
probe tip.
Here's a picture of the tightened up circuit.
https://www.dropbox.com/s/sixe91dvxs40f1z/P1010193.JPG?dl=0


The new total capacitance, probe plus 82pf cap is 94pf. (measured)
16Vpp input, V(A) is 0.068Vpp. Then 16/0.068 = 235.3
235.3 / 94 = 2.5pf.
This is a tighter measurement and also agrees with my calculation of
0.253 that I calculated for the pcb capacitance per sq in.
Rather than fight with a new piece of pcb material just slightly over
1/8" in diameter.
I'm going to go with a new value input cap of 0.25pf.
If you see this as a bad idea, let me know and I'll fumble around
and make a larger cap. I used a 1/8' paper punch to make this cap,
I could use a 1/4" and grind it down, but it's a chore.


Now for the next measurement.
Is this with a T1 in the completed circuit?
Or, do I add the probe + 82pf back in to get a ratio?
Ya, I'm now confused.
I think we might want the voltage at the gate, but I
think that would be an impossible measurement. ie putting 11pf
probe across a 0.3pf cap ?
Thanks, Mikek

Ok, I tried this, out of circuit, just the FET.

T1 |--
.---. 0.3pF |
| ~ |--------||------>|--.
'---' | T1.s = 0.06Vpp
16Vpp |
|---probe tip
82pf –--
--- 12pf
|---probe ground
|
---
///

So, 16Vpp / 0.6Vpp = 266.6
266.6 / 94 = 2.84pf
2.84pf - 0.3pf = 2.54pf for the Cgs.
I think that's to low, I thought it was 5pf,
but I'm looking for your thoughts.

Thanks Mikek

Then no coax:

T1 |--
.---. 0.3pF |
| ~ |--------||------>|--.
'---' | T1.s
1V
Put a known voltage into the 0.3pF, then measure the voltage at T1.s.

Kleijer says his gain at that node is 1/17th.

If things are good this far, add a short piece of coax to the input with
the shield grounded, and try. Then try with the shield driven. Then
Bob's
yer Grandma. Or something.

Cheers,
James Arthur



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[John Larkin]

On Fri, 24 Mar 2017 11:02:32 +0100, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 2017-03-23 20:49, Michael A. Terrell wrote:


I would rather have a 'redneck' on my side in a fight, than an
'ineffectual' intellectual.


A redneck can help you win a fight, but you need the intellectuals
to have a chance to win the war.

Jeroen Belleman

Or to even start the war.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Kevin Aylward]

wrote in message news:mnq8dcpnbekopn07j0cu3crq12hq0905l1@4ax.com...

On Thu, 23 Mar 2017 14:58:23 -0400, "Michael A. Terrell"
<mike.terrell@earthlink.net> wrote:

krw@notreal.com wrote:
On Sun, 19 Mar 2017 14:19:57 -0000 (UTC), Cursitor Doom
curd@notformail.com> wrote:

On Sat, 18 Mar 2017 20:03:50 -0400, krw wrote:

That's impossible, which is the whole "reasonable" thing.

Nothing whatsoever impossible about it!

Not at all. There is always doubt. It may be an unreasonable doubt
but there is _always_ doubt (what if the Earth was really flat?).
Hence, "beyond reasonable doubt".


What do you think of this sorry piece of work?

http://www.wftv.com/news/local/ayala-to-explain-why-she-wont-seek-death-penalty-against-murder-suspect-markeith-loyd/503151996

She should *immediately* be removed from office for violating her oath
of office to follow the constitution and laws of the state of Florida.
That decision isn't hers to make.

Ho hummm..

Like, what specific law says that anybody has to demand the death of someone
else? Dah....

All I see is a the usual baying pack of wolves displaying the usual stunning
display of hypocrisy, totally oblivious to the notion that they want to do
to the accused, what the accused has, allegedly done. If it were so wrong,
then, it can't be right to do it again.

Its outrageous that Gov. Rick Scott expressed outrage, that he may not get
the chance to do what Markeith Loyd is alleged to have done, i.e. kill
someone.

More so when:

"The mother of homicide victim Sade Dixon spoke out Friday in support of
State Attorney Aramis Ayala's decision to not seek the death penalty for her
daughter's accused killer or anyone else."

http://www.clickorlando.com/news/aclu-we-stand-with-state-attorney-ayalas-death-penalty-decision

Surely, it would be more ethical to respect the wishes of the victim's
mother here, instead of respecting election votes.

Of course, assuming the allegations are true, then the crimes are
horrendous, and would certainly warrant life in prison, with no possibility
of parole, however, the idea that members of the state that desire a more
cold bloodied, vastly more premeditated murder is anyway more ethical, is
extremely dubious. Noting that a fleeing felon, in fear of his own life, is
understandably, going to act on his millions of years of evolutionary
programming of protecting himself at all costs.

....and don't even attempt to confuse "understanding" with "condoning".

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html