Dividing a 32768 Hz crystal frequency...

[whit3rd]

On Monday, June 26, 2023 at 2:49:25 PM UTC-7, Clive Arthur wrote:

On 26/06/2023 15:20, John Woodgate wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge. I could use a 4017 and half a a 4013 (sorry about these ancient devices, but they are still good for some things), but I would have to add something to make the crystal oscillate unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I can\'t see how to make it divide by 20. I know there is a technique that combines some of the output signals via an EXOR to achieve divisors that are not powers of 2, but I can\'t find information on which signals to combine.
I\'d just use a PIC or similar running a simple loop toggling an output
pin. The eight pin parts (always?) have Xtal oscillators. Some have
Numerically Controlled Oscillators which might be handy instead of the
simple loop.

eg PIC16(L)F18313/18323

As others have said, watch crystals are good at watch temperatures, not
so good otherwise, so a better spec higher frequency may be the way to
go. Or if you want even more betterer, a GPSDO will give a stable 10MHz
if the antenna can see satellites.

There\'s off-the-shelf non-watch-crystal items like this
<https://abracon.com/Oscillators/ASSVP.pdf>
that can be programmed for any frequency in their range (10 to 160 MHz)
available for about $5 each, programmed to spec, at Digikey.

To do their trickery on-chip, lower frequencies will still take an external
divider... and the CD4017 tricks work best with 10 x 2^N division, just pick N.

 

[Phil Allison]

whit3rd wrote:
------------------------
JW wtote:

I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.


....... Phil

 

[Ricky]

On Thursday, June 29, 2023 at 2:06:54 AM UTC-4, Phil Allison wrote:

whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.


** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.


...... Phil

Which means nothing, because 100 ppm is the spec limit, not indicative of what any particular crystal will do. If you understood tolerances, you would know that to achieve an acceptable failure rate, the actual parts would typically be in a ~10 ppm band.

If you have a process for making 4 ppm crystals reliably at a price point for watches, you need to patent that.

I remember in the early days of digital watches, I had one with a trimmer capacitor. I would adjust it to be \"spot on\" and then it would drift. While there is a spec for initial tolerance, there is also a spec for age drift, which people pay attention to much less. There\'s also a spec for temperature drift, which is much less important for personal time keeping, as most people don\'t keep their clocks in the refrigerator.

I also had a watch with a built in thermometer, which was pretty cool. It could correct for body heat, or you could turn that off and use it as a dive watch. That was very nice, and I\'ve never found another inexpensive watch with that feature.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

 

[Jan Panteltje]

On a sunny day (Wed, 28 Jun 2023 23:41:57 -0700 (PDT)) it happened Ricky
<gnuarm.deletethisbit@gmail.com> wrote in
<0c6f4e12-aa68-4d09-9e6c-a19ef3dbc49dn@googlegroups.com>:

On Thursday, June 29, 2023 at 2:06:54 AM UTC-4, Phil Allison wrote:
whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable f=
requency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100=
ppm frequency variance
is close enough for a wall clock.


** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.


...... Phil

Which means nothing, because 100 ppm is the spec limit, not indicative of w=
hat any particular crystal will do. If you understood tolerances, you woul=
d know that to achieve an acceptable failure rate, the actual parts would t=
ypically be in a ~10 ppm band.

If you have a process for making 4 ppm crystals reliably at a price point f=
or watches, you need to patent that.

I remember in the early days of digital watches, I had one with a trimmer c=
apacitor. I would adjust it to be \"spot on\" and then it would drift. Whil=
e there is a spec for initial tolerance, there is also a spec for age drift=
, which people pay attention to much less. There\'s also a spec for tempera=
ture drift, which is much less important for personal time keeping, as most=
people don\'t keep their clocks in the refrigerator.

I also had a watch with a built in thermometer, which was pretty cool. It =
could correct for body heat, or you could turn that off and use it as a div=
e watch. That was very nice, and I\'ve never found another inexpensive watc=
h with that feature.

I have a Casio Waveceptor radio watch
https://www.casio.com/nl/watches/casio/product.WV-200R-1A/
Also takes care of winter summer time,
allows reception of time reference stations for many countries, here uses DCF77 time reference
https://en.m.wikipedia.org/wiki/DCF77
Usually accurate to within a second, nice if you are at sea and use a sextant for example
Bought it in 2014, still going strong, longest lasting watch I ever had.
And you do not get robbed for it as when wearing a golden whatever.

Flying cup and saucer referral code - http://127.0.0.1

> +-+ Tesla referral code - https://ts.la.la/richard911

 

[Ricky]

On Thursday, June 29, 2023 at 3:20:13 AM UTC-4, Jan Panteltje wrote:

On a sunny day (Wed, 28 Jun 2023 23:41:57 -0700 (PDT)) it happened Ricky
gnuarm.del...@gmail.com> wrote in
0c6f4e12-aa68-4d09...@googlegroups.com>:
On Thursday, June 29, 2023 at 2:06:54 AM UTC-4, Phil Allison wrote:
whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable f> >requency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100> >ppm frequency variance
is close enough for a wall clock.


** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.


...... Phil

Which means nothing, because 100 ppm is the spec limit, not indicative of w=
hat any particular crystal will do. If you understood tolerances, you woul=
d know that to achieve an acceptable failure rate, the actual parts would t> >ypically be in a ~10 ppm band.

If you have a process for making 4 ppm crystals reliably at a price point f> >or watches, you need to patent that.

I remember in the early days of digital watches, I had one with a trimmer c=
apacitor. I would adjust it to be \"spot on\" and then it would drift. Whil=
e there is a spec for initial tolerance, there is also a spec for age drift=
, which people pay attention to much less. There\'s also a spec for tempera=
ture drift, which is much less important for personal time keeping, as most> > people don\'t keep their clocks in the refrigerator.

I also had a watch with a built in thermometer, which was pretty cool. It =
could correct for body heat, or you could turn that off and use it as a div=
e watch. That was very nice, and I\'ve never found another inexpensive watc=
h with that feature.

I have a Casio Waveceptor radio watch
https://www.casio.com/nl/watches/casio/product.WV-200R-1A/
Also takes care of winter summer time,
allows reception of time reference stations for many countries, here uses DCF77 time reference
https://en.m.wikipedia.org/wiki/DCF77
Usually accurate to within a second, nice if you are at sea and use a sextant for example
Bought it in 2014, still going strong, longest lasting watch I ever had.
And you do not get robbed for it as when wearing a golden whatever.

Flying cup and saucer referral code - http://127.0.0.1

+-+ Tesla referral code - https://ts.la.la/richard911

I think you get stranger with every post.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

 

[Martin Brown]

On 29/06/2023 07:06, Phil Allison wrote:

whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

Watch crystals are cut on a quadratic drift rate curve centred at around
25C so they are normally very good stability at household temperatures.

https://www.researchgate.net/figure/Crystal-frequency-drift-with-temperature_fig5_340110168

The worst case error is typically about 50ppm and one sided for the
range 0 to 50C (if the crystal is correctly loaded and driven).

Most homes maintain a steady ambient temperature.

They age a bit and drift long term if you care about that and will
perform less well and deteriorate faster if over driven (as many are).

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

Curiously some older quite high end (amateur) kit has been made with
incorrectly loaded RTC crystals like the Meade LX200 computerised
telescope that keeps keep terrible time ~5 minutes a month drift.

Changing a couple of capacitors and one resistor would have fixed it!
They \"cured\" it by bringing out a model with GPS to (re)set the time!

--
Martin Brown

 

[Jasen Betts]

On 2023-06-28, John Larkin <jlarkin@highlandSNIPMEtechnology.com> wrote:

On Wed, 28 Jun 2023 00:55:11 -0700 (PDT), whit3rd <whit3rd@gmail.com
wrote:

On Tuesday, June 27, 2023 at 11:28:46?PM UTC-7, John Larkin wrote:
On Wed, 28 Jun 2023 14:35:42 +1000, Sylvia Else <syl...@email.invalid
wrote:

Many years ago, I ANDed a bunch of outputs from counter stages, and fed
the result into the reset, to achieve division by some arbitrary
integer. I was electronically naive [*] at the time, and what I did may
have relied on the propagation delays to work properly. The application
would not have been sensitive to the occasional glitch.

Or perhaps I was lucky enough to have bought a counter with a
synchronous reset. Either way, it worked.

Sylvia

[*] OK, OK, you got me; even more electronically naive than now.
Actually, I think that it always works, sync or async.

Not necessarily: async reset can be fooled by the transient between-states
values of a slow slewing or ripple-delayed clocked event. Using the gate
output AT the main clock time should take you from N to zero, as long
as gate and slew delays aren\'t bigger than a clock period.

In the ripple counter case, I recall that the terminal count
transition is the first possible output of the AND gate, so it\'s safe
to drive an async clear. If you decode state N, it divides by N.

sure, so long as the clear is asserted for long enough to reset all the
flip-flops in the ripple counter. in a CD4060 the flip-flops are
faster than the minimum reset pulse width. so you possibly need to add
some delay after the and gate to be certain that it will reset to zero.

the reset will also mess with the crystal oscillator

--
Jasen.
🇺🇦 Слава Україні

 

[Phil Allison]

Martin Brown wrote:
---------------------------------

Watch crystals are cut on a quadratic drift rate curve centred at around
25C so they are normally very good stability at household temperatures.

https://www.researchgate.net/figure/Crystal-frequency-drift-with-temperature_fig5_340110168


Most homes maintain a steady ambient temperature.

** Yep - the most common frequency drift is the temp rising above room ambient inside the equipment where the crystal lives.
Obviously one should avoid siting the crystal next to a heat source but if possible (and needed) install a tiny DC fan that cools the crystal with outside air. Did this with my bench 1GHz frequency counter eliminating the previous warm up drift.

FYI the counter is used to check VHF and UHF radio mic equipment. With a short antenna plugged into the BNC input, enough signal is picked up to work the internal pre-scalar at close range to a transmitter.

...... Phil

 

[Sylvia Else]

On 29-June-23 1:59 am, Anthony William Sloman wrote:

On Thursday, June 29, 2023 at 12:30:05 AM UTC+10, John Larkin wrote:
On Wed, 28 Jun 2023 00:55:11 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Tuesday, June 27, 2023 at 11:28:46?PM UTC-7, John Larkin wrote:
On Wed, 28 Jun 2023 14:35:42 +1000, Sylvia Else <syl...@email.invalid
wrote:

Many years ago, I ANDed a bunch of outputs from counter stages, and fed
the result into the reset, to achieve division by some arbitrary
integer. I was electronically naive [*] at the time, and what I did may
have relied on the propagation delays to work properly. The application
would not have been sensitive to the occasional glitch.

Or perhaps I was lucky enough to have bought a counter with a
synchronous reset. Either way, it worked.

Sylvia

[*] OK, OK, you got me; even more electronically naive than now.
Actually, I think that it always works, sync or async.

Not necessarily: async reset can be fooled by the transient between-states
values of a slow slewing or ripple-delayed clocked event. Using the gate
output AT the main clock time should take you from N to zero, as long
as gate and slew delays aren\'t bigger than a clock period.

In the ripple counter case, I recall that the terminal count
transition is the first possible output of the AND gate, so it\'s safe
to drive an async clear. If you decode state N, it divides by N.

It the counter is long enough and slow enough you may never get something that looks like \"state N\" on the outputs of a ripple counter - the low order bits have got past \"state N\" before the high order bits have got to it.

I think a starting point for this is that the clock period is much
longer than the time required for the counter to settle into a
particular state.

However, given that the reset signal is generated when state N exists,
and the reset will cause state N to cease to exist, the reset pulse is
going to be quite short. If one were trying it with something like this:

https://www.onsemi.com/pdf/datasheet/mc14040b-d.pdf

it might well work, but there\'s no way one would be complying with the
worst case reset pulse width requirement (page 4).

Sylvia.

 

[Jan Panteltje]

On a sunny day (Thu, 29 Jun 2023 03:11:30 -0700 (PDT)) it happened Phil
Allison <pallison49@gmail.com> wrote in
<3b2fb805-4986-4aa6-9dd1-25f61a14f2den@googlegroups.com>:

Martin Brown wrote:
---------------------------------

Watch crystals are cut on a quadratic drift rate curve centred at around
25C so they are normally very good stability at household temperatures.

https://www.researchgate.net/figure/Crystal-frequency-drift-with-temperature_fig5_340110168


Most homes maintain a steady ambient temperature.

** Yep - the most common frequency drift is the temp rising above room ambient inside the equipment where the crystal lives.
Obviously one should avoid siting the crystal next to a heat source but if possible (and needed) install a tiny DC fan that
cools the crystal with outside air. Did this with my bench 1GHz frequency counter eliminating the previous warm up drift.

FYI the counter is used to check VHF and UHF radio mic equipment. With a short antenna plugged into the BNC input, enough
signal is picked up to work the internal pre-scalar at close range to a transmitter.

..... Phil

The USB RTL-SDR sticks are 1 ppm accuracy temperature stabilized and I use those among other things for checking radio sigals and frequencies
and my software can ever record those, latest with FM stereo reception:
https://panteltje.nl/pub/xpsa-0.7.gif
There is a lot of open source software for it, works perfectly on a raspberry Pi too, even very old models.

Old version without FM stereo:
https://panteltje.nl/panteltje/xpsa/index.html

On ebay:
https://www.ebay.com/itm/272411458376
12,496 sold so far...
good seller, have 2 from this one.
Everybody is moving to these sticks, lots of open source software.

 

[John Larkin]

On Wed, 28 Jun 2023 23:06:49 -0700 (PDT), Phil Allison
<pallison49@gmail.com> wrote:

whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.


** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.


...... Phil

Cheap XOs are often specified around 100 PPM but usually arrive within
a PPM or two. An oscillator made from parts is unlikely to be that
good, if it oscillates reliably.

 

[John Larkin]

On Thu, 29 Jun 2023 22:04:01 +1000, Sylvia Else <sylvia@email.invalid>
wrote:

On 29-June-23 1:59 am, Anthony William Sloman wrote:
On Thursday, June 29, 2023 at 12:30:05?AM UTC+10, John Larkin wrote:
On Wed, 28 Jun 2023 00:55:11 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Tuesday, June 27, 2023 at 11:28:46?PM UTC-7, John Larkin wrote:
On Wed, 28 Jun 2023 14:35:42 +1000, Sylvia Else <syl...@email.invalid
wrote:

Many years ago, I ANDed a bunch of outputs from counter stages, and fed
the result into the reset, to achieve division by some arbitrary
integer. I was electronically naive [*] at the time, and what I did may
have relied on the propagation delays to work properly. The application
would not have been sensitive to the occasional glitch.

Or perhaps I was lucky enough to have bought a counter with a
synchronous reset. Either way, it worked.

Sylvia

[*] OK, OK, you got me; even more electronically naive than now.
Actually, I think that it always works, sync or async.

Not necessarily: async reset can be fooled by the transient between-states
values of a slow slewing or ripple-delayed clocked event. Using the gate
output AT the main clock time should take you from N to zero, as long
as gate and slew delays aren\'t bigger than a clock period.

In the ripple counter case, I recall that the terminal count
transition is the first possible output of the AND gate, so it\'s safe
to drive an async clear. If you decode state N, it divides by N.

It the counter is long enough and slow enough you may never get something that looks like \"state N\" on the outputs of a ripple counter - the low order bits have got past \"state N\" before the high order bits have got to it.


I think a starting point for this is that the clock period is much
longer than the time required for the counter to settle into a
particular state.

However, given that the reset signal is generated when state N exists,
and the reset will cause state N to cease to exist, the reset pulse is
going to be quite short. If one were trying it with something like this:

https://www.onsemi.com/pdf/datasheet/mc14040b-d.pdf

it might well work, but there\'s no way one would be complying with the
worst case reset pulse width requirement (page 4).

Sylvia.

The prop delay of the AND gate, and the clear delay of the counter,
will generally make a reliable reset pulse. It pretty much has to
work.

The reset pulse lasts until at least one of the flops clears. And
more.

 

[John Larkin]

On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jlarkin@highlandSNIPMEtechnology.com> wrote in
moap9i94f8h96d3diev581lm8oi2q49f82@4ax.com>:

On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:

On 26-06-2023 16:20, John Woodgate wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge. I could use a 4017
and half a a 4013 (sorry about these ancient devices, but they are still good for some things), but I would have to add something
to make the crystal oscillate unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I can\'t see how to make it divide by 20. I know
there is a technique that combines some of the output signals via an EXOR to achieve divisors that are not powers of 2, but I can\'t
find information on which signals to combine.

A STM32 micro, so you can program whatever frequency you want to pass on.
Software DDS is fun too. Lots of micros have a 10 or 12-bit DAC which
can be lowpass filtered into a nearly perfect sine. Interrupting at a
few hundred KHz is easy nowadays.

A Pi Pico would make a cool general-purpose signal generator. There
are a zillion possibilities for a product there, and would just need a
bit of code.

I\'m guessing that a 1 MHz interrupt rate could be supported on the DDS
core. Covering the audio range would be easy.

I\'ll architect it if someone will code it.

this does 400Hz sin/cos DDS on the two DACs on a 168MHz STM32F407
https://github.com/langwadt/singen

at 500ksps it spends about 50% cpu time in the interrupt calculating each sin/cos using ARMs fixed point lib
using a simple table lookup is uses ~25%

Table lookup is great for DDS, where not many MSBs of the phase
accumulator are used. I\'ve brute-forced a 16 bit sine function the
dumbest possible way, a lookup table with 65536 entries.

On a Pico, one would copy the sine table into RAM, maybe unfold it
from flash at powerup.

I wonder if a Pi Pico can run code, the DDS ISR, out of ram. That
would avoid cache misses.

I once build an audio sine generator with a 4040 counter driving an EPROM with sine table into an R2R DAC
The oscillator was a 4046, wide frequency range,

Everybody here has done that!

>Who needs processors....

Well, they do all sorts of stuff and are crazy cheap. The RP2040 chip
is $1 and has two ARM cores. One core can run code out of RAM at 133
MHz, so could replace an FPGA in a lot of situations.

Software DDS in a cheap uP is cool. Only ADI still makes DDS chips and
they are expensive and a nuisance to interface. May as well use a uP
or a cheap FPGA and do a lot of other stuff.

At audio frequencies, software could DDS and then push a sine out of a
single pin, PWM or delta-sigma. No DAC needed.

 

[John Larkin]

On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable
frequency for a component bridge. I could use a 4017 and half a a 4013
(sorry about these ancient devices, but they are still good for some
things), but I would have to add something to make the crystal oscillate
unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I
can\'t see how to make it divide by 20. I know there is a technique that
combines some of the output signals via an EXOR to achieve divisors that
are not powers of 2, but I can\'t find information on which signals to combine.


Hey, John,

Nice to see you back on SED, man!
An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?

If you ac-couple into a cmos gate and add a high-value feedback
resistor, it sort of self-servoes its bias. And gets weird if there\'s
no signal.

 

[Anthony William Sloman]

On Friday, June 30, 2023 at 12:14:25 AM UTC+10, John Larkin wrote:

On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <al...@comet.invalid> wrote:
On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jla...@highlandSNIPMEtechnology.com> wrote in <moap9i94f8h96d3di...@4ax..com>:
On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:
On 26-06-2023 16:20, John Woodgate wrote:

At audio frequencies, software could DDS and then push a sine out of a single pin, PWM or delta-sigma. No DAC needed.

Pulse width modulation is Don Lancaster\'s magic sine waves which aren\'t all that magic. So is sigma-delta.

A proper DAC covers a lot more ground and doesn\'t need as much filtering.

--
Bill Sloman, Sydney

 

[Jan Panteltje]

On a sunny day (Thu, 29 Jun 2023 07:14:08 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<nt3r9il3mcq4bi9hov0hfdh5ot8qv6stt8@4ax.com>:

On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <alien@comet.invalid
wrote:

On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jlarkin@highlandSNIPMEtechnology.com> wrote in
moap9i94f8h96d3diev581lm8oi2q49f82@4ax.com>:

On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:

On 26-06-2023 16:20, John Woodgate wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge. I could use a
4017
and half a a 4013 (sorry about these ancient devices, but they are still good for some things), but I would have to add
something
to make the crystal oscillate unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I can\'t see how to make it divide by 20. I know
there is a technique that combines some of the output signals via an EXOR to achieve divisors that are not powers of 2,
but I can\'t
find information on which signals to combine.

A STM32 micro, so you can program whatever frequency you want to pass on.
Software DDS is fun too. Lots of micros have a 10 or 12-bit DAC which
can be lowpass filtered into a nearly perfect sine. Interrupting at a
few hundred KHz is easy nowadays.

A Pi Pico would make a cool general-purpose signal generator. There
are a zillion possibilities for a product there, and would just need a
bit of code.

I\'m guessing that a 1 MHz interrupt rate could be supported on the DDS
core. Covering the audio range would be easy.

I\'ll architect it if someone will code it.

this does 400Hz sin/cos DDS on the two DACs on a 168MHz STM32F407
https://github.com/langwadt/singen

at 500ksps it spends about 50% cpu time in the interrupt calculating each sin/cos using ARMs fixed point lib
using a simple table lookup is uses ~25%

Table lookup is great for DDS, where not many MSBs of the phase
accumulator are used. I\'ve brute-forced a 16 bit sine function the
dumbest possible way, a lookup table with 65536 entries.

On a Pico, one would copy the sine table into RAM, maybe unfold it
from flash at powerup.

I wonder if a Pi Pico can run code, the DDS ISR, out of ram. That
would avoid cache misses.

I once build an audio sine generator with a 4040 counter driving an EPROM with sine table into an R2R DAC
The oscillator was a 4046, wide frequency range,

Everybody here has done that!

Who needs processors....

I was joking I hope you noticed...

Well, they do all sorts of stuff and are crazy cheap. The RP2040 chip
is $1 and has two ARM cores. One core can run code out of RAM at 133
MHz, so could replace an FPGA in a lot of situations.

Yes, maybe one day I should try a Pico
But a real Raspberry Pi 4 is so much easier to interface, posting from one now
You have one,
Huawei 4G USB modem stick for net connection.
It sort of replaces the laptop now, does Usenet, music player, using a bigger monitor than the laptop has...
Has a 3.8 TB Toshiba harddisk with an USB hub hanging from it:
/dev/sda2 3844510712 2404050964 1245099084 66% /mnt/sda2
Backups, compile stuff,


try \'sox\' to make audio tones, use an USB audio adaptor
generate wavefiles with tones:
From:
https://www.audiosciencereview.com/forum/index.php?threads/howto-sox-audio-tool-as-a-signal-generator.4242/
sox -n -r 48000 -c 2 -b 16 1000.wav synth 300 sine 1000
sox -n -r 48000 -c 2 -b 16 18000.wav synth 300 sine 18000
sox -n -r 48000 -c 2 -b 16 19000.wav synth 300 sine 19000
sox -n -r 48000 -c 2 -b 16 38000.wav synth 300 sine 38000

Audio is fun, I added voice output to my laptop battery monitor,
you can use google translate to make an mp3 file from text like this:

My script gst7:
#!/bin/bash
# Usage:
# To speak a line of text: echo \"any text\" | ./gst7
# To record a line of text as mp3: echo \"any text\" | ./gst7 filename.mp3
read user_reply
if [ \"$1\" == \"\" ]
then
# mplayer -dumpaudio -dumpfile /dev/stdout -really-quiet -noconsolecontrols \"http://translate.google.com/translate_tts?ie=UTF-8&client=tw-ob&q=$user_reply&tl=en\" | mpg123 -
wget --user-agent seamonkey --no-check-certificate -O /dev/stdout \"http://translate.google.com/translate_tts?ie=UTF-8&client=tw-ob&q=$user_reply&tl=en\" | mpg123 -
else
# mplayer -dumpaudio -dumpfile /dev/stdout -really-quiet -noconsolecontrols \"http://translate.google.com/translate_tts?ie=UTF-8&client=tw-ob&q=$user_reply&tl=en\" > $1
wget --user-agent seamonkey --no-check-certificate -O $1 \"http://translate.google.com/translate_tts?ie=UTF-8&client=tw-ob&q=$user_reply&tl=en\"
fi

So for example
gst7 laptop_battery_low.mp3
makes a nice mp3 file with a female voice with that text


play the mp3 with mpg123 or whatever else, ffplay, mplayer.

There is also \'festival\' for text to speech for the raspberry, plus some others

Wonder if any of that runs on that Pico
Does Pico have a C compiler gcc that runs?

Software DDS in a cheap uP is cool. Only ADI still makes DDS chips and
they are expensive and a nuisance to interface. May as well use a uP
or a cheap FPGA and do a lot of other stuff.

At audio frequencies, software could DDS and then push a sine out of a
single pin, PWM or delta-sigma. No DAC needed.

Yes, done that, PWM, Microchip PIC here as amplifier:
https://panteltje.nl/panteltje/pic/audio_pic/


Most simple things can be done with a PIC micro IF you can code in asm..
https://panteltje.nl/panteltje/pic/index.html

scope_pic has a sine table for Fourier transform.
All asm


There is so much more....

 

[Anthony William Sloman]

On Friday, June 30, 2023 at 1:26:05 AM UTC+10, John Larkin wrote:

On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:

<snip>

An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?

If you ac-couple into a cmos gate and add a high-value feedback resistor, it sort of self-servoes its bias. And gets weird if there\'s no signal.

That\'s not quite what TI says.

https://www.ti.com/lit/an/szza043/szza043.pdf?ts=1688053798084&ref_url=https%253A%252F%252Fwww.google.com%252F

There are other opinions

https://www.iqdfrequencyproducts.com/media/pg/1861/1452506068/ic-crystal-oscillator-circuits-rakon-application-note.pdf

https://www.osti.gov/servlets/purl/1639828

--
Bill Sloman, Sydney

 

[Lasse Langwadt Christensen]

torsdag den 29. juni 2023 kl. 17.42.57 UTC+2 skrev Anthony William Sloman:

On Friday, June 30, 2023 at 12:14:25 AM UTC+10, John Larkin wrote:
On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <al...@comet.invalid> wrote:
On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jla...@highlandSNIPMEtechnology.com> wrote in <moap9i94f8h96d3di...@4ax.com>:
On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:
On 26-06-2023 16:20, John Woodgate wrote:

At audio frequencies, software could DDS and then push a sine out of a single pin, PWM or delta-sigma. No DAC needed.
Pulse width modulation is Don Lancaster\'s magic sine waves which aren\'t all that magic. So is sigma-delta.

Magic sine waves are more like precalculated and optimized delta-sigma that PWM

 

[Lasse Langwadt Christensen]

torsdag den 29. juni 2023 kl. 16.14.25 UTC+2 skrev John Larkin:

On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <al...@comet.invalid
wrote:
On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jla...@highlandSNIPMEtechnology.com> wrote in
moap9i94f8h96d3di...@4ax.com>:

On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:

On 26-06-2023 16:20, John Woodgate wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge. I could use a 4017
and half a a 4013 (sorry about these ancient devices, but they are still good for some things), but I would have to add something
to make the crystal oscillate unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I can\'t see how to make it divide by 20. I know
there is a technique that combines some of the output signals via an EXOR to achieve divisors that are not powers of 2, but I can\'t
find information on which signals to combine.

A STM32 micro, so you can program whatever frequency you want to pass on.
Software DDS is fun too. Lots of micros have a 10 or 12-bit DAC which
can be lowpass filtered into a nearly perfect sine. Interrupting at a
few hundred KHz is easy nowadays.

A Pi Pico would make a cool general-purpose signal generator. There
are a zillion possibilities for a product there, and would just need a
bit of code.

I\'m guessing that a 1 MHz interrupt rate could be supported on the DDS
core. Covering the audio range would be easy.

I\'ll architect it if someone will code it.

this does 400Hz sin/cos DDS on the two DACs on a 168MHz STM32F407
https://github.com/langwadt/singen

at 500ksps it spends about 50% cpu time in the interrupt calculating each sin/cos using ARMs fixed point lib
using a simple table lookup is uses ~25%

Table lookup is great for DDS, where not many MSBs of the phase
accumulator are used. I\'ve brute-forced a 16 bit sine function the
dumbest possible way, a lookup table with 65536 entries.

On a Pico, one would copy the sine table into RAM, maybe unfold it
from flash at powerup.

I wonder if a Pi Pico can run code, the DDS ISR, out of ram. That
would avoid cache misses.

I once build an audio sine generator with a 4040 counter driving an EPROM with sine table into an R2R DAC
The oscillator was a 4046, wide frequency range,
Everybody here has done that!

Who needs processors....

Well, they do all sorts of stuff and are crazy cheap. The RP2040 chip
is $1 and has two ARM cores. One core can run code out of RAM at 133
MHz, so could replace an FPGA in a lot of situations.

Software DDS in a cheap uP is cool. Only ADI still makes DDS chips and
they are expensive and a nuisance to interface. May as well use a uP
or a cheap FPGA and do a lot of other stuff.

sure, at low frequencies

 

[Ricky]

On Thursday, June 29, 2023 at 8:04:12 AM UTC-4, Sylvia Else wrote:

On 29-June-23 1:59 am, Anthony William Sloman wrote:
On Thursday, June 29, 2023 at 12:30:05 AM UTC+10, John Larkin wrote:
On Wed, 28 Jun 2023 00:55:11 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Tuesday, June 27, 2023 at 11:28:46?PM UTC-7, John Larkin wrote:
On Wed, 28 Jun 2023 14:35:42 +1000, Sylvia Else <syl...@email.invalid
wrote:

Many years ago, I ANDed a bunch of outputs from counter stages, and fed
the result into the reset, to achieve division by some arbitrary
integer. I was electronically naive [*] at the time, and what I did may
have relied on the propagation delays to work properly. The application
would not have been sensitive to the occasional glitch.

Or perhaps I was lucky enough to have bought a counter with a
synchronous reset. Either way, it worked.

Sylvia

[*] OK, OK, you got me; even more electronically naive than now.
Actually, I think that it always works, sync or async.

Not necessarily: async reset can be fooled by the transient between-states
values of a slow slewing or ripple-delayed clocked event. Using the gate
output AT the main clock time should take you from N to zero, as long
as gate and slew delays aren\'t bigger than a clock period.

In the ripple counter case, I recall that the terminal count
transition is the first possible output of the AND gate, so it\'s safe
to drive an async clear. If you decode state N, it divides by N.

It the counter is long enough and slow enough you may never get something that looks like \"state N\" on the outputs of a ripple counter - the low order bits have got past \"state N\" before the high order bits have got to it..

I think a starting point for this is that the clock period is much
longer than the time required for the counter to settle into a
particular state.

However, given that the reset signal is generated when state N exists,
and the reset will cause state N to cease to exist, the reset pulse is
going to be quite short.

Why would you not register the reset pulse? Then it lasts a full clock cycle.

If one were trying it with something like this:

https://www.onsemi.com/pdf/datasheet/mc14040b-d.pdf

it might well work, but there\'s no way one would be complying with the
worst case reset pulse width requirement (page 4).

You would if you designed the circuit properly. Clock the reset FF from the rising edge of the clock, and the final state will appear for half a clock, and the counter will be in the zero state for a clock and a half.

--

Rick C.

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