Dividing a 32768 Hz crystal frequency...

[Ricky]

On Thursday, June 29, 2023 at 12:17:14 PM UTC-4, Lasse Langwadt Christensen wrote:

torsdag den 29. juni 2023 kl. 16.14.25 UTC+2 skrev John Larkin:
On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <al...@comet.invalid
wrote:
On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jla...@highlandSNIPMEtechnology.com> wrote in
moap9i94f8h96d3di...@4ax.com>:

On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:

On 26-06-2023 16:20, John Woodgate wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge. I could use a 4017
and half a a 4013 (sorry about these ancient devices, but they are still good for some things), but I would have to add something
to make the crystal oscillate unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I can\'t see how to make it divide by 20. I know
there is a technique that combines some of the output signals via an EXOR to achieve divisors that are not powers of 2, but I can\'t
find information on which signals to combine.

A STM32 micro, so you can program whatever frequency you want to pass on.
Software DDS is fun too. Lots of micros have a 10 or 12-bit DAC which
can be lowpass filtered into a nearly perfect sine. Interrupting at a
few hundred KHz is easy nowadays.

A Pi Pico would make a cool general-purpose signal generator. There
are a zillion possibilities for a product there, and would just need a
bit of code.

I\'m guessing that a 1 MHz interrupt rate could be supported on the DDS
core. Covering the audio range would be easy.

I\'ll architect it if someone will code it.

this does 400Hz sin/cos DDS on the two DACs on a 168MHz STM32F407
https://github.com/langwadt/singen

at 500ksps it spends about 50% cpu time in the interrupt calculating each sin/cos using ARMs fixed point lib
using a simple table lookup is uses ~25%

Table lookup is great for DDS, where not many MSBs of the phase
accumulator are used. I\'ve brute-forced a 16 bit sine function the
dumbest possible way, a lookup table with 65536 entries.

On a Pico, one would copy the sine table into RAM, maybe unfold it
from flash at powerup.

I wonder if a Pi Pico can run code, the DDS ISR, out of ram. That
would avoid cache misses.

I once build an audio sine generator with a 4040 counter driving an EPROM with sine table into an R2R DAC
The oscillator was a 4046, wide frequency range,
Everybody here has done that!

Who needs processors....

Well, they do all sorts of stuff and are crazy cheap. The RP2040 chip
is $1 and has two ARM cores. One core can run code out of RAM at 133
MHz, so could replace an FPGA in a lot of situations.

Software DDS in a cheap uP is cool. Only ADI still makes DDS chips and
they are expensive and a nuisance to interface. May as well use a uP
or a cheap FPGA and do a lot of other stuff.
sure, at low frequencies

So, you think FPGAs have significant frequency limitations? What sample rates are you thinking of? My impression was that usually the limitation is in the DAC, both sample rate and resolution.

Some time ago, I learned that insufficient phase accumulator resolution would generate spurs close to the frequency being generated, which makes them very hard to filter. This is not an intuitive outcome. So the resolution of the phase word needs to be large and the sine generator needs to accommodate this added resolution. As such, a simple lookup table is often not adequate, but other sine generation techniques need to be used to limit these close in spurs.

--

Rick C.

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

 

[Anthony William Sloman]

On Friday, June 30, 2023 at 2:15:26 AM UTC+10, Lasse Langwadt Christensen wrote:

torsdag den 29. juni 2023 kl. 17.42.57 UTC+2 skrev Anthony William Sloman:
On Friday, June 30, 2023 at 12:14:25 AM UTC+10, John Larkin wrote:
On Thu, 29 Jun 2023 05:16:41 GMT, Jan Panteltje <al...@comet.invalid> wrote:
On a sunny day (Wed, 28 Jun 2023 14:58:33 -0700) it happened John Larkin
jla...@highlandSNIPMEtechnology.com> wrote in <moap9i94f8h96d3di...@4ax.com>:
On Wed, 28 Jun 2023 14:01:13 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
onsdag den 28. juni 2023 kl. 16.40.32 UTC+2 skrev John Larkin:
On Wed, 28 Jun 2023 14:58:05 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:
On 26-06-2023 16:20, John Woodgate wrote:

At audio frequencies, software could DDS and then push a sine out of a single pin, PWM or delta-sigma. No DAC needed.
Pulse width modulation is Don Lancaster\'s magic sine waves which aren\'t all that magic. So is sigma-delta.

Magic sine waves are more like precalculated and optimized delta-sigma than PWM

Both are pulse width modulation, so there\'s no \"more like\" in it. There are lots of ways of doing pulse width modulation. You dissipate power on every switching edge, so there\'s a temptation to use fewer edges and not push the switching noise up to the high frequencies which are easier to filter out..

--
Bill Sloman, Sydney

 

[Lasse Langwadt Christensen]

torsdag den 29. juni 2023 kl. 17.26.05 UTC+2 skrev John Larkin:

On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable
frequency for a component bridge. I could use a 4017 and half a a 4013
(sorry about these ancient devices, but they are still good for some
things), but I would have to add something to make the crystal oscillate
unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I
can\'t see how to make it divide by 20. I know there is a technique that
combines some of the output signals via an EXOR to achieve divisors that
are not powers of 2, but I can\'t find information on which signals to combine.


Hey, John,

Nice to see you back on SED, man!
An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?


If you ac-couple into a cmos gate and add a high-value feedback
resistor, it sort of self-servoes its bias. And gets weird if there\'s
no signal.

https://assets.nexperia.com/documents/data-sheet/74HCU04.pdf

fig.13

 

[John Larkin]

On Thu, 29 Jun 2023 12:53:21 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 29. juni 2023 kl. 17.26.05 UTC+2 skrev John Larkin:
On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable
frequency for a component bridge. I could use a 4017 and half a a 4013
(sorry about these ancient devices, but they are still good for some
things), but I would have to add something to make the crystal oscillate
unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I
can\'t see how to make it divide by 20. I know there is a technique that
combines some of the output signals via an EXOR to achieve divisors that
are not powers of 2, but I can\'t find information on which signals to combine.


Hey, John,

Nice to see you back on SED, man!
An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?


If you ac-couple into a cmos gate and add a high-value feedback
resistor, it sort of self-servoes its bias. And gets weird if there\'s
no signal.

https://assets.nexperia.com/documents/data-sheet/74HCU04.pdf

fig.13

Delete R1 and it becomes my self-biasing comparator.

I invented that when I was a kid. It\'s barely possible someone else
used it first.

 

[Lasse Langwadt Christensen]

torsdag den 29. juni 2023 kl. 23.24.06 UTC+2 skrev John Larkin:

On Thu, 29 Jun 2023 12:53:21 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 29. juni 2023 kl. 17.26.05 UTC+2 skrev John Larkin:
On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable
frequency for a component bridge. I could use a 4017 and half a a 4013
(sorry about these ancient devices, but they are still good for some
things), but I would have to add something to make the crystal oscillate
unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I
can\'t see how to make it divide by 20. I know there is a technique that
combines some of the output signals via an EXOR to achieve divisors that
are not powers of 2, but I can\'t find information on which signals to combine.


Hey, John,

Nice to see you back on SED, man!
An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?


If you ac-couple into a cmos gate and add a high-value feedback
resistor, it sort of self-servoes its bias. And gets weird if there\'s
no signal.

https://assets.nexperia.com/documents/data-sheet/74HCU04.pdf

fig.13
Delete R1 and it becomes my self-biasing comparator.

I invented that when I was a kid. It\'s barely possible someone else
used it first.

I\'ve seen one inverter in a 74hc14 used as oscillator, then low pass filtered and used
to bias the rest of the inverters in the middle of the hysteresis \"window\"
to condition VR sensors, that have output that vary from <1V to +100V with speed

 

[Phil Hobbs]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

torsdag den 29. juni 2023 kl. 23.24.06 UTC+2 skrev John Larkin:
On Thu, 29 Jun 2023 12:53:21 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 29. juni 2023 kl. 17.26.05 UTC+2 skrev John Larkin:
On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable
frequency for a component bridge. I could use a 4017 and half a a 4013
(sorry about these ancient devices, but they are still good for some
things), but I would have to add something to make the crystal oscillate
unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I
can\'t see how to make it divide by 20. I know there is a technique that
combines some of the output signals via an EXOR to achieve divisors that
are not powers of 2, but I can\'t find information on which signals to combine.


Hey, John,

Nice to see you back on SED, man!
An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?


If you ac-couple into a cmos gate and add a high-value feedback
resistor, it sort of self-servoes its bias. And gets weird if there\'s
no signal.

https://assets.nexperia.com/documents/data-sheet/74HCU04.pdf

fig.13
Delete R1 and it becomes my self-biasing comparator.

I invented that when I was a kid. It\'s barely possible someone else
used it first.

I\'ve seen one inverter in a 74hc14 used as oscillator, then low pass filtered and used
to bias the rest of the inverters in the middle of the hysteresis \"window\"
to condition VR sensors, that have output that vary from <1V to +100V with speed

You’d have to be careful not to turn on the protection diodes. Any
asymmetry there would move the bias point.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC /
Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

 

[John Larkin]

On Thu, 29 Jun 2023 14:46:52 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 29. juni 2023 kl. 23.24.06 UTC+2 skrev John Larkin:
On Thu, 29 Jun 2023 12:53:21 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 29. juni 2023 kl. 17.26.05 UTC+2 skrev John Larkin:
On Mon, 26 Jun 2023 16:05:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

tirsdag den 27. juni 2023 kl. 00.39.14 UTC+2 skrev Phil Hobbs:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
John Woodgate <jmw2...@gmail.com> wrote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable
frequency for a component bridge. I could use a 4017 and half a a 4013
(sorry about these ancient devices, but they are still good for some
things), but I would have to add something to make the crystal oscillate
unless there is a way to use the other half of the 4013 to make the oscillator.

I also looked at using just a 4096, which gives me the oscillator, but I
can\'t see how to make it divide by 20. I know there is a technique that
combines some of the output signals via an EXOR to achieve divisors that
are not powers of 2, but I can\'t find information on which signals to combine.


Hey, John,

Nice to see you back on SED, man!
An HC40103 will do it, if you don’t mind a 5% duty cycle.

Plus a 74HC1G04 or something for the oscillator.

I usually see an unbuffered inverter used, and then you have to mess with drive levels
and load caps. Unless power is an issue is it worth he hassle when you can get an
oscillator you know will work for a dollar?


If you ac-couple into a cmos gate and add a high-value feedback
resistor, it sort of self-servoes its bias. And gets weird if there\'s
no signal.

https://assets.nexperia.com/documents/data-sheet/74HCU04.pdf

fig.13
Delete R1 and it becomes my self-biasing comparator.

I invented that when I was a kid. It\'s barely possible someone else
used it first.

I\'ve seen one inverter in a 74hc14 used as oscillator, then low pass filtered and used
to bias the rest of the inverters in the middle of the hysteresis \"window\"
to condition VR sensors, that have output that vary from <1V to +100V with speed

Schmitts by design don\'t have giant shoot-thru currents. Some gates
will fry if biased mid-range.

Magnetic coil and eddy-current type speed sensors tend to have voltage
linear on speed, so a modified integrator is the ideal thing to put
ahead of a comparator. I have a circuit around here somewhere...

A stepper motor makes a nice tach, but can shock you if you twist it
fast.

 

[whit3rd]

On Wednesday, June 28, 2023 at 11:06:54 PM UTC-7, Phil Allison wrote:

whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range; temperature coefficient has too much curvature.
AT-cut crystals can hold 10ppm over that range.

 

[Phil Allison]

whit3rd wrote:
-------------------------------

JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

> AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.



........ Phil

 

[Ricky]

On Thursday, June 29, 2023 at 7:13:58 PM UTC-4, whit3rd wrote:

On Wednesday, June 28, 2023 at 11:06:54 PM UTC-7, Phil Allison wrote:
whit3rd wrote:
------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range; temperature coefficient has too much curvature.
AT-cut crystals can hold 10ppm over that range.

People seem to toss around crystal specs very loosely. There are at least three specs I can think of off the top of my head. One is the initial spec, at 25°C. Another is for aging over time. Then crystals are specified over temperature. AT cut crystals are cut with a double inflection curve, which wavers over the temperature range, while XY cut crystals used mostly for low frequencies have a parabolic shape, with the peak at 25°C.

When people talk about 100 ppm, they are usually referring to the initial accuracy. The aging spec is some ppm/year. The AT cut temperature spec is bracketed over a range of temperature, while the XY cut crystal is described by the parabolic equation, so ppm/°C.

--

Rick C.

---+ Get 1,000 miles of free Supercharging
---+ Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Thursday, June 29, 2023 at 7:26:48 PM UTC-7, Phil Allison wrote:

whit3rd wrote:
-------------------------------
JW wtote:
I want to divide a 32768 Hz crystal frequency by 20 to get a stable frequency for a component bridge.

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;
** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that. Cost, to keep the temperature even, yes. Shame, no.

AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.

See here <https://www.jauch.com/blog/en/ask-the-engineer-how-temperature-sensitive-are-quartz-crystals/>

 

[Sylvia Else]

On 30-June-23 2:51 am, Ricky wrote:

On Thursday, June 29, 2023 at 8:04:12 AM UTC-4, Sylvia Else wrote:
On 29-June-23 1:59 am, Anthony William Sloman wrote:
On Thursday, June 29, 2023 at 12:30:05 AM UTC+10, John Larkin wrote:
On Wed, 28 Jun 2023 00:55:11 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Tuesday, June 27, 2023 at 11:28:46?PM UTC-7, John Larkin wrote:
On Wed, 28 Jun 2023 14:35:42 +1000, Sylvia Else <syl...@email.invalid
wrote:

Many years ago, I ANDed a bunch of outputs from counter stages, and fed
the result into the reset, to achieve division by some arbitrary
integer. I was electronically naive [*] at the time, and what I did may
have relied on the propagation delays to work properly. The application
would not have been sensitive to the occasional glitch.

Or perhaps I was lucky enough to have bought a counter with a
synchronous reset. Either way, it worked.

Sylvia

[*] OK, OK, you got me; even more electronically naive than now.
Actually, I think that it always works, sync or async.

Not necessarily: async reset can be fooled by the transient between-states
values of a slow slewing or ripple-delayed clocked event. Using the gate
output AT the main clock time should take you from N to zero, as long
as gate and slew delays aren\'t bigger than a clock period.

In the ripple counter case, I recall that the terminal count
transition is the first possible output of the AND gate, so it\'s safe
to drive an async clear. If you decode state N, it divides by N.

It the counter is long enough and slow enough you may never get something that looks like \"state N\" on the outputs of a ripple counter - the low order bits have got past \"state N\" before the high order bits have got to it.

I think a starting point for this is that the clock period is much
longer than the time required for the counter to settle into a
particular state.

However, given that the reset signal is generated when state N exists,
and the reset will cause state N to cease to exist, the reset pulse is
going to be quite short.

Why would you not register the reset pulse? Then it lasts a full clock cycle.


If one were trying it with something like this:

https://www.onsemi.com/pdf/datasheet/mc14040b-d.pdf

it might well work, but there\'s no way one would be complying with the
worst case reset pulse width requirement (page 4).

You would if you designed the circuit properly. Clock the reset FF from the rising edge of the clock, and the final state will appear for half a clock, and the counter will be in the zero state for a clock and a half.

By now, we\'re talking about three discrete ICs, for what should be a
simple task.

Sylvia.

 

[Phil Allison]

whit3rd wrote:
--------------------------

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that.

** It completely destroys your false assertions.

AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.

** +/- 50ppm drift is typical over that range.

Go away fool.

....... Phil

 

[whit3rd]

On Thursday, June 29, 2023 at 10:48:09 PM UTC-7, Phil Allison wrote:

whit3rd wrote:
--------------------------

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that.
** It completely destroys your false assertions.
AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.
** +/- 50ppm drift is typical over that range.

Huh? What \'drift\' do you mean? I\'m looking at the range of the
as-manufactured temperature response curves, none of which is flat, for maximum-over-temperature
range of an individual crystal. \'Typical\' isn\'t what I\'m looking at, but best-case
given that only those temperature curves are possible for AT shear-mode.

The \'typical\' that you refer to is just one of the possible manufacturing tolerances,
NOT the theoretical best available.

 

[Ricky]

On Friday, June 30, 2023 at 1:48:09 AM UTC-4, Phil Allison wrote:

whit3rd wrote:
--------------------------

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that.
** It completely destroys your false assertions.
AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.
** +/- 50ppm drift is typical over that range.

Go away fool.

AT cut crystals have a family of curves for the temperature vs. frequency plot, depending on the details of how they are cut. In general, they are cut for a double inflection, crossing the 0 error point three times. This reduces the range of frequency variance over a limited temperature range.

32,768 Hz crystals don\'t have a ± variance over temperature. They are specified at a temperature they are cut for, then vary only in one direction as temperature changes in either direction. The variance is by the square of the temperature difference... a parabola... fool.

Why do you have to be such a jerk about this stuff. Anyone can make a mistake, especially you. It doesn\'t need to be a huge emotional thing. You seem to get your ego all wrapped up in it, calling people names, then it often turns out you are wrong. WTF is wrong with you? What is your damage???

--

Rick C.

--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

 

[Phil Allison]

whit3rd wrote:
--------------------------

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that.
** It completely destroys your false assertions.
AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.
** +/- 50ppm drift is typical over that range.
Huh? What \'drift\' do you mean?

** FFS Go away !!!

 

[Phil Allison]

Tricky Ricky wrote:
------------------------------

whit3rd wrote:
--------------------------

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that.
** It completely destroys your false assertions.
AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.
** +/- 50ppm drift is typical over that range.

Go away fool.

AT cut crystals have a family of curves for the temperature vs. frequency plot, depending on the details of how they are cut. In general, they are cut for a double inflection, crossing the 0 error point three times. This reduces the range of frequency variance over a limited temperature range.

** Yawnnnnnn...................

> 32,768 Hz crystals don\'t have a ± variance over temperature.

** Really ?

Why do you have to be such a jerk about this stuff.
Anyone can make a mistake,

** But only desperate assholes like \"whitless\" persist in making the same ones over and over.
The guy is a troll and so are you.

FYI All trolls are fair game.

.......... Phil

 

[Ricky]

On Friday, June 30, 2023 at 3:51:18 AM UTC-4, Phil Allison wrote:

Tricky Ricky wrote:
------------------------------
whit3rd wrote:
--------------------------

Those clock/watch crystals are good, but only at wrist temperature; 100ppm frequency variance
is close enough for a wall clock.

** A 100ppm error amounts to over 4 minutes in a month.

Even budget \" Quartz\" clocks do about 100 times better than that.

The tuning fork crystals in those clocks aren\'t good for better than 100ppm
over a normal (0 to 70 C) temperature range;

** Shame a wall clock experiences no such extreme temp range.

I don\'t see any shame in that.
** It completely destroys your false assertions.
AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.
** +/- 50ppm drift is typical over that range.

Go away fool.

AT cut crystals have a family of curves for the temperature vs. frequency plot, depending on the details of how they are cut. In general, they are cut for a double inflection, crossing the 0 error point three times. This reduces the range of frequency variance over a limited temperature range.
** Yawnnnnnn...................
32,768 Hz crystals don\'t have a ± variance over temperature.
** Really ?
Why do you have to be such a jerk about this stuff.
Anyone can make a mistake,
** But only desperate assholes like \"whitless\" persist in making the same ones over and over.
The guy is a troll and so are you.

FYI All trolls are fair game.

.......... Phil

As usual, when you are wrong about something, you will not even consider checking any references. I\'ll make it easy for you. Here\'s a 32.768 kHz crystal data sheet. Notice the temperature spec is negative and in units of ppm/°C^2 That makes the curve a parabola, with the peak between 20 and 30 °C (the turnover temperature).

https://ecsxtal.com/store/pdf/ECX-1210.pdf

--

Rick C.

--++ Get 1,000 miles of free Supercharging
--++ Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Friday, June 30, 2023 at 12:42:12 AM UTC-7, Phil Allison wrote:

whit3rd wrote:

AT-cut crystals can hold 10ppm over that range.

** Per degree C - same as a watch crystal.

No, that\'s the whole range 0 to 70C.
** +/- 50ppm drift is typical over that range.
Huh? What \'drift\' do you mean?
** FFS Go away !!!

From where? Aren\'t you posting from somewhere near the Antipodes?

 

[Phil Allison]

whit3rd wrote:
----------------------

** FFS Go away !!!

From where?

** From me - you fucking retard.