B
B
Guest
jo wrote:
you can get some help.
It is better if you post the error messages that you're getting so
you can get some help.
V
vidhya
Guest
Thank you very much for the help...
I need to know if there is any software that can convert the Layout
file to either gdsII or CIF format...
I tried using the Import option..but apparently the cadence version i
have doesnt have the license for that option..
vidhya.
m_rajeswaran@yahoo.com (Rajeswaran M) wrote in message news:<cc6774d1.0308062145.77f84392@posting.google.com>...
I need to know if there is any software that can convert the Layout
file to either gdsII or CIF format...
I tried using the Import option..but apparently the cadence version i
have doesnt have the license for that option..
vidhya.
m_rajeswaran@yahoo.com (Rajeswaran M) wrote in message news:<cc6774d1.0308062145.77f84392@posting.google.com>...
E
Erik Wanta
Guest
File->Export->Stream
File->Export->CIF
vidhyaa123@hotmail.com (vidhya) wrote in message news:<7e4f4a47.0308111006.90e72d6@posting.google.com>...
File->Export->CIF
vidhyaa123@hotmail.com (vidhya) wrote in message news:<7e4f4a47.0308111006.90e72d6@posting.google.com>...
A
Andrew Beckett
Guest
Erik is right, but from what you've said, you don't have the license.
For stream out the product was 960 - however, in recent versions
(IC446 and IC50 I think), this is included in 300, and you no longer need
a separate license for stream in/out.
Andrew.
On 11 Aug 2003 16:54:52 -0700, erikwanta@starband.net (Erik Wanta) wrote:
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
For stream out the product was 960 - however, in recent versions
(IC446 and IC50 I think), this is included in 300, and you no longer need
a separate license for stream in/out.
Andrew.
On 11 Aug 2003 16:54:52 -0700, erikwanta@starband.net (Erik Wanta) wrote:
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
E
eda support guy
Guest
Erik Wanta wrote:
circuit simulation packages run really OK under wine. I tested crossover
wine on a redhat7.3.
But I believe it must be possible also to get spectre to run under
windows, as well. The x86 objects in the linux executable would have to
be first re-linked to the windows target, with all dependencies (such as
globetrotter libraries) and this is probably quite some work.
and, I might add that both the orcad pcb layout package and pspice
circuit simulation packages run really OK under wine. I tested crossover
wine on a redhat7.3.
But I believe it must be possible also to get spectre to run under
windows, as well. The x86 objects in the linux executable would have to
be first re-linked to the windows target, with all dependencies (such as
globetrotter libraries) and this is probably quite some work.
E
eda support guy
Guest
Tracy Groller wrote:
years ago. The layout verification tool and its integration in ic442
were quite impressive. And it was technically speaking not any longer a
proprietary tool, it was handled by some company called chameleon , if I
remember right. These guys were getting an email every time we started
the tool... they must have sold the patent to microsoft
I remember using and maintaining this LV tool and TIspice about 3Rajeswaran
Well the skill I submitted you could grab the rectangle
and determine the bBox and size occordingly whether
in the X or Y direction, it's just a geometry problem from
school .ie: get the dstFig~>bBox then resize in the X or Y direction .
Tracy
Rajeswaran M wrote:
Tracy,
The problem is not the oversizing, but oversizing in one direction (X
or Y).
Also, you have provided VER deck code (which is internal to us
I dont think most of people aware of VER based decks.
years ago. The layout verification tool and its integration in ic442
were quite impressive. And it was technically speaking not any longer a
proprietary tool, it was handled by some company called chameleon , if I
remember right. These guys were getting an email every time we started
the tool... they must have sold the patent to microsoft
E
eda support guy
Guest
Vladimir wrote:
halted simulation: the checkpoint data does not capture the state of the
device models, so those will show transient effects that can
significantly affect your circuit behaviour.
The recover from checkpoint will not be a perfect continuation of the
halted simulation: the checkpoint data does not capture the state of the
device models, so those will show transient effects that can
significantly affect your circuit behaviour.
T
Tracy Groller
Guest
The LV tool your referring to is called K2 Chameleon which bought the
tool from TI several years
ago, which was developed inhouse by TI, Cadence has since bought K2 so
in the future it should
show up for all users .
eda support guy wrote:
\ ~ ~ ///
---- ( @ @ )
| | ======oOOo==(_)==oOOo=======================================
| |__<*> ___ Tracy Groller | Texas Instruments, Inc.
| _|III|_ | ------------------| HPA EDA Artisan Development
_____| /_ III _/ \ TI MSGID: TAG2 | P.O. Box 660199, MS 8729
\_ /III/ | PC Drop: PFLL | Dallas, Texas 75266
\ _ /III/ _| -------------------------------------------------
\_/ \ \___> - Phone: (214) 480-6385 Fax:
\ / Email: h-groller@ti.com
\ \ =======================================================
\---\
tool from TI several years
ago, which was developed inhouse by TI, Cadence has since bought K2 so
in the future it should
show up for all users .
eda support guy wrote:
--Tracy Groller wrote:
Rajeswaran
Well the skill I submitted you could grab the rectangle
and determine the bBox and size occordingly whether
in the X or Y direction, it's just a geometry problem from
school .ie: get the dstFig~>bBox then resize in the X or Y direction .
Tracy
Rajeswaran M wrote:
Tracy,
The problem is not the oversizing, but oversizing in one direction (X
or Y).
Also, you have provided VER deck code (which is internal to us
I dont think most of people aware of VER based decks.
I remember using and maintaining this LV tool and TIspice about 3
years ago. The layout verification tool and its integration in ic442
were quite impressive. And it was technically speaking not any longer
a proprietary tool, it was handled by some company called chameleon ,
if I remember right. These guys were getting an email every time we
started the tool... they must have sold the patent to microsoft
\ ~ ~ ///
---- ( @ @ )
| | ======oOOo==(_)==oOOo=======================================
| |__<*> ___ Tracy Groller | Texas Instruments, Inc.
| _|III|_ | ------------------| HPA EDA Artisan Development
_____| /_ III _/ \ TI MSGID: TAG2 | P.O. Box 660199, MS 8729
\_ /III/ | PC Drop: PFLL | Dallas, Texas 75266
\ _ /III/ _| -------------------------------------------------
\_/ \ \___> - Phone: (214) 480-6385 Fax:
\ / Email: h-groller@ti.com
\ \ =======================================================
\---\
R
Rajeswaran M
Guest
Now Cadence is owning the tool I thought the tool was developed by and for TI.
Solving this re-sizing problem using LV deck has same effort as with Assura/Diva.
eda support guy <cad_support_at_catena_dot_the_netherlands> wrote in message news:<3f38fa65@shknews01>...
I thought the tool was developed by and for TI.Solving this re-sizing problem using LV deck has same effort as with Assura/Diva.
eda support guy <cad_support_at_catena_dot_the_netherlands> wrote in message news:<3f38fa65@shknews01>...
Tracy Groller wrote:
Rajeswaran
Well the skill I submitted you could grab the rectangle
and determine the bBox and size occordingly whether
in the X or Y direction, it's just a geometry problem from
school .ie: get the dstFig~>bBox then resize in the X or Y direction .
Tracy
Rajeswaran M wrote:
Tracy,
The problem is not the oversizing, but oversizing in one direction (X
or Y).
Also, you have provided VER deck code (which is internal to us
I dont think most of people aware of VER based decks.
I remember using and maintaining this LV tool and TIspice about 3
years ago. The layout verification tool and its integration in ic442
were quite impressive. And it was technically speaking not any longer a
proprietary tool, it was handled by some company called chameleon , if I
remember right. These guys were getting an email every time we started
the tool... they must have sold the patent to microsoft
T
Tracy Groller
Guest
The tool was created in house by TI a good 20 years ago .
Then sold to K2 which was then bought by Cadence .
The resize can be done in skill .
Rajeswaran M wrote:
\ ~ ~ ///
---- ( @ @ )
| | ======oOOo==(_)==oOOo=======================================
| |__<*> ___ Tracy Groller | Texas Instruments, Inc.
| _|III|_ | ------------------| HPA EDA Artisan Development
_____| /_ III _/ \ TI MSGID: TAG2 | P.O. Box 660199, MS 8729
\_ /III/ | PC Drop: PFLL | Dallas, Texas 75266
\ _ /III/ _| -------------------------------------------------
\_/ \ \___> - Phone: (214) 480-6385 Fax:
\ / Email: h-groller@ti.com
\ \ =======================================================
\---\
Then sold to K2 which was then bought by Cadence .
The resize can be done in skill .
Rajeswaran M wrote:
--Now Cadence is owning the tool
Solving this re-sizing problem using LV deck has same effort as with Assura/Diva.
eda support guy <cad_support_at_catena_dot_the_netherlands> wrote in message news:<3f38fa65@shknews01>...
Tracy Groller wrote:
Rajeswaran
Well the skill I submitted you could grab the rectangle
and determine the bBox and size occordingly whether
in the X or Y direction, it's just a geometry problem from
school .ie: get the dstFig~>bBox then resize in the X or Y direction .
Tracy
Rajeswaran M wrote:
Tracy,
The problem is not the oversizing, but oversizing in one direction (X
or Y).
Also, you have provided VER deck code (which is internal to us
I dont think most of people aware of VER based decks.
I remember using and maintaining this LV tool and TIspice about 3
years ago. The layout verification tool and its integration in ic442
were quite impressive. And it was technically speaking not any longer a
proprietary tool, it was handled by some company called chameleon , if I
remember right. These guys were getting an email every time we started
the tool... they must have sold the patent to microsoft
\ ~ ~ ///
---- ( @ @ )
| | ======oOOo==(_)==oOOo=======================================
| |__<*> ___ Tracy Groller | Texas Instruments, Inc.
| _|III|_ | ------------------| HPA EDA Artisan Development
_____| /_ III _/ \ TI MSGID: TAG2 | P.O. Box 660199, MS 8729
\_ /III/ | PC Drop: PFLL | Dallas, Texas 75266
\ _ /III/ _| -------------------------------------------------
\_/ \ \___> - Phone: (214) 480-6385 Fax:
\ / Email: h-groller@ti.com
\ \ =======================================================
\---\
B
B
Guest
If I recall well cdsSpice has been frozen since a while and I don't
think it supports a 0.18u tech. So unless you have good reasons to
use it, you're better off using a better alternative. may be you have
access to spectre or hspice ... If yes, go ahead and use and repost
if you need help.
One way to test this, is to use a level 3 (use anyone since this is
for test purposes only) and make sure the line where the "m1" is
declared is correct.
Badhrinath Jagannathan wrote:
think it supports a 0.18u tech. So unless you have good reasons to
use it, you're better off using a better alternative. may be you have
access to spectre or hspice ... If yes, go ahead and use and repost
if you need help.
One way to test this, is to use a level 3 (use anyone since this is
for test purposes only) and make sure the line where the "m1" is
declared is correct.
Badhrinath Jagannathan wrote:
E
Erik Wanta
Guest
I don't see a field to specify a seed in the MC GUI.
The documentation says:
If you do not specify a seed, then each time that you run the
analysis, you get different results; that is, a different stream of
pseudorandom numbers is generated. If you do not specify a seed, the
Spectre simulator uses the Spectre process id (PID) as a seed.
I don't see this to be the case however. If I do a Simulation->Create
Input Files I always get seed=1 in the MC section of the netlist.
---
Erik
"Yan Zhang" <yz3w@virginia.edu> wrote in message news:<bj2rls$dkg$1@murdoch.acc.Virginia.EDU>...
The documentation says:
If you do not specify a seed, then each time that you run the
analysis, you get different results; that is, a different stream of
pseudorandom numbers is generated. If you do not specify a seed, the
Spectre simulator uses the Spectre process id (PID) as a seed.
I don't see this to be the case however. If I do a Simulation->Create
Input Files I always get seed=1 in the MC section of the netlist.
---
Erik
"Yan Zhang" <yz3w@virginia.edu> wrote in message news:<bj2rls$dkg$1@murdoch.acc.Virginia.EDU>...
M
Muzaffer Kal
Guest
On 2 Sep 2003 14:07:16 -0700, mizhael@yahoo.com (walala) wrote:
and utilization are at that point. It is possible that you're using
the Floorplan command in SE incorrectly.
Muzaffer Kal
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
Look at your floor plan output to see what the core size, site size
and utilization are at that point. It is possible that you're using
the Floorplan command in SE incorrectly.
Muzaffer Kal
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
A
Andrew Beckett
Guest
Yes, the seed is currently fixed. There's a PCR to allow the seed to be
specified in the UI (I don't remember the PCR number) - I think it has
come up in the past on this group (check google).
The idea behind having a fixed seed was to allow you to have reproducable
results - and you can (sort of) workaround the problem by changing the starting
run number on the form.
I'm assuming Yan that you're not saying that the results for each point in
the monte-carlo are the same as all the other points, but rather that the
results for the whole set of runs stays the same?
If the results are the same point to point, then that would suggest that
you either have models which don't vary, or more likely that you have
expressions for your outputs which reference the wrong set of results.
Andrew.
On 2 Sep 2003 18:34:30 -0700, erikwanta@starband.net (Erik Wanta) wrote:
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
specified in the UI (I don't remember the PCR number) - I think it has
come up in the past on this group (check google).
The idea behind having a fixed seed was to allow you to have reproducable
results - and you can (sort of) workaround the problem by changing the starting
run number on the form.
I'm assuming Yan that you're not saying that the results for each point in
the monte-carlo are the same as all the other points, but rather that the
results for the whole set of runs stays the same?
If the results are the same point to point, then that would suggest that
you either have models which don't vary, or more likely that you have
expressions for your outputs which reference the wrong set of results.
Andrew.
On 2 Sep 2003 18:34:30 -0700, erikwanta@starband.net (Erik Wanta) wrote:
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
E
eda support guy
Guest
Erik Wanta wrote:
the partial answer is :
$(cds_root)/share/license/products.dfII
but if you look, for instance, at the new cadence download site you find
more details, so I suspect there is a better source for this mapping. I
plan to find this and add a better feature# -> name conversion to the
PHPlicensewatcher ( it is a tool from sourceforge ).
Nowadays, I don t have too much of a problem with the "feature number"
to "feature name" mapping, but I have more of a problem with the
"corporate product name" to "download product name" mapping.
Especially since the corporate names and product bundles change so
often. And the download names are 3 letters acronym that are on most web
pages unexpanded.
An illustration:
- Try for instance a search of "LDV" on the cadence corporate site: I
had one(1) hit
- then, on the download site, look at the products inside solaris-LDV,
and compare with windows-LDV
- go back to corporate site search, and try "NC-sim" "inca" "AMS"
"envisia", try to map the existing links between those, and with LDV.
connect the dots and put color inside ;-)
Even the tool names change sometimes (analog artist becomes analog
design environment, device level editor becomes virtuoso XL).
<calimero mode> I wish cadence thought less about pleasing lawyers and
PR, and more about the end-users, or even about us, poor support drones
! </calimero mode> ;-]
As for marketing, I don t know about the US or Japan, but around here
decision-makers find this "change the package and sell the same stuff" a
very cheap trick, a rather unexpected one for a market leader. That's a
shame, because some of those tools are good.
Erik,
the partial answer is :
$(cds_root)/share/license/products.dfII
but if you look, for instance, at the new cadence download site you find
more details, so I suspect there is a better source for this mapping. I
plan to find this and add a better feature# -> name conversion to the
PHPlicensewatcher ( it is a tool from sourceforge ).
Nowadays, I don t have too much of a problem with the "feature number"
to "feature name" mapping, but I have more of a problem with the
"corporate product name" to "download product name" mapping.
Especially since the corporate names and product bundles change so
often. And the download names are 3 letters acronym that are on most web
pages unexpanded.
An illustration:
- Try for instance a search of "LDV" on the cadence corporate site: I
had one(1) hit
- then, on the download site, look at the products inside solaris-LDV,
and compare with windows-LDV
- go back to corporate site search, and try "NC-sim" "inca" "AMS"
"envisia", try to map the existing links between those, and with LDV.
connect the dots and put color inside ;-)
Even the tool names change sometimes (analog artist becomes analog
design environment, device level editor becomes virtuoso XL).
<calimero mode> I wish cadence thought less about pleasing lawyers and
PR, and more about the end-users, or even about us, poor support drones
! </calimero mode> ;-]
As for marketing, I don t know about the US or Japan, but around here
decision-makers find this "change the package and sell the same stuff" a
very cheap trick, a rather unexpected one for a market leader. That's a
shame, because some of those tools are good.
E
Erik Wanta
Guest
FYI, the PCR number is 432223.
---
Erik
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<kcsalvs4t13hjse8fu9selr0p9r1isj2lk@4ax.com>...
---
Erik
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<kcsalvs4t13hjse8fu9selr0p9r1isj2lk@4ax.com>...
E
Edward J Kalenda
Guest
geHiCommonFindMarker() is a little better than Verify/Markers/Find but
it still has all the markers in a single list. Maybe if it were sorted
it would do what he needs.
I think what Jan really wants is something like what Assura has: a list
of the unique marker strings. When you click on a string, you can then
walk through the markers with that string. The drcDisplay.il file that
was posted here some time ago does a fairly nice job of this. I've
attached it below.
On Fri, 22 Aug 2003 12:16:16 -0400, "Sam Tran" <tran@orion-design.com>
wrote:
it still has all the markers in a single list. Maybe if it were sorted
it would do what he needs.
I think what Jan really wants is something like what Assura has: a list
of the unique marker strings. When you click on a string, you can then
walk through the markers with that string. The drcDisplay.il file that
was posted here some time ago does a fairly nice job of this. I've
attached it below.
On Fri, 22 Aug 2003 12:16:16 -0400, "Sam Tran" <tran@orion-design.com>
wrote:
B
boki
Guest
Dear Andrew,
We have this program in our server, but.. could you please
tell me how to start it ... ( command ), something like icde / icfb /
layout ...
Thanks a lot!
Boki.
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<ddr9lvc6egfmk16nj7sj1lb2dgd6g9fgj2@4ax.com>...
We have this program in our server, but.. could you please
tell me how to start it ... ( command ), something like icde / icfb /
layout ...
Thanks a lot!
Boki.
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<ddr9lvc6egfmk16nj7sj1lb2dgd6g9fgj2@4ax.com>...
E
eda support guy
Guest
The best customisation of the verify/marker/find I have seen so far
was in a BiCMOS design kit from National Semiconductor. If there is
anyone here from NS who has the authority to post this code, that would
be nice. It fixed the problem mentioned.
I suppose this kind of customisation gives no big edge in layout
productivity, it more an "annoyance-fix" for beginner layouters, while
the experienced ones will use the search from virtuoso, or simply an LSW
valid layers+area select, as a workaound.
Oh, about the search from virtuoso:
has anyone used it on schematics ? I did that a few times because it is
more advanced than the search from composer. Simply copy/paste the
schematic to a layout, do the search/replace, an copy the result back to
the schematic. I noticed no problem, but it doesn t mean that I really
did not loose any database info in the operation. Anyone has a good idea
of the consequences of doing this ? Or knows a trick to hook a better
search/replace in composer ?
Edward J Kalenda wrote:
was in a BiCMOS design kit from National Semiconductor. If there is
anyone here from NS who has the authority to post this code, that would
be nice. It fixed the problem mentioned.
I suppose this kind of customisation gives no big edge in layout
productivity, it more an "annoyance-fix" for beginner layouters, while
the experienced ones will use the search from virtuoso, or simply an LSW
valid layers+area select, as a workaound.
Oh, about the search from virtuoso:
has anyone used it on schematics ? I did that a few times because it is
more advanced than the search from composer. Simply copy/paste the
schematic to a layout, do the search/replace, an copy the result back to
the schematic. I noticed no problem, but it doesn t mean that I really
did not loose any database info in the operation. Anyone has a good idea
of the consequences of doing this ? Or knows a trick to hook a better
search/replace in composer ?
Edward J Kalenda wrote:
E
eda support guy
Guest
Indeed,
it is very useful to be able to go from a given MC run in
results/waveform back to the state of the process and models. Around
here, the typical designer has already pushed the envelope on disk usage
and CPU time before he starts to do MC runs, so he will not be able to
save all results, and he will not have the time to simply rerun the
first 73 runs when he notices something "interesting" in the 74th MC run
and want to know more about it.
Even with the possibility to set the seed to the value of a given MC
run, there is still quite some work to relate the seed value to the
process parameter and model parameter values. And the process params are
what you want to know so that you can understand how the process state
makes the circuit fail, and be able to correct.
Since MC, corner runs and such are late in the electrical design
phase, at a time when people a also busy documenting, preparing
presentations, meetings, and close to a deadline, they will almost never
go through much trouble to trace back what this particular MC run was
doing to their circuit. They will rather make assumptions (that they don
t check by simulation), fix the circuit, start a new set of simulations
and check only that the worst case situation doesn happen anymore.
Andrew Beckett wrote:
it is very useful to be able to go from a given MC run in
results/waveform back to the state of the process and models. Around
here, the typical designer has already pushed the envelope on disk usage
and CPU time before he starts to do MC runs, so he will not be able to
save all results, and he will not have the time to simply rerun the
first 73 runs when he notices something "interesting" in the 74th MC run
and want to know more about it.
Even with the possibility to set the seed to the value of a given MC
run, there is still quite some work to relate the seed value to the
process parameter and model parameter values. And the process params are
what you want to know so that you can understand how the process state
makes the circuit fail, and be able to correct.
Since MC, corner runs and such are late in the electrical design
phase, at a time when people a also busy documenting, preparing
presentations, meetings, and close to a deadline, they will almost never
go through much trouble to trace back what this particular MC run was
doing to their circuit. They will rather make assumptions (that they don
t check by simulation), fix the circuit, start a new set of simulations
and check only that the worst case situation doesn happen anymore.
Andrew Beckett wrote: