F
fogh
Guest
satya wrote:
spectre -h montecarlo
spectre -h export
it is generally true but there is an exception.
spectre -h montecarlo
spectre -h export
S
Stefano Zanella
Guest
let's say monte carlo only
Stefano
spectre -h export
****************************************************************************
The export feature is not supported. It is designated for internal use only.
****************************************************************************
fogh wrote:
Stefano
spectre -h export
****************************************************************************
The export feature is not supported. It is designated for internal use only.
****************************************************************************
fogh wrote:
S
Svenn Are Bjerkem
Guest
In article <436ff2ce@darkstar>, Linh Hoang <linhAtataTucscPerioDedu>
says...
dc_shell is (at the time of writing ;-) ) a product of that company.
--
Svenn
says...
I think this is a question rather asked in a Synopsys newsgroup as
dc_shell is (at the time of writing ;-) ) a product of that company.
--
Svenn
A
Andrew Beckett
Guest
Oh, it's really not as complicated as all that! Starting with the one
that is wanted, here's a variety of examples of varying complexity (the
examples are followed with an representation of the sequence they
expand to).
Put simply - 0:n*m repeats each bit m times, whereas (0:n)*m repeats
the whole 0:n range m times one after the other. Then you can concatenate
them too, and further group them with parentheses, and so on.
x<0:31*4>
0,0,0,0,1,1,1,1,2,2,2,2....,31,31,31,31
x<(0:31)*4>
0,1,2,3,4,5,6,...31,0,1,2,3,4,5,6,...31,...
x<(0:31*2)*2>
0,0,1,1,2,2,3,3,...,31,31,0,0,1,1,2,2,3,3,...,31,31
x<0:31*2,31:0*2>
0,0,1,1,2,2,3,3,...,31,31,31,31,30,30,29,29,...,2,2,1,1,0,0
x<(0:31,31:0)*2>
0,1,2,3,4,...,31,31,30,29,...,2,1,0,0,1,2,3,4,...,31,31,30,29,...,2,1,0
Regards,
Andrew.
On Mon, 31 Oct 2005 21:33:38 -0500, "Gerry Vandevalk" <g_vandevalk@yahoo.com>
wrote:
that is wanted, here's a variety of examples of varying complexity (the
examples are followed with an representation of the sequence they
expand to).
Put simply - 0:n*m repeats each bit m times, whereas (0:n)*m repeats
the whole 0:n range m times one after the other. Then you can concatenate
them too, and further group them with parentheses, and so on.
x<0:31*4>
0,0,0,0,1,1,1,1,2,2,2,2....,31,31,31,31
x<(0:31)*4>
0,1,2,3,4,5,6,...31,0,1,2,3,4,5,6,...31,...
x<(0:31*2)*2>
0,0,1,1,2,2,3,3,...,31,31,0,0,1,1,2,2,3,3,...,31,31
x<0:31*2,31:0*2>
0,0,1,1,2,2,3,3,...,31,31,31,31,30,30,29,29,...,2,2,1,1,0,0
x<(0:31,31:0)*2>
0,1,2,3,4,...,31,31,30,29,...,2,1,0,0,1,2,3,4,...,31,31,30,29,...,2,1,0
Regards,
Andrew.
On Mon, 31 Oct 2005 21:33:38 -0500, "Gerry Vandevalk" <g_vandevalk@yahoo.com>
wrote:
All:
I defy anyone at Cadence to tell me exactly how bus ripping works.
The documents below describe a subset legal bus definitions that work, but
other esoteric combinations work.
The custom memory group at my ex-employer used some pretty wild combinations
that worked.
As a matter of fact, they would write bus def's just like you describe them
( something like <4*i<31:0>> and they would get the bus you describe .. )
I will ask former member of the group for the syntax he uses and post it!
-- Gerry
"Bernd Fischer" <""bernd.fischer\"@xignal-A%&HY%$v#&G=.de"> wrote in message
news:3se81dFnsi5dU1@individual.net...
Virtuoso Schematic Editor User Guide,
Section: Multiple-Bit Wire Connections
Section: Wire-to-Iterated Instance Connections
Section: Multiple-Bit Wire Naming Conventions
Bernd
JC wrote:
Hi,
Using the Cadence schematic tool, I have a cell instantiated 128 times,
Icell1<127:0>.
I want groups of 4 cells at the time to have the same input, so there
will be 32 signals, x<31:0> going to 128 cells.
I can label the bus to the input
etc., x<1>, x<1>, x<1>, x<1>, x<0>, x<0>, x<0>, x<0
but it is a very long string.
What is the syntax to abbreviate it, such as
etc., ((x<1>*4), ((x<0>
or something even shorter such as
bit=0; (((x<bit + 1>
Thanks,
Joe
joe.clark@nospm@adtran.com
E
Ed "Mr. Diva" Kalenda
Guest
Thanks for the test case. I was able to find the problem and adjust the
rules compiler to handle it.
Every coefficient is zero for elec to metal2. The rule compiler was
changed to skip the processing steps with a coefficient of zero since
they won't produce anything and was skipping them all. This caused the
message about an invalid multiLevelParasitic rule.
The techfile for the PDK should be corrected to have meaningful values,
but that's up to the NCSU people.
The rule deck is also odd in that it has duplicate cap clauses for elec
to metal2, and for elec to metal1.
On Mon, 24 Oct 2005 13:01:09 -0700, Edward J Kalenda <ed@kalenda.com>
wrote:
Cadence Design Systems
This is just me blathering, not the company, since they don't let talk for them.
rules compiler to handle it.
Every coefficient is zero for elec to metal2. The rule compiler was
changed to skip the processing steps with a coefficient of zero since
they won't produce anything and was skipping them all. This caused the
message about an invalid multiLevelParasitic rule.
The techfile for the PDK should be corrected to have meaningful values,
but that's up to the NCSU people.
The rule deck is also odd in that it has duplicate cap clauses for elec
to metal2, and for elec to metal1.
On Mon, 24 Oct 2005 13:01:09 -0700, Edward J Kalenda <ed@kalenda.com>
wrote:
Ed "Mr. Diva" Kalenda
Cadence Design Systems
This is just me blathering, not the company, since they don't let talk for them.
J
Johannes Grad
Guest
Hi Ed,
thanks so much for fixing this Diva problem.
I posted a patch to the NCSU PDK 1.4 here:
http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=53
To summarize, Ed fixed 2 bugs in the NCSU PDK:
- Syntax error in divaDRC.rul
- Diva Extraction fails under IC51-41
Patches for both bugs are provided at the above website.
Thanks again,
Johannes Grad
Ed Mr. Diva Kalenda wrote:
thanks so much for fixing this Diva problem.
I posted a patch to the NCSU PDK 1.4 here:
http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=53
To summarize, Ed fixed 2 bugs in the NCSU PDK:
- Syntax error in divaDRC.rul
- Diva Extraction fails under IC51-41
Patches for both bugs are provided at the above website.
Thanks again,
Johannes Grad
Ed Mr. Diva Kalenda wrote:
F
fogh
Guest
Yes Stefano,
I just wanted to point out that documentation is not too consistent, because
it shows that you have to use export in monte-carlo, but then claims that export
is not useful for the usual designer.... Unless "internal use" meant something
else
Stefano Zanella wrote:
I just wanted to point out that documentation is not too consistent, because
it shows that you have to use export in monte-carlo, but then claims that export
is not useful for the usual designer.... Unless "internal use" meant something
else
Stefano Zanella wrote:
G
Gerry Vandevalk
Guest
Yes it can be easy, but you can nest them in complex ways and they still
work.
(negative counting works too in x<31:0> arrays or more complex like
y<31:0:-2> (i think!) )
by the way ... don't you mean
x<0:31>*4
expands to
x<0>,x<0>,x<0>,x<0>,x<1>,x<1>, ... ,x<31>,x<31>
etc.
-- Gerry
"Andrew Beckett" <andrewb@DcEaLdEeTnEcTe.HcIoSm> wrote in message
news:hkt4n156ucsjit4plg4ojnfp376b60po3d@4ax.com...
work.
(negative counting works too in x<31:0> arrays or more complex like
y<31:0:-2> (i think!) )
by the way ... don't you mean
x<0:31>*4
expands to
x<0>,x<0>,x<0>,x<0>,x<1>,x<1>, ... ,x<31>,x<31>
etc.
-- Gerry
"Andrew Beckett" <andrewb@DcEaLdEeTnEcTe.HcIoSm> wrote in message
news:hkt4n156ucsjit4plg4ojnfp376b60po3d@4ax.com...
Oh, it's really not as complicated as all that! Starting with the one
that is wanted, here's a variety of examples of varying complexity (the
examples are followed with an representation of the sequence they
expand to).
Put simply - 0:n*m repeats each bit m times, whereas (0:n)*m repeats
the whole 0:n range m times one after the other. Then you can concatenate
them too, and further group them with parentheses, and so on.
x<0:31*4
0,0,0,0,1,1,1,1,2,2,2,2....,31,31,31,31
x<(0:31)*4
0,1,2,3,4,5,6,...31,0,1,2,3,4,5,6,...31,...
x<(0:31*2)*2
0,0,1,1,2,2,3,3,...,31,31,0,0,1,1,2,2,3,3,...,31,31
x<0:31*2,31:0*2
0,0,1,1,2,2,3,3,...,31,31,31,31,30,30,29,29,...,2,2,1,1,0,0
x<(0:31,31:0)*2
0,1,2,3,4,...,31,31,30,29,...,2,1,0,0,1,2,3,4,...,31,31,30,29,...,2,1,0
Regards,
Andrew.
On Mon, 31 Oct 2005 21:33:38 -0500, "Gerry Vandevalk"
g_vandevalk@yahoo.com
wrote:
All:
I defy anyone at Cadence to tell me exactly how bus ripping works.
The documents below describe a subset legal bus definitions that work, but
other esoteric combinations work.
The custom memory group at my ex-employer used some pretty wild
combinations
that worked.
As a matter of fact, they would write bus def's just like you describe
them
( something like <4*i<31:0>> and they would get the bus you describe .. )
I will ask former member of the group for the syntax he uses and post it!
-- Gerry
"Bernd Fischer" <""bernd.fischer\"@xignal-A%&HY%$v#&G=.de"> wrote in
message
news:3se81dFnsi5dU1@individual.net...
Virtuoso Schematic Editor User Guide,
Section: Multiple-Bit Wire Connections
Section: Wire-to-Iterated Instance Connections
Section: Multiple-Bit Wire Naming Conventions
Bernd
JC wrote:
Hi,
Using the Cadence schematic tool, I have a cell instantiated 128 times,
Icell1<127:0>.
I want groups of 4 cells at the time to have the same input, so there
will be 32 signals, x<31:0> going to 128 cells.
I can label the bus to the input
etc., x<1>, x<1>, x<1>, x<1>, x<0>, x<0>, x<0>, x<0
but it is a very long string.
What is the syntax to abbreviate it, such as
etc., ((x<1>
or something even shorter such as
bit=0; (((x<bit + 1>
Thanks,
Joe
joe.clark@nospm@adtran.com
R
Roger Light
Guest
Andrew Beckett wrote:
idea it was that powerful. Thank you!
Is it possible to have the naming skip a wire? So if the bus wires I
want to name are every other wire? Something like:
a<0> b<0> a<1> b<1> a<2> b<2>
Or is naming this possible all in one go?
Most of the reason for me wanting to do that is solved by iterated
instances anyway - I didn't know about them either. I guess I should
read more of the documentation, but there is just so much to get through.
Thanks again,
Roger
Man, that was useful. I've always used <0:31> with expansion, but had no
idea it was that powerful. Thank you!
Is it possible to have the naming skip a wire? So if the bus wires I
want to name are every other wire? Something like:
a<0> b<0> a<1> b<1> a<2> b<2>
Or is naming this possible all in one go?
Most of the reason for me wanting to do that is solved by iterated
instances anyway - I didn't know about them either. I guess I should
read more of the documentation, but there is just so much to get through.
Thanks again,
Roger
R
Roger Light
Guest
Roger Light wrote:
leave out the net tap *name* and just use the index:
<0> <0> <1> <1> <2> <2>
From comphelp.pdf section "Tapping Wire Intersections by Name".
Thanks,
Roger
Answering my own question, as long as the bus is named elsewhere, I can
leave out the net tap *name* and just use the index:
<0> <0> <1> <1> <2> <2>
From comphelp.pdf section "Tapping Wire Intersections by Name".
Thanks,
Roger
J
Joe Clark
Guest
Thanks for the answers and ideas, guys.
Joe
"JC" <no@spam.com> wrote in message
news:adbdd$43616149$d0fb9763$31862@API-DIGITAL.COM...
Joe
"JC" <no@spam.com> wrote in message
news:adbdd$43616149$d0fb9763$31862@API-DIGITAL.COM...
Hi,
Using the Cadence schematic tool, I have a cell instantiated 128 times,
Icell1<127:0>.
I want groups of 4 cells at the time to have the same input, so there will
be 32 signals, x<31:0> going to 128 cells.
I can label the bus to the input
etc., x<1>, x<1>, x<1>, x<1>, x<0>, x<0>, x<0>, x<0
but it is a very long string.
What is the syntax to abbreviate it, such as
etc., ((x<1>
or something even shorter such as
bit=0; (((x<bit + 1>
Thanks,
Joe
joe.clark@nospm@adtran.com
F
firegardeneve
Guest
You might want to check the gate file that to check if slc identfies
the logic correctly or no. You can use the dg_gate command. According
to the documentation there is no BUFBD1 type of a cell, but there are
BUFIF0 and BUFIF1. If this is the error, then you can make corrections
in the gate file and then run db_gsim again on the modified gate file.
There is a section on Making gate file corrections in the document that
you would want to look at.
hope that helps.
the logic correctly or no. You can use the dg_gate command. According
to the documentation there is no BUFBD1 type of a cell, but there are
BUFIF0 and BUFIF1. If this is the error, then you can make corrections
in the gate file and then run db_gsim again on the modified gate file.
There is a section on Making gate file corrections in the document that
you would want to look at.
hope that helps.
O
okguy
Guest
I succeed to change the terminal name but in the schematic the net names
connected by label are not change. I just rename it: term~>name=new_name
I cannot find the way to chage the net label using skill code.
Any trick ?
connected by label are not change. I just rename it: term~>name=new_name
I cannot find the way to chage the net label using skill code.
Any trick ?
T
Trevor Bowen
Guest
It is possible for the database to support a net name that is different
than the attached terminal name. However, changing the terminal name,
as you suggested, and then performing a "Check and Save" will update the
old net to the new name.
In case you do not want to have run "Check and Save", and you want your
code to do it for you, try this:
dbMergeNet(dbCreateNet(term~>cellView new_name) term~>net)
term~>name = new_name
Currently, you cannot rename a net directly, as you can for a terminal,
(I think this should be possible, personally) so you have to create a
new net with the new name and merge the old net into the new net.
okguy wrote:
than the attached terminal name. However, changing the terminal name,
as you suggested, and then performing a "Check and Save" will update the
old net to the new name.
In case you do not want to have run "Check and Save", and you want your
code to do it for you, try this:
dbMergeNet(dbCreateNet(term~>cellView new_name) term~>net)
term~>name = new_name
Currently, you cannot rename a net directly, as you can for a terminal,
(I think this should be possible, personally) so you have to create a
new net with the new name and merge the old net into the new net.
okguy wrote:
O
okguy
Guest
I tried it but it does not change the labels.
My problem is that it generate errors when netlisting. Another way could
be to selct all labels and rename the label. Do you know the skill to
rename a label ?
OkGuy
My problem is that it generate errors when netlisting. Another way could
be to selct all labels and rename the label. Do you know the skill to
rename a label ?
OkGuy
A
Andrew Beckett
Guest
On Tue, 22 Nov 2005 20:49:40 -0500, "okguy" <okguy74@hotmail.com> wrote:
you just renamed (by changing the terminal name)? If so, these will not change
automatically at check-and-save time as was suggested.
Say you have three variables already set:
cv - database object of cellView
oldName - old terminal name
newName - new terminal name
then:
term=dbFindTermByName(cv oldName)
term~>name=newName
foreach(fig term~>net~>figs
foreach(child fig~>children
when(child~>objType=="label" && child~>theLabel==oldName
child~>theLabel=newName
) ; when
) ; foreach
) ; foreach
will do it. This looks at all the figures associated with the net (e.g the
wires), and then looks for children of these wires (the attached labels) and
changes them.
Regards,
Andrew.
I assume you're talking about the labels attached to wires attached to the pin
you just renamed (by changing the terminal name)? If so, these will not change
automatically at check-and-save time as was suggested.
Say you have three variables already set:
cv - database object of cellView
oldName - old terminal name
newName - new terminal name
then:
term=dbFindTermByName(cv oldName)
term~>name=newName
foreach(fig term~>net~>figs
foreach(child fig~>children
when(child~>objType=="label" && child~>theLabel==oldName
child~>theLabel=newName
) ; when
) ; foreach
) ; foreach
will do it. This looks at all the figures associated with the net (e.g the
wires), and then looks for children of these wires (the attached labels) and
changes them.
Regards,
Andrew.
O
okguy
Guest
I also have this problem : either for operating point either for node
voltage.
Sometimes it works, sometimes not ...
Anyway to fix it? Is it a cdf problem?
voltage.
Sometimes it works, sometimes not ...
Anyway to fix it? Is it a cdf problem?
B
Bernd Fischer
Guest
From the docs:
aelPushSignifDigits(x_digs) => x_digs
Places (pushes) a given value onto the stack of values for the number of
significant digits the aelEngNotation function uses to create engineering
notation strnums.
I don't know what's the reason for the behaviour you see,
but might be that aelPushSignifDigits is somewhere hidden in a
Calculator function that you have used before in your
session and that causes the issue.
Bernd
ajay.balan@gmail.com wrote:
aelPushSignifDigits(x_digs) => x_digs
Places (pushes) a given value onto the stack of values for the number of
significant digits the aelEngNotation function uses to create engineering
notation strnums.
I don't know what's the reason for the behaviour you see,
but might be that aelPushSignifDigits is somewhere hidden in a
Calculator function that you have used before in your
session and that causes the issue.
Bernd
ajay.balan@gmail.com wrote:
X
xiaolong
Guest
What is the meaning of " file a SR" ?
B
boriswart
Guest
SR = service request.
xiaolong wrote:
> What is the meaning of " file a SR" ?
xiaolong wrote:
> What is the meaning of " file a SR" ?