6 bit things...

[John Walliker]

On Friday, 5 August 2022 at 16:30:03 UTC+1, Joe Gwinn wrote:

On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joeg...@comcast.net
wrote:

On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com
wrote:

Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

It would still be a byte. Univac 1108, with 36-bit words.

A byte was always a fraction of a word, but the length of a word was
whatever the computer was designed for. All sizes were tried.

I\'ve worked on digital computers with the following word sizes (in
bits): 12, 16, 24, 32, 36, 48, 64.

There were just as many floating-point formats.

Now days, it has settled down, and words are multiples of 8 bits in
size, usually a power of two. And all FP is IEEE.

The standards folk came up with \"octet\" because byte was so
ill-defined.

Half an octet was sometimes called a nybble. And so on.


I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

is DC balanced, which SFP likes.

If you use 8-bit patterns (best for component availability), but use
only the DC balanced subset, does that suffice?

We could do 8b10b, but that would need an FPGA to generate and
receive. I\'m thinking about a spare-time thing that I could design
without an FPGA or uP, all hardware. My digital people are swamped
with big projects and I need something fun to design.


Or, turn it around. Figure out how many DC-balanced patterns you
need, double it (for growth), and figure out long a word is needed.
Don\'t forget to include some control patterns.


The data is a 1-bit steam from a delta-sigma ADC. I just want to
transport it over fiber, and SFP is the easy way to do that. But SFP
is intended for telecom, ac coupled, intolerant of dc imbalance. Most
SFPs won\'t pass anything below about 1 MHz. But they are crazy fast
and have great AGC.

Is it 100 million bits per second, or symbols per second?

The ADUM7703 can be clocked up to 20 MHz, but we really don\'t need to
do that. 10M would be plenty.


What is being digitized? Voice? Data of some kind?

Some customer\'s analog voltage. Might be a strain gage load cell, for
example. We\'d have some input ranges.

All very low bandwidth stuff. Is it required to transmit absolute
values, or is just the \"AC\" part enough?

Sounds like for instance actual strain values are desired.



Is there a maximum latency and latency jitter requirement?

Neither, actually. I just want to transport the ADC output correctly.

OK.



One-bit delta samples are usually signed, so the minimum is two
symbols. If the voltage being sent is zero, then we\'ll get a steady
+,-,+,-,+, stream, which will have very strong RF spurs and thus
emissions, so need to break this up.

The ADC has a one-bit output over +-320 mV input, and averages 50%
duty cycle at 0 volts in. I just want to transport that bit over a
fiber link.

So the ADC output is a signed bit per sample.

It\'s an ADUM7703 delta-sigma a/d converter; it doesn\'t actually sample
but runs its stuff continuously. It has a clock input and a single bit
logic output. The duty cycle of the output reports the analog input:
0% duty cycle is -320 mV and 100% is +320 mV. It\'s fully isolated and
crazy precise. Once we convey that logic level to a destination, we
\"decimate\" it into a 16 or 18 or 20 bit value that reflects the input
voltage. The decimation is typically digital, a sinc3 filter, but I
might do it all analog in this case. Decimation becomes a lowpass
filter.
The fact that the ADUM7703 is clocked implies that is samples on the
clock. Otherwise, why require a clock input? Datasheet page 4 shows
the relationship.

More at end.

A zero symbol makes it three, and an idle symbol, makes it four
symbols.


Gigabit Ethernet does something like this, only grander, with two
patterns for every possible symbol to be sent, and they track current
DC balance, and choose which pattern to use that will reduce the
running DC balance.

8b10b does elaborate long-term DC balancing like that. Too much work.

SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
35% to 65%.

Yes, too much trouble. But if you use table lookup, you can get close
enough.

I don\'t want an FPGA or a uP in this box. All my coder-people are too
busy on other projects now. So, a few gates and flipflops.

OK. This too can be done, given a large ratio between optical bit
rate and ADC bitrate.

The AGC in the SFP is pretty fast, but the optical bitrate must be
much faster, or the AGC will flatten the desired signal. The SFP
datasheet should define the AGC response speed.

The combination of AGC and AC coupling makes SFPs not work well at
data rates below about 1 MHz. That varies a lot with specific parts.


So, pick a convenient optical signaling (flash) rate well above the
AGC reaction speed, so you will be able to recover the sent pattern at
the SFP output.

Here is one possible design:

Choose a ADC sample rate a fraction of the optical rate. The fraction
is determined by choosing orthogonal codes to represent +1, zero, or
-1 ADC outputs to be sent. Also need a frame-start symbol.

The orthogonal codes are chosen from the standard Gold Codes:

.<https://en.wikipedia.org/wiki/Gold_code

The codes have odd length, and are fairly close to balanced, so one
ought to be able to find some truncated Gold codes of even length
(drop last bit) that are exactly balanced. We need only four such
symbol codes, and a 16-bit code would allow the optical rate to be 16
times the code (ADC output) rate.

There must be a steady stream of ADC symbols, even if ADC output is
zero, to keep the SFP AGC stable.

Generation. Drive a 16-line demux with the optical clock. Make or
don\'t make connections from the demux to an adder, as dictated by the
symbol to be sent. The adder output is used to drive the SFP TX
input.

Reception. Lock a phase-lock loop to the optical flash rate, to
recover the optical clock.

Have one correlator per symbol type, all running in parallel. Given
the near-perfect correlation behavior of Gold codes, the correlator
output will be roughly one unit amplitude except at the pattern
center, where the peak will be about 16 units, so a threshold set at 8
units should enable perfect recovery.

The frame sync symbol is used if we are switching between a reference
voltage and the strain-gage output voltage, to mark where reference
starts. May need an ref-end symbol.

If no correlator peaks for more than a few symbol periods, complain.
The SFP will also tell you if any optical power is being received, if
I recall.

Design the receiver first, as it\'s usually the harder of the two, then
design the transmitter to make the receiver happy.

It\'s really simple; just move the 1-bit logic level output of the ADC
to the destination and recover a clock to know where the bits are.
We\'d clock the ADC at 20 or maybe 10 MHz.
If I\'m understanding the timing diagram on datasheet page 4, one can
have a long string of ones, or of zeros, depending on the input analog
voltage, which has fairly low bandwidth and so can linger at a voltage
for very long durations.

It\'s these long rafts of ones or zeros that I worry will baffle the
SFP\'s AGC function, causing data-dependent link failures.

What make and model of SFP are you looking at?


But one could use two Gold-code symbols, encoding MDATA one and MDATA
zero, and a pair of correlators at the other end of the fiber-optic
link to recover the original MDATA stream.

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?

With optical fibre losses of a few tenths of a dB/km and a likely link
margin of well over 10dB I don\'t think optical cable length will be an
issue here.
The originally proposed 6-bit encoding scheme included the data bit
followed by its complement, so that will have removed any dc baseline
fluctuation issues.
SFPs are remarkable tolerant of optical abuse. I have tried using
multimode fibre with single mode SFPs and single mode SFPs with
multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every
combination works fine despite the optical losses in some of those
configurations.

John

 

[John Larkin]

On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
wrote:

Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

It would still be a byte. Univac 1108, with 36-bit words.

A byte was always a fraction of a word, but the length of a word was
whatever the computer was designed for. All sizes were tried.

I\'ve worked on digital computers with the following word sizes (in
bits): 12, 16, 24, 32, 36, 48, 64.

There were just as many floating-point formats.

Now days, it has settled down, and words are multiples of 8 bits in
size, usually a power of two. And all FP is IEEE.

The standards folk came up with \"octet\" because byte was so
ill-defined.

Half an octet was sometimes called a nybble. And so on.


I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

is DC balanced, which SFP likes.

If you use 8-bit patterns (best for component availability), but use
only the DC balanced subset, does that suffice?

We could do 8b10b, but that would need an FPGA to generate and
receive. I\'m thinking about a spare-time thing that I could design
without an FPGA or uP, all hardware. My digital people are swamped
with big projects and I need something fun to design.


Or, turn it around. Figure out how many DC-balanced patterns you
need, double it (for growth), and figure out long a word is needed.
Don\'t forget to include some control patterns.


The data is a 1-bit steam from a delta-sigma ADC. I just want to
transport it over fiber, and SFP is the easy way to do that. But SFP
is intended for telecom, ac coupled, intolerant of dc imbalance. Most
SFPs won\'t pass anything below about 1 MHz. But they are crazy fast
and have great AGC.

Is it 100 million bits per second, or symbols per second?

The ADUM7703 can be clocked up to 20 MHz, but we really don\'t need to
do that. 10M would be plenty.


What is being digitized? Voice? Data of some kind?

Some customer\'s analog voltage. Might be a strain gage load cell, for
example. We\'d have some input ranges.

All very low bandwidth stuff. Is it required to transmit absolute
values, or is just the \"AC\" part enough?

Sounds like for instance actual strain values are desired.



Is there a maximum latency and latency jitter requirement?

Neither, actually. I just want to transport the ADC output correctly.

OK.



One-bit delta samples are usually signed, so the minimum is two
symbols. If the voltage being sent is zero, then we\'ll get a steady
+,-,+,-,+, stream, which will have very strong RF spurs and thus
emissions, so need to break this up.

The ADC has a one-bit output over +-320 mV input, and averages 50%
duty cycle at 0 volts in. I just want to transport that bit over a
fiber link.

So the ADC output is a signed bit per sample.

It\'s an ADUM7703 delta-sigma a/d converter; it doesn\'t actually sample
but runs its stuff continuously. It has a clock input and a single bit
logic output. The duty cycle of the output reports the analog input:
0% duty cycle is -320 mV and 100% is +320 mV. It\'s fully isolated and
crazy precise. Once we convey that logic level to a destination, we
\"decimate\" it into a 16 or 18 or 20 bit value that reflects the input
voltage. The decimation is typically digital, a sinc3 filter, but I
might do it all analog in this case. Decimation becomes a lowpass
filter.

The fact that the ADUM7703 is clocked implies that is samples on the
clock. Otherwise, why require a clock input? Datasheet page 4 shows
the relationship.

More at end.



A zero symbol makes it three, and an idle symbol, makes it four
symbols.


Gigabit Ethernet does something like this, only grander, with two
patterns for every possible symbol to be sent, and they track current
DC balance, and choose which pattern to use that will reduce the
running DC balance.

8b10b does elaborate long-term DC balancing like that. Too much work.

SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
35% to 65%.

Yes, too much trouble. But if you use table lookup, you can get close
enough.

I don\'t want an FPGA or a uP in this box. All my coder-people are too
busy on other projects now. So, a few gates and flipflops.

OK. This too can be done, given a large ratio between optical bit
rate and ADC bitrate.

The AGC in the SFP is pretty fast, but the optical bitrate must be
much faster, or the AGC will flatten the desired signal. The SFP
datasheet should define the AGC response speed.

The combination of AGC and AC coupling makes SFPs not work well at
data rates below about 1 MHz. That varies a lot with specific parts.


So, pick a convenient optical signaling (flash) rate well above the
AGC reaction speed, so you will be able to recover the sent pattern at
the SFP output.

Here is one possible design:

Choose a ADC sample rate a fraction of the optical rate. The fraction
is determined by choosing orthogonal codes to represent +1, zero, or
-1 ADC outputs to be sent. Also need a frame-start symbol.

The orthogonal codes are chosen from the standard Gold Codes:

.<https://en.wikipedia.org/wiki/Gold_code

The codes have odd length, and are fairly close to balanced, so one
ought to be able to find some truncated Gold codes of even length
(drop last bit) that are exactly balanced. We need only four such
symbol codes, and a 16-bit code would allow the optical rate to be 16
times the code (ADC output) rate.

There must be a steady stream of ADC symbols, even if ADC output is
zero, to keep the SFP AGC stable.

Generation. Drive a 16-line demux with the optical clock. Make or
don\'t make connections from the demux to an adder, as dictated by the
symbol to be sent. The adder output is used to drive the SFP TX
input.

Reception. Lock a phase-lock loop to the optical flash rate, to
recover the optical clock.

Have one correlator per symbol type, all running in parallel. Given
the near-perfect correlation behavior of Gold codes, the correlator
output will be roughly one unit amplitude except at the pattern
center, where the peak will be about 16 units, so a threshold set at 8
units should enable perfect recovery.

The frame sync symbol is used if we are switching between a reference
voltage and the strain-gage output voltage, to mark where reference
starts. May need an ref-end symbol.

If no correlator peaks for more than a few symbol periods, complain.
The SFP will also tell you if any optical power is being received, if
I recall.

Design the receiver first, as it\'s usually the harder of the two, then
design the transmitter to make the receiver happy.

It\'s really simple; just move the 1-bit logic level output of the ADC
to the destination and recover a clock to know where the bits are.
We\'d clock the ADC at 20 or maybe 10 MHz.

If I\'m understanding the timing diagram on datasheet page 4, one can
have a long string of ones, or of zeros, depending on the input analog
voltage, which has fairly low bandwidth and so can linger at a voltage
for very long durations.

Of course voltages near the negative rail have to get close to 0% duty
cycle, low bit density. I can avoid that by not allowing more than,
say, +-250 mV.

Delta-sigma \"noise shapes\" to push the data spectrum up, namely avoid
low frequency components in the duty cycle.

It\'s these long rafts of ones or zeros that I worry will baffle the
SFP\'s AGC function, causing data-dependent link failures.

That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

What make and model of SFP are you looking at?

I\'ve evaluated a bunch of them. I\'ll have to look that up.

But one could use two Gold-code symbols, encoding MDATA one and MDATA
zero, and a pair of correlators at the other end of the fiber-optic
link to recover the original MDATA stream.

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?

A couple of km, maybe. Singlemode can go 10s of km.

Joe Gwinn

 

[Gerhard Hoffmann]

Am 05.08.22 um 19:15 schrieb John Larkin:

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?

A couple of km, maybe. Singlemode can go 10s of km.

I think the limit is dispersion, not attenuation.

Chees, Gerhard

 

[John Larkin]

On Fri, 05 Aug 2022 19:18:19 +0300, upsidedown@downunder.com wrote:

On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
wrote:

Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

is DC balanced, which SFP likes.

Since you are transferring only a single (net) bit, why are you
worrying about the names of the actual frame bits ?

Names?

Compare to the situation with asynchronous serial communication. A
UART can usually transfer 5-8 (some up to 14) net data bits, but in
addition to this, the start bit is added, an optional parity bit and
0, 1, 1.5 or 2 stop bits are added, producing a 75 to 16 bit
transmitted frame. You really rarely have to worry about the total
frame size (except for some RS-485 converters).

I can get 10 Gbit SFPs cheap, so channel rate isn\'t an issue. But we
need DC balance and circuit simplicity. The new 4-bit thing looks
good, 1 0 d \\d per frame.

 

[Lasse Langwadt Christensen]

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:

On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010

 

[Phil Hobbs]

Gerhard Hoffmann wrote:

Am 05.08.22 um 19:15 schrieb John Larkin:

And, optical SNR matters.  If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased.  What is the maximum optical
cable length contemplated?

A couple of km, maybe. Singlemode can go 10s of km.

I think the limit is dispersion, not attenuation.

Chees, Gerhard

Step-index multimode can be as bad as 20 ns/km iirc. Good graded-index
fibre is more than a factor of 10 better (400 MHz * km is a number I\'ve
seen).

Single-mode fibre is good for a really long distance--it\'s just the
optical bandwidth that sets the dispersion.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010

Cute. But pattern 1010 1010

has an embedded 1010

which means that a simple running decoder can mis-frame
the clumps.

 

[John Larkin]

On Fri, 5 Aug 2022 19:20:08 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

Am 05.08.22 um 19:15 schrieb John Larkin:

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?

A couple of km, maybe. Singlemode can go 10s of km.

I think the limit is dispersion, not attenuation.

Chees, Gerhard

Right. Multimode has bad time dispersion.

The Guinness record for an un-repeatered fiber link is 10,358.16 km.

 

[Lasse Langwadt Christensen]

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:

On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?

which means that a simple running decoder can mis-frame
the clumps.

won\'t you have that problem with all possible ways of using 4 bit?

 

[Mike Monett]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com
jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?


which means that a simple running decoder can mis-frame the clumps.

won\'t you have that problem with all possible ways of using 4 bit?

MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero deadband
PFD in 1970, and Memorex patented it. It is shown on page 3 of my \'234
patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102
34.pdf





--
MRM

 

[a a]

On Friday, 5 August 2022 at 23:02:14 UTC+2, Mike Monett wrote:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com
jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?


which means that a simple running decoder can mis-frame the clumps.

won\'t you have that problem with all possible ways of using 4 bit?
MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero deadband
PFD in 1970, and Memorex patented it. It is shown on page 3 of my \'234
patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102
34.pdf





--
MRM

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Anonymous caller does not have storage.objects.get access to the Google Cloud Storage object.
</Details>
</Error>

 

[Joe Gwinn]

On Fri, 05 Aug 2022 10:15:20 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:

On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
wrote:

Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

It would still be a byte. Univac 1108, with 36-bit words.

A byte was always a fraction of a word, but the length of a word was
whatever the computer was designed for. All sizes were tried.

I\'ve worked on digital computers with the following word sizes (in
bits): 12, 16, 24, 32, 36, 48, 64.

There were just as many floating-point formats.

Now days, it has settled down, and words are multiples of 8 bits in
size, usually a power of two. And all FP is IEEE.

The standards folk came up with \"octet\" because byte was so
ill-defined.

Half an octet was sometimes called a nybble. And so on.


I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

is DC balanced, which SFP likes.

If you use 8-bit patterns (best for component availability), but use
only the DC balanced subset, does that suffice?

We could do 8b10b, but that would need an FPGA to generate and
receive. I\'m thinking about a spare-time thing that I could design
without an FPGA or uP, all hardware. My digital people are swamped
with big projects and I need something fun to design.


Or, turn it around. Figure out how many DC-balanced patterns you
need, double it (for growth), and figure out long a word is needed.
Don\'t forget to include some control patterns.


The data is a 1-bit steam from a delta-sigma ADC. I just want to
transport it over fiber, and SFP is the easy way to do that. But SFP
is intended for telecom, ac coupled, intolerant of dc imbalance. Most
SFPs won\'t pass anything below about 1 MHz. But they are crazy fast
and have great AGC.

Is it 100 million bits per second, or symbols per second?

The ADUM7703 can be clocked up to 20 MHz, but we really don\'t need to
do that. 10M would be plenty.


What is being digitized? Voice? Data of some kind?

Some customer\'s analog voltage. Might be a strain gage load cell, for
example. We\'d have some input ranges.

All very low bandwidth stuff. Is it required to transmit absolute
values, or is just the \"AC\" part enough?

Sounds like for instance actual strain values are desired.



Is there a maximum latency and latency jitter requirement?

Neither, actually. I just want to transport the ADC output correctly.

OK.



One-bit delta samples are usually signed, so the minimum is two
symbols. If the voltage being sent is zero, then we\'ll get a steady
+,-,+,-,+, stream, which will have very strong RF spurs and thus
emissions, so need to break this up.

The ADC has a one-bit output over +-320 mV input, and averages 50%
duty cycle at 0 volts in. I just want to transport that bit over a
fiber link.

So the ADC output is a signed bit per sample.

It\'s an ADUM7703 delta-sigma a/d converter; it doesn\'t actually sample
but runs its stuff continuously. It has a clock input and a single bit
logic output. The duty cycle of the output reports the analog input:
0% duty cycle is -320 mV and 100% is +320 mV. It\'s fully isolated and
crazy precise. Once we convey that logic level to a destination, we
\"decimate\" it into a 16 or 18 or 20 bit value that reflects the input
voltage. The decimation is typically digital, a sinc3 filter, but I
might do it all analog in this case. Decimation becomes a lowpass
filter.

The fact that the ADUM7703 is clocked implies that is samples on the
clock. Otherwise, why require a clock input? Datasheet page 4 shows
the relationship.

More at end.



A zero symbol makes it three, and an idle symbol, makes it four
symbols.


Gigabit Ethernet does something like this, only grander, with two
patterns for every possible symbol to be sent, and they track current
DC balance, and choose which pattern to use that will reduce the
running DC balance.

8b10b does elaborate long-term DC balancing like that. Too much work.

SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
35% to 65%.

Yes, too much trouble. But if you use table lookup, you can get close
enough.

I don\'t want an FPGA or a uP in this box. All my coder-people are too
busy on other projects now. So, a few gates and flipflops.

OK. This too can be done, given a large ratio between optical bit
rate and ADC bitrate.

The AGC in the SFP is pretty fast, but the optical bitrate must be
much faster, or the AGC will flatten the desired signal. The SFP
datasheet should define the AGC response speed.

The combination of AGC and AC coupling makes SFPs not work well at
data rates below about 1 MHz. That varies a lot with specific parts.


So, pick a convenient optical signaling (flash) rate well above the
AGC reaction speed, so you will be able to recover the sent pattern at
the SFP output.

Here is one possible design:

Choose a ADC sample rate a fraction of the optical rate. The fraction
is determined by choosing orthogonal codes to represent +1, zero, or
-1 ADC outputs to be sent. Also need a frame-start symbol.

The orthogonal codes are chosen from the standard Gold Codes:

.<https://en.wikipedia.org/wiki/Gold_code

The codes have odd length, and are fairly close to balanced, so one
ought to be able to find some truncated Gold codes of even length
(drop last bit) that are exactly balanced. We need only four such
symbol codes, and a 16-bit code would allow the optical rate to be 16
times the code (ADC output) rate.

There must be a steady stream of ADC symbols, even if ADC output is
zero, to keep the SFP AGC stable.

Generation. Drive a 16-line demux with the optical clock. Make or
don\'t make connections from the demux to an adder, as dictated by the
symbol to be sent. The adder output is used to drive the SFP TX
input.

Reception. Lock a phase-lock loop to the optical flash rate, to
recover the optical clock.

Have one correlator per symbol type, all running in parallel. Given
the near-perfect correlation behavior of Gold codes, the correlator
output will be roughly one unit amplitude except at the pattern
center, where the peak will be about 16 units, so a threshold set at 8
units should enable perfect recovery.

The frame sync symbol is used if we are switching between a reference
voltage and the strain-gage output voltage, to mark where reference
starts. May need an ref-end symbol.

If no correlator peaks for more than a few symbol periods, complain.
The SFP will also tell you if any optical power is being received, if
I recall.

Design the receiver first, as it\'s usually the harder of the two, then
design the transmitter to make the receiver happy.

It\'s really simple; just move the 1-bit logic level output of the ADC
to the destination and recover a clock to know where the bits are.
We\'d clock the ADC at 20 or maybe 10 MHz.

If I\'m understanding the timing diagram on datasheet page 4, one can
have a long string of ones, or of zeros, depending on the input analog
voltage, which has fairly low bandwidth and so can linger at a voltage
for very long durations.

Of course voltages near the negative rail have to get close to 0% duty
cycle, low bit density. I can avoid that by not allowing more than,
say, +-250 mV.

I\'d assume that you would prefer not to do that.

If both zero and one MDATA samples are each coded with a DC balanced
pattern, there is no need to restrict the voltage range.

Delta-sigma \"noise shapes\" to push the data spectrum up, namely avoid
low frequency components in the duty cycle.

This MDATA signal seems to be pulse-width modulated,not sigma-delta
(despite the name), sampled at the ADC clock rate. What is being
transmitted is in fact an absolute voltage value, with some
quantization noise added. See datasheet page 16.

No idea why they talk of sigma-delta. Certainly was confusing me.

Maybe the sigma-delta stuff is buried in the front half of the \"ADC\".
There was talk of an internal 16-bit register somewhere. It could be
accumulating the up/down change pulses, the current value of this
register being what is pulse-width modulated and transmitted back to
earth.

It\'s these long rafts of ones or zeros that I worry will baffle the
SFP\'s AGC function, causing data-dependent link failures.

That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

Yes. Basically, what we are discussing here is how long the symbol
pattern should be. You still need a way to decode that isn\'t
vulnerable to frame-shift errors.

For which you need long strings of either kind of symbol (zero or one)
to decode in exactly one way, not using the end of one symbol and the
start of the next to declare an ADC sample. So the pattern cannot be
too short or too simple.

Digital correlation receivers are pretty simple, basically a shift
register with outputs being summed, half being direct and half being
inverted.

When the sought-for pattern is centered in the shift register, the
summer emits a peak of amplitude N. Otherwise, the output amplitude
is roughly zero, max unity, where N is the length of the pattern (and
thus shift register) in bits. No computer needed.

What make and model of SFP are you looking at?

I\'ve evaluated a bunch of them. I\'ll have to look that up.

If they all claim the enet PHY mentioned later, the AGC time constant
ought to be about the same, most likely being specified in the
relevant enet standard, to ensure that SFP modules are
interchangeable.

But one could use two Gold-code symbols, encoding MDATA one and MDATA
zero, and a pair of correlators at the other end of the fiber-optic
link to recover the original MDATA stream.

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?

A couple of km, maybe. Singlemode can go 10s of km.

Singlemode fiber is cheap, and will certainly do the job. The
Ethernet PHY you want for this is \"1000BASE-LX\", as defined in IEEE
802.3 Clause 38. This is a common Gigabit Ethernet via optical fiber
PHY.

Going one-fifth the max reach should yield ample optical SNR, so long
ate there are few optical connectors


Joe Gwinn

 

[Joe Gwinn]

On Fri, 5 Aug 2022 09:22:21 -0700 (PDT), John Walliker
<jrwalliker@gmail.com> wrote:

On Friday, 5 August 2022 at 16:30:03 UTC+1, Joe Gwinn wrote:
[snip]

And, optical SNR matters. If the minimum SNR is high, the tolerance
for non-zero DC balance, is increased. What is the maximum optical
cable length contemplated?

With optical fibre losses of a few tenths of a dB/km and a likely link
margin of well over 10dB I don\'t think optical cable length will be an
issue here.

Yes. It turns out that the max reach is one km, and singlemode will
go five km.

The originally proposed 6-bit encoding scheme included the data bit
followed by its complement, so that will have removed any dc baseline
fluctuation issues.

It should, but the two-bit and four-bit schemes may be challenged. And
also suffer from framing errors.

SFPs are remarkable tolerant of optical abuse. I have tried using
multimode fibre with single mode SFPs and single mode SFPs with
multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every
combination works fine despite the optical losses in some of those
configurations.

At 50 meters, basically anything will work.

With signals sent by RS422 over wire, the standard observation/joke
was that one could sent this signal on a two-strand barbed wire fence
-- so long as the cows didn\'t use the fence as a back scratchier.

Joe Gwinn

 

[Jasen Betts]

On 2022-08-04, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
usenet@revmaps.no-ip.org> wrote:

On 2022-08-03, jlarkin@highlandsniptechnology.com <jlarkin@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM

Manchester is ambiguous. A string of 0s looks just like a string of
1s.

And also vise-versa but only then.

still the above looks the same as manchester( 0 1 d )

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

So now it\'s manchester( 1 d ) what does idle look like?

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

FM coding seems easier

--
Jasen.

 

[Jasen Betts]

On 2022-08-05, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

Of course voltages near the negative rail have to get close to 0% duty
cycle, low bit density. I can avoid that by not allowing more than,
say, +-250 mV.

Delta-sigma \"noise shapes\" to push the data spectrum up, namely avoid
low frequency components in the duty cycle.


It\'s these long rafts of ones or zeros that I worry will baffle the
SFP\'s AGC function, causing data-dependent link failures.

That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

Biphase-M code (FM) does that for 2 slots per data bit instead of 4

It seems like you\'re reinventing the wheel, and having rejected the
triangular wheel for the square wheel are impressed by the
improvement it gives.

--
Jasen.

 

[John Larkin]

On Fri, 5 Aug 2022 23:13:37 -0000 (UTC), Jasen Betts
<usenet@revmaps.no-ip.org> wrote:

On 2022-08-05, John Larkin <jlarkin@highland_atwork_technology.com> wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

Of course voltages near the negative rail have to get close to 0% duty
cycle, low bit density. I can avoid that by not allowing more than,
say, +-250 mV.

Delta-sigma \"noise shapes\" to push the data spectrum up, namely avoid
low frequency components in the duty cycle.


It\'s these long rafts of ones or zeros that I worry will baffle the
SFP\'s AGC function, causing data-dependent link failures.

That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

Biphase-M code (FM) does that for 2 slots per data bit instead of 4

A long string of 0s is ambiguous. Harder to decode.

It seems like you\'re reinventing the wheel, and having rejected the
triangular wheel for the square wheel are impressed by the
improvement it gives.

I didn\'t invent the 4-bit version. I wish I had.

But thank you for your polite and constructive assistance.

 

[John Larkin]

On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?

The decoder is a 3-bit shift register and a 2-input xnor gate.

 

[Phil Hobbs]

Mike Monett wrote:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com
jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?


which means that a simple running decoder can mis-frame the clumps.

won\'t you have that problem with all possible ways of using 4 bit?

MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero deadband
PFD in 1970, and Memorex patented it. It is shown on page 3 of my \'234
patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102
34.pdf

The schematics redrawn by the patent artist are fun, if not super
intelligible. Before I go trying to follow them, did the artist get
them right?

Cheers

Phil Hobbs




--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Mike Monett]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Mike Monett wrote:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com
jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?


which means that a simple running decoder can mis-frame the clumps.

won\'t you have that problem with all possible ways of using 4 bit?

MFM coding is DC balanced and easy to encode. It is hard to decode:

https://en.wikipedia.org/wiki/Modified_frequency_modulation

It requires a PLL with zero deadband. I invented the first zero
deadband PFD in 1970, and Memorex patented it. It is shown on page 3 of
my \'234 patent:

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38
102 34.pdf
The schematics redrawn by the patent artist are fun, if not super
intelligible. Before I go trying to follow them, did the artist get
them right?

Cheers

Phil Hobbs

I don\'t know. I never checked them. As you well know yourself, Patent
attorneys take the most well layed out schematics and turn them into
scrambled spaghetti. There were 5 pages of this crap and I didn\'t have time
to go through them all. I had left Memorex by that time and was working for
Diablo Corporation (now extinct), so all I did was sign the papers and take
the mandantory $1.00 to transfer ownership.

Trying to follow the schematic may be difficult. The circuit had to switch
between full phase/frequency detection to MFM decoding, as well as
synchronize the loop as quickly as possible after the address mark. This is a
short section of erased data to signify an area of all data bits (all ones)
to get the loop locked up on the correct data separator window.

The essential part of the circuit is what happens after the pair of d-flops
that form the PFD. By nature, PFD\'s cannot have deadband. Deadband occurs
when either the pullup or pulldown digital to analog conversion has a long
propagation delay so it does not respond to short pulses around zero phase
error.

The critical area is the quad pairs of 2N4209/2N5851 differential pairs
arranged so they cannot saturate.

This is what I-forget-his-name did in the MC4044. The ASC file is located in
https://tinyurl.com/2p97vht8

His input transistor for the pullup side, Q1, saturated as soon as the DATA
d-flop, U1, was clocked. Consequently, it did not come out of saturation for
a long time after both d-flops were reset. This produced the deadband. He
could easily have avoided this problem by adding a Baker clamp at the input
of Q1:

https://en.wikipedia.org/wiki/Baker_clamp

I avoided this problem by setting the current through the input differential
pair to 20ma and 10mA. When driving 50 Ohms, this produces 1V and 0.5V that
drives the output pair of differential amplifiers. I could have dropped the
pulldown emitter resistor to 510 ohms, but there were so many other issues
with trying to get foreign parts through Memorex purchasing that I was simply
swamped. It worked, time for refinement later.

Anyway, the critical thing is the input differential pair did not saturate,
and there was no deadband. I verified this with countless hours under the
scope hood. If you have ever spent time under a scope hood, you know about
the band it etches around your eyes. I wore that band for 9 months while I
was developing this circuit. The deadband problem was solved.

Of course, there are much simpler ways of coupling a pair of d-flops to a
loop filter, but I won\'t go through them now. Maybe later. The key is to make
the circuit fast enough to follow the short pulses from the d-flops around
zero phase error.





--
MRM

 

[Mike Monett]

Mike Monett <spamme@not.com> wrote:

[...]

Of course, there are much simpler ways of coupling a pair of d-flops to
a loop filter, but I won\'t go through them now. Maybe later. The key is
to make the circuit fast enough to follow the short pulses from the
d-flops around zero phase error.

I forgot - I included one method in FASTDIOD.ASC in
https://tinyurl.com/2p97vht8


--
MRM