6 bit things...

[Ricky]

On Tuesday, August 9, 2022 at 4:30:56 AM UTC-4, Jasen Betts wrote:

On 2022-08-06, Ricky <gnuarm.del...@gmail.com> wrote:
On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

How would that matter? eventually it will resolve, and until then it
is all ones anyway, you might be off by a count of one, but coming
into the signal mid stream you are already starting from a bad position,
and this hasn\'t made it any worse than it would be if you could find
the frame start immediately. So just guess, if it turns out you were
wrong there\'s only one other choice.

This is raw delta-sigma data, so all bits are least signifigant, and
if you receive, missed, extra, or corrupted single bits it prpbably
won\'t have noticeable effect.

There is nothing magical about the pattern 1 0 d \\d.

Yeah, for example FM coding gets you the same features in half as many timeslots.

On Friday, August 5, 2022 at 4:20:58 PM UTC-4, John Larkin wrote:

On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:


move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

which means that a simple running decoder can mis-frame
the clumps.

I\'m not the one defining the problem. Clearly, framing is important or Larkin would not have brought up the concern. He seems to shoot down solutions with a wide bore shotgun, the sort of shot that would bring down his own solution, if he simply looked at it through the same sights.

Either mis-alignment will or will not matter. Hard to have it both ways.

--

Rick C.

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

 

[Joe Gwinn]

On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Meaning the outputs of stages 1 and 3, for a separation of two bits?


Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
.<https://en.wikipedia.org/wiki/XNOR_gate

I have been playing with it, and I\'m not getting useful detection of
the sent MDATA bits. Perhaps I\'m doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.


I intend to lowpass filter it. I don\'t need a bit rate reduction.

So I modeled that (in Mathematica), and it does appear to work,
extrapolating to four times the pattern rate in the process, making
low-pass filtering easier.

Basically, this approach replicates the PWM waveform that MDATA is
carrying, and has nothing to do with sigma-delta coding. (The 4:1
bitrate extrapolation above is not quite the same thing as sigma-delta
noise shaping, but a similar effect.)

I also modeled 4-bit symbols, which don\'t work - no balanced 4-bit
pattern is self-orthogonal (so the correlation receiver will
automatically frame correctly), so I didn\'t look for mutually
orthogonal pattern sets.

I\'m working on 6-bit patterns, where there are many more candidates.

Such things do exist, and the question is only how large the patterns
must be. Pattern lengths that are powers of two are usually most
convenient.

Joe Gwinn

 

[John Larkin]

On Wed, 10 Aug 2022 14:19:46 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Meaning the outputs of stages 1 and 3, for a separation of two bits?


Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
.<https://en.wikipedia.org/wiki/XNOR_gate

I have been playing with it, and I\'m not getting useful detection of
the sent MDATA bits. Perhaps I\'m doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.


I intend to lowpass filter it. I don\'t need a bit rate reduction.

So I modeled that (in Mathematica), and it does appear to work,
extrapolating to four times the pattern rate in the process, making
low-pass filtering easier.

It just replicates the original 20 Mbps data at the adc output.

I\'d resync it after the xor gate to get clean complementary CMOS logic
levels and then use a differential filter and amp on the q and /q flop
outputs. 50% duty cycle is zero volts out.

Basically, this approach replicates the PWM waveform that MDATA is
carrying, and has nothing to do with sigma-delta coding. (The 4:1
bitrate extrapolation above is not quite the same thing as sigma-delta
noise shaping, but a similar effect.)

The d \\d data from the ADC is delta-sigma. The encoding and
transmission process doesn\'t care.

I also modeled 4-bit symbols, which don\'t work - no balanced 4-bit
pattern is self-orthogonal (so the correlation receiver will
automatically frame correctly), so I didn\'t look for mutually
orthogonal pattern sets.

I\'m working on 6-bit patterns, where there are many more candidates.

Such things do exist, and the question is only how large the patterns
must be. Pattern lengths that are powers of two are usually most
convenient.

Joe Gwinn
--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Joe Gwinn]

On Wed, 10 Aug 2022 13:57:11 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Wed, 10 Aug 2022 14:19:46 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Meaning the outputs of stages 1 and 3, for a separation of two bits?


Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
.<https://en.wikipedia.org/wiki/XNOR_gate

I have been playing with it, and I\'m not getting useful detection of
the sent MDATA bits. Perhaps I\'m doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.


I intend to lowpass filter it. I don\'t need a bit rate reduction.

So I modeled that (in Mathematica), and it does appear to work,
extrapolating to four times the pattern rate in the process, making
low-pass filtering easier.

It just replicates the original 20 Mbps data at the adc output.

So you\'re clocking the SFP input faster than the MDATA rate, as for
every MDAT bit there are four SFP bits, \"1 0 d /d\".

I recall some discussion of this, but I\'ve lost the thread on that in
all the back-and-forth. I may not be alone. Probably time for a
re-baseline of the discussion.

I\'d resync it after the xor gate to get clean complementary CMOS logic
levels and then use a differential filter and amp on the q and /q flop
outputs. 50% duty cycle is zero volts out.

OK.

Basically, this approach replicates the PWM waveform that MDATA is
carrying, and has nothing to do with sigma-delta coding. (The 4:1
bitrate extrapolation above is not quite the same thing as sigma-delta
noise shaping, but a similar effect.)

The d \\d data from the ADC is delta-sigma. The encoding and
transmission process doesn\'t care.

Well I see the problem now. One can describe this in either way, and
the datasheet is a bit ambiguous on the subject.

While it makes a whole lot of sense for the ADC (in the isolated side)
to be delta-sigma, the MDAT interface (spanning the gap between
isolated and grounded) can be seen as PWM or delta-sigma.

From datasheet page 1:

\"The analog input is continuously sampled by a high performance analog
modulator and converted to a ones density digital output stream with a
data rate of up to 21 MHz.\"

Note the talk of \"ones density\".


From datasheet page 16:

\"The time average single-bit data from the modulator is directly
proportional to the input signal. \"

Note the talk of averaged (versus integrated).

\"A differential signal of 0 mV ideally results in a stream of
alternating 1s and 0s at the MDAT output pin. This output is high 50%
of the time and low 50% of the time. A differential input of 250 mV
produces a stream of 1s and 0s that are high 89.06% of the time. A
differential input of -250 mV produces a stream of 1s and 0s that are
high 10.94% of the time.

A differential input of 320 mV ideally results in a stream of all 1s.
A differential input of -320 mV ideally results in a stream of all 0s.
The ADuM7703 absolute full-scale range is ±320 mV, and the specified
full-scale performance range is ±250 mV, as shown in Table 13.\"

The above describes quantized pulse duty-cycle or fixed-frame
pulse-width modulation, as also shown in Figure 26 on the same page.
This very much implies a PWM kind of waveform.


From datasheet page 17, figure 27 (and associated text) make the
input-voltage to output-average-voltage mapping more precise.


From <https://en.wikipedia.org/wiki/Delta-sigma_modulation>:

Motivation section: \"Delta-sigma modulation converts an analog
voltage signal into a pulse frequency, or pulse density, which can be
understood as pulse-density modulation (PDM).\"

In the asynchronous case, the pulse positions are more or less random.

In Figure 3, we see a sampled delta-sigma ADC output, with varying
pulse density.

The ADuM7703 may go farther, collecting all the One bits to one side
and all the Zero bits to the other in a frame of short duration, so
while it is still the bit density that varies, it now does so in the
form of PWM modulation.

It will take a scope trace or two to nail this down.


Joe Gwinn

 

[John Larkin]

On Fri, 12 Aug 2022 16:48:54 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

On Wed, 10 Aug 2022 13:57:11 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Wed, 10 Aug 2022 14:19:46 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:

On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
use...@revmaps.no-ip.org> wrote:

On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
Is a byte always 8 bits?

no, this is why internet standards use the term \"Octet\" instead

What can I call a 6-bit byte? A clump?

sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
\"Sextet\" would work also.

I want to send data over an SFP optical link, in 6-bit things.

0 1 1 0 d \\d repeated, roughly 100 Mbits/sec

looks like manchester encoded one bit PWM
Manchester is ambiguous. A string of 0s looks just like a string of
1s.

One of my guys, on his ferry ride, figured out how to add two bit
times

1 0 d \\d

to get a DC balanced form that is easy to generate and decode. It\'s
terrifyingly clever.

move the bits around and it is FSK; F and 2F

1100
1010


Cute. But pattern 1010 1010

has an embedded 1010

isn\'t that what you get with 1 0 d \\d and d = 1 ?
The decoder is a 3-bit shift register and a 2-input xnor gate.

and how does that help? you still need to use 1010

Will that even work? A correlation receiver with emit a pulse
whenever the desired pattern is in the shift register, even if it
happens to find the pattern between two correctly-framed instances of
the pattern.

A 2-input xnor is not a correlation receiver.

I guess I\'m not visualizing the specific circuit used.

Joe Gwinn

The decoder is a 3-bit shift register. Xnor the first and last bits.

Meaning the outputs of stages 1 and 3, for a separation of two bits?


Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
an xnor that spans 3 bits, and slide it along the pattern.

Any D sees a 1 in either direction. Any \\d sees a 0. Any 1 sees a d.
Any 0 sees a \\d.

XNOR will emit a One if the two inputs are the same, and Zero
otherwise. So either matched Zeros or matched Ones will yield a One.
.<https://en.wikipedia.org/wiki/XNOR_gate

I have been playing with it, and I\'m not getting useful detection of
the sent MDATA bits. Perhaps I\'m doing something wrong?

This approach does not yield only one output bit per 4-bit input
symbol, instead getting large rafts of output bits, so it seems that
we still need to find the framing somehow to achieve the 4:1 bitrate
reduction.


I intend to lowpass filter it. I don\'t need a bit rate reduction.

So I modeled that (in Mathematica), and it does appear to work,
extrapolating to four times the pattern rate in the process, making
low-pass filtering easier.

It just replicates the original 20 Mbps data at the adc output.

So you\'re clocking the SFP input faster than the MDATA rate, as for
every MDAT bit there are four SFP bits, \"1 0 d /d\".

I recall some discussion of this, but I\'ve lost the thread on that in
all the back-and-forth. I may not be alone. Probably time for a
re-baseline of the discussion.


I\'d resync it after the xor gate to get clean complementary CMOS logic
levels and then use a differential filter and amp on the q and /q flop
outputs. 50% duty cycle is zero volts out.

OK.


Basically, this approach replicates the PWM waveform that MDATA is
carrying, and has nothing to do with sigma-delta coding. (The 4:1
bitrate extrapolation above is not quite the same thing as sigma-delta
noise shaping, but a similar effect.)

The d \\d data from the ADC is delta-sigma. The encoding and
transmission process doesn\'t care.

Well I see the problem now. One can describe this in either way, and
the datasheet is a bit ambiguous on the subject.

While it makes a whole lot of sense for the ADC (in the isolated side)
to be delta-sigma, the MDAT interface (spanning the gap between
isolated and grounded) can be seen as PWM or delta-sigma.

From datasheet page 1:

\"The analog input is continuously sampled by a high performance analog
modulator and converted to a ones density digital output stream with a
data rate of up to 21 MHz.\"

Note the talk of \"ones density\".

That\'s American for \"duty cycle.\" But random.

From datasheet page 16:

\"The time average single-bit data from the modulator is directly
proportional to the input signal. \"

Note the talk of averaged (versus integrated).

We usually decimate the delta-sigma ADC data into an 18 or 20-bit
integer in an FPGA. My guys like to use a sinc3 lowpass filter, which
looks like it shouldn\'t work but it does.

But I\'m considering an analog-to-analog link, no FPGA, with data sent
over fiber SFP.

\"A differential signal of 0 mV ideally results in a stream of
alternating 1s and 0s at the MDAT output pin. This output is high 50%
of the time and low 50% of the time. A differential input of 250 mV
produces a stream of 1s and 0s that are high 89.06% of the time. A
differential input of -250 mV produces a stream of 1s and 0s that are
high 10.94% of the time.

A differential input of 320 mV ideally results in a stream of all 1s.
A differential input of -320 mV ideally results in a stream of all 0s.
The ADuM7703 absolute full-scale range is ±320 mV, and the specified
full-scale performance range is ±250 mV, as shown in Table 13.\"

It\'s a great chip. The isolation lets the input hang across, say, a
current shunt with some giant common-mode voltage.

The above describes quantized pulse duty-cycle or fixed-frame
pulse-width modulation, as also shown in Figure 26 on the same page.
This very much implies a PWM kind of waveform.


From datasheet page 17, figure 27 (and associated text) make the
input-voltage to output-average-voltage mapping more precise.


From <https://en.wikipedia.org/wiki/Delta-sigma_modulation>:

Motivation section: \"Delta-sigma modulation converts an analog
voltage signal into a pulse frequency, or pulse density, which can be
understood as pulse-density modulation (PDM).\"

In the asynchronous case, the pulse positions are more or less random.

The genius of delta-sigma is that it randomizes the duty cycle and
pushes the spectrum up. Unlike classic PWM, it\'s much easier to
process and filter.

In Figure 3, we see a sampled delta-sigma ADC output, with varying
pulse density.

The ADuM7703 may go farther, collecting all the One bits to one side
and all the Zero bits to the other in a frame of short duration, so
while it is still the bit density that varies, it now does so in the
form of PWM modulation.

It will take a scope trace or two to nail this down.


Joe Gwinn

I actually have an LT Spice model of a delta-sigma ADC, if anyone
wants to play with it.

 

[Les Cargill]

John Larkin wrote:

On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

<snip>

--
Les Cargill

 

[John Larkin]

On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com>
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.

 

[Lasse Langwadt Christensen]

lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:

On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:
John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip
How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.

you can\'t, but since it is a DSM stream you\'ll have lot of transitions unless something is wrong
so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1

Version 4
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FLAG 80 384 0
FLAG -544 -352 0
FLAG 1840 400 0
FLAG 1712 -32 0
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FLAG -192 -256 ADC_Dp
FLAG 2880 96 DATA_OUT
FLAG 560 -256 MDATA
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SYMATTR Value SINE(.5 .5 80e6)
SYMBOL bv -544 -464 R0
WINDOW 3 52 61 Left 2
SYMATTR Value V=RAND(time*1e8)
SYMATTR InstName B1
SYMBOL Digital\\\\dflop 240 -80 R0
WINDOW 3 8 12 Left 2
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SYMATTR Value td=1n
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WINDOW 123 0 0 Left 0
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SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage 1712 -128 R0
WINDOW 123 0 0 Left 0
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SYMATTR Value 1k
SYMBOL Digital\\\\xor 704 112 R0
SYMATTR InstName A1
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SYMATTR InstName A5
SYMBOL Digital\\\\and 2192 -176 R0
SYMATTR InstName A6
TEXT 1200 -504 Left 2 !.tran 1u
TEXT -400 -472 Left 2 ;ADC sim
TEXT 880 -440 Left 2 ;Transmitter
TEXT 1480 -448 Left 2 ;Reciever
TEXT 2288 -304 Left 2 ;11 = 0->1
TEXT 2288 -152 Left 2 ;00= 1->0
RECTANGLE Normal 1088 432 -64 -496 2
RECTANGLE Normal -624 -496 -144 -144 2
RECTANGLE Normal 3040 432 1440 -496 2

 

[Les Cargill]

John Larkin wrote:

On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.

You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.

--
Les Cargill

 

[Les Cargill]

Lasse Langwadt Christensen wrote:

lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:
John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip
How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.

you can\'t, but since it is a DSM stream you\'ll have lot of transitions unless something is wrong
so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1

Bits are always paired as 01 or 10, meaning 0 and 1 respectively.


<snip>

--
Les Cargill

 

[Lasse Langwadt Christensen]

søndag den 14. august 2022 kl. 01.20.17 UTC+2 skrev Les Cargill:

Lasse Langwadt Christensen wrote:
lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:
John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip
How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.

you can\'t, but since it is a DSM stream you\'ll have lot of transitions unless something is wrong
so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1

Bits are always paired as 01 or 10, meaning 0 and 1 respectively.

yes so every time there\'s a change in data you get a 00 or 11 in the stream

eg data = 00101100 -> stream = 01.01:10:01:10.10:01.01

 

[Lasse Langwadt Christensen]

søndag den 14. august 2022 kl. 01.18.39 UTC+2 skrev Les Cargill:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.

You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.

with 20MHz data rate?

 

[Jasen Betts]

On 2022-08-12, Joe Gwinn <joegwinn@comcast.net> wrote:

\"The analog input is continuously sampled by a high performance analog
modulator and converted to a ones density digital output stream with a
data rate of up to 21 MHz.\"

Note the talk of \"ones density\".

as opposed to what?

From datasheet page 16:

\"The time average single-bit data from the modulator is directly
proportional to the input signal. \"

Note the talk of averaged (versus integrated).

This is merely the difference between the destination and the route.

\"A differential signal of 0 mV ideally results in a stream of
alternating 1s and 0s at the MDAT output pin. This output is high 50%
of the time and low 50% of the time. A differential input of 250 mV
produces a stream of 1s and 0s that are high 89.06% of the time. A
differential input of -250 mV produces a stream of 1s and 0s that are
high 10.94% of the time.

Note above the 101010 pattern for 0V is characteristic of delta-sigma,
but that that doesn\'t match the picture in figure 26.

A differential input of 320 mV ideally results in a stream of all 1s.
A differential input of -320 mV ideally results in a stream of all 0s.
The ADuM7703 absolute full-scale range is ±320 mV, and the specified
full-scale performance range is ±250 mV, as shown in Table 13.\"

The above describes quantized pulse duty-cycle or fixed-frame
pulse-width modulation, as also shown in Figure 26 on the same page.
This very much implies a PWM kind of waveform.

Seems fairly ambiguous to me.

Jasen.

 

[server]

On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcargil99@gmail.com>
wrote:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.



You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.

My premise was that I\'d build both ends with no code, no c and no
VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing
error, could be done with a bit of discrete logic. A delta-sigma adc
would provide lots of opportunities to test that.

 

[Lasse Langwadt Christensen]

søndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:

On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.



You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.
My premise was that I\'d build both ends with no code, no c and no
VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing
error, could be done with a bit of discrete logic. A delta-sigma adc
would provide lots of opportunities to test that.

not need to mess with frames,
just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

I guess you didn\'t see the spice sim

 

[Les Cargill]

jlarkin@highlandsniptechnology.com wrote:

On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcargil99@gmail.com
wrote:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.



You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.

My premise was that I\'d build both ends with no code, no c and no
VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

Fair enough. I was estimating complexity really. I don\'t recall an
expected data rate being called out although \"optical\" would imply
something like 20 Mpbs.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing
error, could be done with a bit of discrete logic. A delta-sigma adc
would provide lots of opportunities to test that.

--
Les Cargill

 

[John Walliker]

On Sunday, 14 August 2022 at 20:05:39 UTC+1, Les Cargill wrote:

That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.
....
Fair enough. I was estimating complexity really. I don\'t recall an
expected data rate being called out although \"optical\" would imply
something like 20 Mpbs.

Cheap SFPs will happily run at 10Gbit/s.

John

 

[Lasse Langwadt Christensen]

søndag den 14. august 2022 kl. 15.51.33 UTC+2 skrev Lasse Langwadt Christensen:

søndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.



You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.
My premise was that I\'d build both ends with no code, no c and no
VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing
error, could be done with a bit of discrete logic. A delta-sigma adc
would provide lots of opportunities to test that.
not need to mess with frames,
just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

I guess you didn\'t see the spice sim

you could even skip all the PLL stuff, just set a FF on the falling edge after >1.5period high, clear FF on rising edge after >~1.5period low

 

[server]

On Mon, 15 Aug 2022 08:08:29 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

søndag den 14. august 2022 kl. 15.51.33 UTC+2 skrev Lasse Langwadt Christensen:
søndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.



You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.
My premise was that I\'d build both ends with no code, no c and no
VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing
error, could be done with a bit of discrete logic. A delta-sigma adc
would provide lots of opportunities to test that.
not need to mess with frames,
just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

I guess you didn\'t see the spice sim

you could even skip all the PLL stuff, just set a FF on the falling edge after >1.5period high, clear FF on rising edge after >~1.5period low

Biphase always has a transition mid-bit. So a transition detector and
a 0.75t non-retriggerable one-shot soon syncs up.

I knew that decades ago and sort of forgot.

 

[Ricky]

On Monday, August 15, 2022 at 12:08:05 PM UTC-4, jla...@highlandsniptechnology.com wrote:

On Mon, 15 Aug 2022 08:08:29 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

sųndag den 14. august 2022 kl. 15.51.33 UTC+2 skrev Lasse Langwadt Christensen:
sųndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com
wrote:

John Larkin wrote:
On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net
wrote:
snip
That\'s the reason to send 4 bits for every actual payload bit, to keep
the SFP data balanced.

You could send the bit and its 1\'s complement right after for less than
half the cost.

snip

How would the receiver distinguish between a stream of 1s and a stream
of 0s? They look alike.



You\'d need a sync pattern for start of frame, 16 zeros followed by 16
ones, say. Maybe 4 instead of 16.

then just 10,01,01,10... an agreed number of times.

Might ECC it; Hamming, others. It\'s optical so maybe a YAGNI.

Wild arse guess is 50 lines of C for the encoder and 50 more
for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
or two.

PIC16 might be big enough. Should be close to bit times
in latency.
My premise was that I\'d build both ends with no code, no c and no
VHDL. Just small-scale cmos logic chips.

And I want to ship 20 Mbps, kinda fast for 50 lines of c.

I guess that biphase, 01 and 10 with detection of 11 as a bit framing
error, could be done with a bit of discrete logic. A delta-sigma adc
would provide lots of opportunities to test that.
not need to mess with frames,
just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

I guess you didn\'t see the spice sim

you could even skip all the PLL stuff, just set a FF on the falling edge after >1.5period high, clear FF on rising edge after >~1.5period low
Biphase always has a transition mid-bit. So a transition detector and
a 0.75t non-retriggerable one-shot soon syncs up.

Only if you have non-constant data. You already rejected several suggestions based on the fact that they required non-constant data to sync up.

Sometimes I wonder if you know what you want.

--

Rick C.

---+ Get 1,000 miles of free Supercharging
---+ Tesla referral code - https://ts.la/richard11209