VHDL Language

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VHDL, Big RGB-generator - needs shortening, algorithms
Replies
3
Views
841
HT-Lab
H
N
Free evaluation of HercuLeS high-level synthesis now availab
Replies
0
Views
306
Nikolaos Kavvadias
N
A
verification strategy with no specs
Replies
4
Views
924
Rob Anderson
R
T
Multiple Clocks on single bus
Replies
6
Views
892
TheHogs88
T
P
Ask about finding maximum and second's maximum number in arr
Replies
4
Views
837
Andy
A
T
Cannot find function "TO_INTEGER" for these actuals
Replies
17
Views
1K
Alan Fitch
A
T
Distributed Ram with Initial Values (Virtex)
Replies
11
Views
1K
Andy
A
R
Chasing Bugs in the Fog
Replies
4
Views
981
Jon Elson
J
B
Digital PLL
Replies
4
Views
1K
-
?
T
How can I avoid variable in this loop (outside the process)?
Replies
5
Views
852
Paul Uiterlinden
P
T
signal ram: ram_t := (others => (others '0'));
Replies
3
Views
791
Andy
A
?
Signal xx cannot be synthesized, bad synchronous description
Replies
15
Views
1K
-
?
A
vmkr segmentation fault
Replies
1
Views
769
Paul Uiterlinden
P
E
DSP48 in synchronous process or not, what's the difference?
Replies
2
Views
793
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?
?
A few question about vhdl(clk,signal,etc..)
Replies
3
Views
767
Andy
A
?
2 counters, counting states of Bit stream
Replies
16
Views
2K
Andy
A
D
ram problem
Replies
2
Views
839
Andy
A
B
Synchronous programmable counter
Replies
1
Views
811
Nicolas Matringe
N
?
HELP! VHDL real TYPE produces infinite decimal. How to app
Replies
5
Views
979
Alan Fitch
A
V
Cascading the attributes
Replies
10
Views
1K
Andy
A
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