S
SD
Guest
Dave,
That is an interesting result, but I was actually more interested in
seeing the I/O numbers for the benchmarked designs, instead of adding
new (arbitrary?) I/O constraints that may not have been part of the
original design. If the I/O constraints were not met, then the
results become difficult to interpret.
The only other question in my mind would be whether the different cost
tables were used for the Xilinx implementation. However, if both
vendors met the I/O constraints, and different cost tables/settings
were used for Xilinx (as was done for Altera with DSE) then I agree
that the benchmarking is reasonable and there is some validity to
them.
SD
davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0404191200.408126fc@posting.google.com>...
That is an interesting result, but I was actually more interested in
seeing the I/O numbers for the benchmarked designs, instead of adding
new (arbitrary?) I/O constraints that may not have been part of the
original design. If the I/O constraints were not met, then the
results become difficult to interpret.
The only other question in my mind would be whether the different cost
tables were used for the Xilinx implementation. However, if both
vendors met the I/O constraints, and different cost tables/settings
were used for Xilinx (as was done for Altera with DSE) then I agree
that the benchmarking is reasonable and there is some validity to
them.
SD
davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0404191200.408126fc@posting.google.com>...
SD,
1. To respond to your concerns, our benchmarking team ran a second set
of experiments to compare Stratix to Virtex-II Pro in which the
circuits are given I/O constraints in addition to Fmax contraints. The
results showed a decrease in the absolute Fmax produced for both
families of between 5% to 6%, but a negligible change (less than 0.5%)
in the relative comparison. So, our results as presented in the Net
Seminar remain valid both with a without I/O constraints.
2. Design age varies greatly though in general the larger designs tend
to be newer than the smaller designs. Most of the large designs (>40K
LEs) are less than 1 year old. Most of the small & mid density designs
are 1-3 years old. To the extent that we look for data points that are
"out-lying" and fix them (as they are often representive of broader
issues), there is some tuning of our software around these designs. I
think this likely contributes to the discrepancy in results, though I
would speculate that it contributes much less than the methodology
differences.
Dave Greenfield
Altera Product Marketing
nofpgaspam@yahoo.com (SD) wrote in message news:<27eca41.0404131035.7a9a355f@posting.google.com>...
Dave,
Thanks for your response. If I may address some of these points one
last time...
1. I understand that you don't have constraints for all these designs,
but for the designs you ran the benchmarks on, wouldn't it be more
thorough to include the I/O timing for the critical path as well?
Since you already have the data, it shouldn't be much more effort.
Would it be possible to at least show an average Tsu/Tco change on the
critical paths for the benchmark designs? I'm not disputing your
claims of a 5% difference, but without that data, I'm only getting
numbers for the middle slice of the path.
2. Could you provide the approximate average age of these designs?
Also could you comment on whether you think some of the discrepancy in
the benchmarking results is due to tool/architecture tuning to these
designs? If the designs were used during Altera's tool/architecture
development, then they should (and hopefully would) favor an Altera
implementation.
3. Sounds reasonable enough
SD
