Undefined Symbol error 3312 and 1209

G

Gaurav Agarwal

Guest
Please help me out with this code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity comple2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end comple2;

architecture Behavioral of comple2 is
signal D : out STD_LOGIC_VECTOR (3 downto 0);

begin

D <= (not a);
b <= D + "0001";

end Behavioral;


i am getting this error
ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'.
ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block)
 
On Saturday, 23 August 2014 19:01:58 UTC+5:30, Gaurav Agarwal wrote:
Please help me out with this code



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

library UNISIM;

use UNISIM.VComponents.all;



entity comple2 is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : out STD_LOGIC_VECTOR (3 downto 0));

end comple2;



architecture Behavioral of comple2 is

signal D : out STD_LOGIC_VECTOR (3 downto 0);



begin



D <= (not a);

b <= D + "0001";



end Behavioral;





i am getting this error

ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'.

ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block)
Click to expand...

if i remove out keyword then its showing an error
ERROR:HDLParsers:808 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. + can not have such operands in this context.

line 43 is the operation on port b
 
On Saturday, 23 August 2014 19:01:58 UTC+5:30, Gaurav Agarwal wrote:
Please help me out with this code



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

library UNISIM;

use UNISIM.VComponents.all;



entity comple2 is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : out STD_LOGIC_VECTOR (3 downto 0));

end comple2;



architecture Behavioral of comple2 is

signal D : out STD_LOGIC_VECTOR (3 downto 0);



begin



D <= (not a);

b <= D + "0001";



end Behavioral;





i am getting this error

ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'.

ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block)
Click to expand...

lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked!
 
On 8/23/2014 9:31 AM, Gaurav Agarwal wrote:
Please help me out with this code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity comple2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end comple2;

architecture Behavioral of comple2 is
signal D : out STD_LOGIC_VECTOR (3 downto 0);

begin

D <= (not a);
b <= D + "0001";

end Behavioral;


i am getting this error
ERROR:HDLParsers:3312 - "G:/xilinx_projects/Day1/comple2.vhd" Line 42. Undefined symbol 'D'.
ERROR:HDLParsers:1209 - "G:/xilinx_projects/Day1/comple2.vhd" Line 43. D: Undefined symbol (last report in this block)
Click to expand...

Your signal declaration should not include the keyword "out".

--

Rick
 
On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote:
> Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages.

Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. Then you can perform unsigned arithmetic on SLVs (with SLV or naturals), using an OFFICIAL package, rather than the synopsys-developed non-standard packages.

Andy
 
Le 23/08/2014 20:19, Gaurav Agarwal a écrit :

> lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked!

Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages.
Learn how to use the numeric_std package instead. Declare your ports and
signal as unsigned instead of std_logic_vector, you will even be able to
write "b <= d + 1;"

Nicolas
 
Le 24/08/2014 02:27, Andy a écrit :
On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote:
Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages.

Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned. Then you can perform unsigned arithmetic on SLVs (with SLV or naturals), using an OFFICIAL package, rather than the synopsys-developed non-standard packages.
Click to expand...

Oh no no no no no no (shakes head)
Well, technically yes you could but as a fierce advocate of strong
typing, I can not support this heresy ;o)

Nicolas
 
On 8/24/2014 6:33 PM, Nicolas Matringe wrote:
Le 24/08/2014 02:27, Andy a écrit :
On Saturday, August 23, 2014 4:27:52 PM UTC-5, Nicolas Matringe wrote:
Terrible mistake. Thou shalt not use the std_logic_* arithmetic
packages.

Or just use the vhdl-2008 standard package ieee.numeric_std_unsigned.
Then you can perform unsigned arithmetic on SLVs (with SLV or
naturals), using an OFFICIAL package, rather than the
synopsys-developed non-standard packages.

Oh no no no no no no (shakes head)
Well, technically yes you could but as a fierce advocate of strong
typing, I can not support this heresy ;o)
Click to expand...

Is there some advantage to such strong typing? I think the active word
in "strong typing" is "typing". There is far too much of it in VHDL.
I'm happy with a few very clear, well defined *short* cuts.

Actually these short cuts don't have anything to do with strong typing.
The library simply defines an operator which uses the appropriate
types on its inputs and output. What's wrong with that?

--

Rick
 
On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote:
Le 23/08/2014 20:19, Gaurav Agarwal a �crit :



lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked!



Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages.

Learn how to use the numeric_std package instead. Declare your ports and

signal as unsigned instead of std_logic_vector, you will even be able to

write "b <= d + 1;"



Nicolas
Click to expand...

can you please give the exact code using the numeric_std package?
 
Le 25/08/2014 17:54, Gaurav Agarwal a ĂŠcrit :
On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote:
Le 23/08/2014 20:19, Gaurav Agarwal a �crit :
lol! i removed the keyword out and then used the package STD_LOGIC_UNSIGNED.ALL and it worked!

Terrible mistake. Thou shalt not use the std_logic_* arithmetic packages.
Learn how to use the numeric_std package instead. Declare your ports and
signal as unsigned instead of std_logic_vector, you will even be able to
write "b <= d + 1;"
can you please give the exact code using the numeric_std package?
Click to expand...

I can

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity comple2 is
Port ( a : in unsigned (3 downto 0);
b : out unsigned (3 downto 0));
end comple2;

architecture Behavioral of comple2 is
signal D : out unsigned (3 downto 0);
begin
D <= (not a);
b <= D + 1;
end Behavioral;

Just as I said, use unsigned instead of std_logic_vector.

There's no need to use the intermediate signal D, you can do it all in a
single expression, BTW.

Nicolas
 
On 8/25/2014 3:40 PM, Nicolas Matringe wrote:
Le 25/08/2014 17:54, Gaurav Agarwal a ĂŠcrit :
On Sunday, 24 August 2014 02:57:52 UTC+5:30, Nicolas Matringe wrote:
Le 23/08/2014 20:19, Gaurav Agarwal a �crit :
lol! i removed the keyword out and then used the package
STD_LOGIC_UNSIGNED.ALL and it worked!

Terrible mistake. Thou shalt not use the std_logic_* arithmetic
packages.
Learn how to use the numeric_std package instead. Declare your ports and
signal as unsigned instead of std_logic_vector, you will even be able to
write "b <= d + 1;"
can you please give the exact code using the numeric_std package?

I can

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity comple2 is
Port ( a : in unsigned (3 downto 0);
b : out unsigned (3 downto 0));
end comple2;

architecture Behavioral of comple2 is
signal D : out unsigned (3 downto 0);
begin
D <= (not a);
b <= D + 1;
end Behavioral;

Just as I said, use unsigned instead of std_logic_vector.

There's no need to use the intermediate signal D, you can do it all in a
single expression, BTW.

Nicolas
Click to expand...

You used "out" in your signal declaration for D. Was that intentional?

--

Rick
 
Le 25/08/2014 22:42, rickman a écrit :

> You used "out" in your signal declaration for D. Was that intentional?

Oops sorry no, I just copy-pasted the orignal code and replaced the
types, I forgot to fix this.

Nicolas
 
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