Timer circuit help

[John Fields]

On Tue, 23 Nov 2004 08:49:39 +0000, Terry Pinnell
<terrypinDELETE@THESEdial.pipex.com> wrote:

kensmith@green.rahul.net (Ken Smith) wrote:

Neat, _and_ 50% duty cycle, but since the earliest output from the
4060 is Q3, there will be 8 clock cycles between IN going high and OUT
going active, which isn't what the OP's timing diagram:


No, the circuit works fine. Those are all NOR gates.

When the reset first goes away, Qn is low. The output goes high right
away.

After some clock cycles, Qn goes high causing the low on the output.

After that same number of pulses, Qn goes low.




Input:
____________________________
_____| |___........

Output:
_ _ ____________________
_____| |_| |_| |___........

^ 3-4 pulses 50% duty cycle ~6 Hz


I'd hoped to breadboard your neat solution but found I had no 4060s.
And when I turned to CircuitMaker to try a simulation instead, I was
disappointed to find its model library has no 4060.

However, it does have the 4020, which is essentially an almost
identical 14-stage ripple counter, although lacking the oscillator
section of the 4060. But so far my attempts to implement your approach
with a 4020 (and a few NORs, which I assume are 4001s?) has failed.
Anyone else able to do that please?

---
Part of the 4060's oscillator circuitry is an internal inverter with
pinned out input and output which Ken used, but which isn't available
on the 4020. What you'd have to do then, to make an ~ equivalent
oscillator, would be to use the spare section of the 4001 for that
inverter, like this:


+--[C]--+--[R]--+
| | * |
| [R] |
| | |
| B--+ |
+--Y | B-+
| A--+---Y
| A-+
| |
| +---------+ |
+-O|> Q(n+2)|--+
IN>--+--A | |
| Y-----+--|R Qn|---A
+--B | +---------+ Y-->OUT
+----------------B


* I dont believe this R is needed for CMOS, and a short should work
just as well.

--
John Fields

 

[Terry Pinnell]

Fred Bloggs <nospam@nospam.com> wrote:

You don't need any NOR gates whatsoever- you take Qn+3 and stuff a one
on that RTC input of the oscillator , pin 10, through a diode and the
4060 freezes in Qn=0 state which is the turn-on polarity for the bulb.
The n runs 1-14 and then RT x CT= 1/(2.3*6Hz*2^n) by the data sheet.

Thanks - I'll try that when the 4060s I've ordered arrive. (If time
allows, I also plan to try your 555 solution, and John Fields' shift
register approach.) Meanwhile, as mentioned, I'd like to simulate with
4020. Just about to study JF's post on that.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:

I *think* I've faithfully followed your schematic, but have not so far
been able to get it simulating:
http://www.terrypin.dial.pipex.com/Images/PulserUsing4020-1.gif

Have I misinterpreted your suggested adaptation?

Eureka! Your adaptation of Ken's circuit was spot on. And I'd copied
it OK. What I'd got badly wrong was the frequency of the clock. It
should not of course have been at 6 Hz. Now that I've increased it,
the output is correct:
http://www.terrypin.dial.pipex.com/Images/PulserUsing4020-2.gif

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Ken Smith]

In article <8c47q0h24ljekieqeca28f3bs1855cf30n@4ax.com>,
John Fields <jfields@austininstruments.com> wrote:
[.. go back and read it ..]

Yes. I just wired up your 4066 version and 100k quiets things down
nicely.

I assume you mean 4060. The 4066 is an analog switch IIRC. Although I
think I could make this circuit with an analog switch, I did not in this
case.

BTW, here's what the thing looks like with the clock inhibit set at
Q(n+2) and Q(n+3):

_______________________
INPUT____| |_____________
_ _ _______________
Q(n+2)___| |_| |_| |_____________
_ _ _ _ _______
Q(n+3)___| |_| |_| |_| |_| |_____________

Very nice! I hope the OP is getting what he wanted. (perhaps not what he
asked for)

--
--
kensmith@rahul.net forging knowledge

 

[Rich Grise]

On Tue, 23 Nov 2004 20:51:05 +0000, Terry Pinnell wrote:

Eureka!

Congrats!

Rich

 

[Jonathan Kirwan]

On Tue, 23 Nov 2004 17:27:06 -0600, John Fields <jfields@austininstruments.com>
wrote:

I also ran across ICAN-6883, "Simplified Design of Astable RC
Oscillators Using the CD4060B or two CMOS Inverters" (!) which I'll
scan and post if anyone's interested.

I'd appreciate it and thanks for the offer.

Jon

 

[Terry Pinnell]

kensmith@green.rahul.net (Ken Smith) wrote:

You're just yanking my chain. Right!

3 + 2 = 6 ???????????????????

If you really did wire it that way, there would be 4 low going pulses,
unless the input signal goes low before they are completed. The *.gif
shows the timing just about right for that being the case. The input goes
low during the 3rd low going pulse.

You had me worried there for a minute!

No yanking, straight question! But I suspect it's down to
interpretation of the spec, as I've tried to show here:
http://www.terrypin.dial.pipex.com/Images/PulserFlaw2.gif

My query was because I've been assuming that the third setting does
*not* meet the spec.

Of course, it's purely academic. In practice if the clock is carefully
adjusted by trial and error, the required result is easily obtained
from this very neat circuit.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

John Fields <jfields@austininstruments.com> wrote:

I also ran across ICAN-6883, "Simplified Design of Astable RC
Oscillators Using the CD4060B or two CMOS Inverters" (!) which I'll
scan and post if anyone's interested.

Yes please.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Robo]

On Tue, 23 Nov 2004 17:27:06 -0600, John Fields
<jfields@austininstruments.com> wrote:

Thanks. I think he's long gone, so this is just for fun now.

Still here and learning Struggling a little with the ascii art

but enjoying the discussion. As soon as I get some 4060s I'll be
breadboarding it.

Thanks again.....

 

[John Fields]

--
John Fields

 

[Terry Pinnell]

kensmith@green.rahul.net (Ken Smith) wrote:

No, its down to the issue of 3+2=5. You've overlooked something obvious.
Obvious things are the easiest to overlook. My circuit says Q and
Q(n+2). You've build one with Q and Q(N+3) The circuit you've made
will attempt to pulse 4 low times. If you leave the input high long
enough, you will see 4 downward pulses. If you move the Q6 connection to
the Q5 connection, it should work correctly.

OK, understood. In fact I had tried Q3 and Q5. That gave me the
simulation I posted earlier:
http://www.terrypin.dial.pipex.com/Images/PulserUsing4020-2.gif

But a little later I'd started experimenting with Q3 and Q6, for two
reasons. First, because of Fred Bloggs' post at
news:41A357FE.80106@nospam.com introducing Q(n+3). And secondly
because I couldn't get a *4* pulse result from your circuit.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

John Fields <jfields@austininstruments.com> wrote:

---
2 chip, 3 pulse solution on abse under "Timer circuit help"

Not exactly 50% duty cycle, but I can get it there with one more chip
or maybe a different shift register and reworking the logic a little.

How close to 50% do you need?

Does the following correctly represent your hand-drawn HC175 approach
please?
http://www.terrypin.dial.pipex.com/Images/PulserJF1.gif

If so, as you see, it gives 5 pulses. Not "3 to 4" as specified. That
is, assuming we count them consistently, as per earlier simulations of
my own and Ken Smith's circuits. IOW, the high that is sustained until
IN goes low is counted as a pulse. And, of course, partial pulses, no
matter how brief, also count.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:

Looks good. As you said, no NORs.

Given CM's lack of a 4060, any chance you could adapt it for a 4020
please?

How many output pulses does it produce, 3 or 4? The OP's spec was "3
to 4". Arguably the 'ideal' solution should be quickly adaptable to
give either.

I had a stab at it myself:
http://www.terrypin.dial.pipex.com/Images/PulserFB-1.gif

But as you see I cannot get the correct output. It's obviously because
of the missing diode. But, with its anode on Q6, none of the
connections I tried for the cathode gave the required result, despite
seeming equivalent to your original.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[John Fields]

On Wed, 24 Nov 2004 15:52:30 -0600, John Fields
<jfields@austininstruments.com> wrote:

Also, I'm pretty sure you'll find that if you wire up the circuit per
my schematic and drive it from a proper source the output glitch at
the leading edge of IN will go away.

---
'Scope output on abse under "Timer circuit help"

--
John Fields

 

[Terry Pinnell]

John Fields <jfields@austininstruments.com> wrote:

On Wed, 24 Nov 2004 15:52:30 -0600, John Fields
jfields@austininstruments.com> wrote:


Also, I'm pretty sure you'll find that if you wire up the circuit per
my schematic and drive it from a proper source the output glitch at
the leading edge of IN will go away.

---
'Scope output on abse under "Timer circuit help"

Thanks, that clinches it!

Your '3-pulse' circuit is what I'm now calling a 4-pulse circuit, for
consistency with other posts, especially Ken Smith's 4060 circuit; see
news:co2o8h$n3s$2@blue.rahul.net


--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

John Fields <jfields@austininstruments.com> wrote:

No. The oscillator structure is _quite_ different, (note that the
output of yours is high for a low input, while the output of mine is
low for a low input) mine is driven from a TTL source (not a switch)
so it can't float, my logic is all HC, my NANDs aren't Schmitt
triggers, D0 on my 175 is not switched, and the power supply is
assumed to either on all the time or off.

Other than that...

No seegar this time then? <g>

If so, as you see, it gives 5 pulses. Not "3 to 4" as specified. That
is, assuming we count them consistently, as per earlier simulations of
my own and Ken Smith's circuits. IOW, the high that is sustained until
IN goes low is counted as a pulse. And, of course, partial pulses, no
matter how brief, also count.

---
I don't count the persistent high as a pulse, but it doesn't matter
since my 3 pulse output will satisfy the OP's criterion, either way.

Agreed. The OP has long since implied it's of no consequence. I'm just
curious to know which of the several circuits suggested is flexible in
that respect. IOW, as if the spec "...pulse 3 to 4 times" had actually
meant he/she wanted easy change.

Also, I'm pretty sure you'll find that if you wire up the circuit per
my schematic and drive it from a proper source the output glitch at
the leading edge of IN will go away.

Your abse post has saved me the trouble - nothing like an actual
'scope output to resolve questions like that!

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

Fred Bloggs <nospam@nospam.com> wrote:

Terry Pinnell wrote:
Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:


Looks good. As you said, no NORs.

Given CM's lack of a 4060, any chance you could adapt it for a 4020
please?

How many output pulses does it produce, 3 or 4? The OP's spec was
"3 to 4". Arguably the 'ideal' solution should be quickly adaptable
to give either.


I had a stab at it myself:
http://www.terrypin.dial.pipex.com/Images/PulserFB-1.gif

But as you see I cannot get the correct output. It's obviously
because of the missing diode. But, with its anode on Q6, none of the
connections I tried for the cathode gave the required result, despite
seeming equivalent to your original.

Your R2 is too small- the recommendation is that R2= 2 x R1-minimum, so
make it 100K-200K regardless. Also the
4060 has a NAND for your U1C and an inverter for your U1D. Your circuit
is functionally the same for simulation purposes.

You do have the correct output- your OUT waveform turns on the bulb when
it's LOW- and you have four LOW pulses followed by solid LOW as
required.

You can consider Q6 to be the overflow for the Q4/Q5 pair
which is clocked by the negative going edges of Q3. So that the the 4th
Q3 (-) edge clocks Q6 HIGH which then interrupts the astable LOW period
forcing its output HIGH, an *inactive* edge for CP which does not cause
counter
advance- freezing the whole thing up. The bulb remains ON until the
switch is opened and the next switch closure clears the counter and
starts it over etc...

OK, thanks, understood.

If we use a definition of pulse count consistent with the one I'm
using in my discussion with Ken Smith about *his* 4060+NORs circuit,
yours has 5, not 4. (Fails the spec <g>.)

Your next challenge is to reliably make this a two
wire circuit- where you apply 12V to the whole chip, clear it, and let
it run, etc. Also, it would be best to use the MSB stages of the counter
requiring largest astable frequency, and smallest Rt * Ct hopefully then
allowing you to use an NPO type timing Ct. The 4060 is missing Q11 IIRC
or something like that.

I think I'll leave that to the OP!

I think you should find this ckt boring compared to the dual 555 chopped
ramp pulse counter- which is less trouble.

I hope to try that too.

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[Terry Pinnell]

Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:

John Fields <jfields@austininstruments.com> wrote:

Part of the 4060's oscillator circuitry is an internal inverter with
pinned out input and output which Ken used, but which isn't available
on the 4020. What you'd have to do then, to make an ~ equivalent
oscillator, would be to use the spare section of the 4001 for that
inverter, like this:


+--[C]--+--[R]--+
| | * |
| [R] |
| | |
| B--+ |
+--Y | B-+
| A--+---Y
| A-+
| |
| +---------+ |
+-O|> Q(n+2)|--+
IN>--+--A | |
| Y-----+--|R Qn|---A
+--B | +---------+ Y-->OUT
+----------------B


* I dont believe this R is needed for CMOS, and a short should work
just as well.

Many thanks. I'll have a crack at that soon.

I *think* I've faithfully followed your schematic, but have not so far
been able to get it simulating:
http://www.terrypin.dial.pipex.com/Images/PulserUsing4020-1.gif

Have I misinterpreted your suggested adaptation?

--
Terry Pinnell
Hobbyist, West Sussex, UK

 

[John Fields]

On Tue, 23 Nov 2004 22:07:16 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:

In article <8c47q0h24ljekieqeca28f3bs1855cf30n@4ax.com>,
John Fields <jfields@austininstruments.com> wrote:
[.. go back and read it ..]

Yes. I just wired up your 4066 version and 100k quiets things down
nicely.

I assume you mean 4060. The 4066 is an analog switch IIRC. Although I
think I could make this circuit with an analog switch, I did not in this
case.

BTW, here's what the thing looks like with the clock inhibit set at
Q(n+2) and Q(n+3):

_______________________
INPUT____| |_____________
_ _ _______________
Q(n+2)___| |_| |_| |_____________
_ _ _ _ _______
Q(n+3)___| |_| |_| |_| |_| |_____________


Very nice! I hope the OP is getting what he wanted. (perhaps not what he
asked for)

---
Thanks. I think he's long gone, so this is just for fun now.

BTW, I was little concerned about what the deal was with the
"substrate diodes", so I looked it up in my 1984 RCA CMOS IC Databook,
and ICAN-6230 shows an astable with no current limiting resistor, and
explains that the _protection diodes_ clamp the output of the cap to
one diode drop above and below the supply rails, so there doesn't
appear to be any problem with the latchup due to the parasitic
structure at the current levels one would expect by dumping the size
of caps being used in this application into the rails. However, the
use of the resistor _does_ reduce the variation in pulse width due to
changes in Vdd, so it's probably a good thing anyway since it turns
out to be one of those serendipetous "twofers" you get every now and
then.

I also ran across ICAN-6883, "Simplified Design of Astable RC
Oscillators Using the CD4060B or two CMOS Inverters" (!) which I'll
scan and post if anyone's interested.

--
John Fields

 

[Terry Pinnell]

Fred Bloggs <nospam@nospam.com> wrote:

Fred Bloggs wrote:

well- not quite:
View in a fixed-width font such as Courier.

.
.
. +--------+-------------+-------------+--------+
. | | | | |
. | | | | |
. | | +-------------------------------> OUT
. | | | | | |
. | | | | | |
. | | | | +-----------------------+
. | | | | | | | |
. | | | \ | | | |
. | +----------+ | 2R/10 | | +----------+ |
. | | VDD | | \ | | | VDD | |
. | | | | / | | | | |
. | | | | | | | | | |
. IN>--+--|RST OUT|----+------|>|-----+ +--|RST OUT| |
. | | | | | | | | | |
. | | LMC555 | \ +---+ | \ | LMC555 | |
. | | | R | | | 1.5R | | |
. | | | \ - | | \ | DIS|---+
. | | | / v | | / | |
. | | | | - | | | | |
. | | THR|----+---+-------+ +-----|THR |
. +--+ | | | | | | |
. | | | TRG|----+ +----------+-----|TRG |
. \ | | | | | | | | |
. R/10 | | | | | | | | |
. \ | | GND | === | \ === | GND |
. / | +----------+ |C | R/10 |C +----------+
. | | | | | \ | |
. | +-|<|----|---------|---+ / | |
. | | | | | |
. GND>-+-----------+---------+-------+------+-----------+
.
.
.
.
. 1.4 x RC= 1/6 => R=120K C=1uF
.
. Then R/10=12K and 2R/10=24K and 1.5R=180K
.
. All diodes 1N914A
.
.
Are you sure about that schematic? Is this the 'dual 555 chopped ramp

pulse counter' circuit you describe in your more recent post
news:41A343E4.1070203@nospam.com ? In that you say "...the first 555
is a standard 6Hz astable...", but that LH 555 above doesn't look like
a standard to me. For example, where is the upper resistor, from
Discharge (pin 7) to Vcc? But even if I add that, so far I've been
unable to get it simulating.

--
Terry Pinnell
Hobbyist, West Sussex, UK