Plotting frequency with time...

[Andrew Beckett]

The tool is AMS Designer.

There are a number of previous threads on this - you might want to check
on google to get more information, or you could (if all else fails) read the
manual.

Andrew.

On 23 Aug 2004 19:41:13 -0700, manivannanbhoopathy@yahoo.com (Manivannan) wrote:

Hai ,

I am new to this group and to Cadence,

My question is: is there a way to run vhdl-ams code in Cadence?

I have run vhdl and tried verilog-ams on Cadence.

For now i am using a student version of System Vision provided by
Mentor Graphics, but since my University has a licensed version of
Cadence, i was just wondering if i can port my codes to Cadence.

I will be happy if somebody could suggest me a way if one exists.

Thanks
Manivannan

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Bernd Fischer]

Eric,

We are also not happy with the analog waveform viewers provided by
Cadence.
All the hope over years was put into the new Wavescan which should be
an improvement or at least an adequate replacement for AWD,
but it seems to be not the case.

Also an other issue here is that Cadence does only supports
their proprietary waveform format PSF, which does not allow you
to hook in third party waveform viewers which are more suitable.

A common waveform format in the industry is the
FSDB (Fast Signal Database) format, supported by
many analog waveform viewers e.g. Novas nWave,
Sandwork's WaveView Analyzer and Synopsys Cosmos Scope.
FSDB is original form Novas, but I think it is open now.
FSDB requires less diskspace for the same wave form as PSF
therefore the wave form viewers can open a big file much faster
than AWD on PSF.

There is a PCR at Cadence that the Affirma Analog Environment
should support the FSDB format #650290, but I think there is
no action on it.

Just for completion a funny thing, UltraSim does or at least
did support FSDB.

Regards Bernd

Erik Wanta wrote:

Wavescan is taking 100s of MB of memory and running dog slow and
spawning several java processes. I have disabled it for not and we
are back to awd.

envSetVal("asimenv.startup" "cds_ade_wftool" 'string "awd")
---
Erik

 

[Kholdoun TORKI]

The "errFile" contains a section where are listed the topcells.
This section comes just after the "scanning" and "translating" sections.

.......
Saving all cells ...


Top Cells in File

--------------------------------------------------------------------------
top_cell layout


List Hierarchy (#cellInst,#arrayInst)

--------------------------------------------------------------------------
top_cell layout
..top_core layout(1)
...block1 layout(1)
....my_block1 layout(2)
....my_block2 layout(1)
....my_block3 layout(16)
etc ....


Regards,
=================
Kholdoun TORKI
http://cmp.imag.fr
==================


Spaller wrote:

This is true only in the case where the gdsII file is created as a streamOut
of a given top cell, and that particular file was created in top-down order.

The later versions of pipo stream out in bottom-up order, so the last cell
would be the "top cell".

The "top cell" is in quotes since an entire library could have been streamed
out, and so there could be multiple top cells in the gdsII file.

In that case, the top cells would be those which are not referenced by any
other cell, but that is an entirely different thing that pipo will not tell
you.

spaller

--

...


"Ronald" <rkdocc@yahoo.com> wrote in message
news:f96c3977.0407230849.3cca9ab7@posting.google.com...

Some of the gds reader tool defined before are good.

In Cadence flow, you could use pipo to get the top cell name.
This is a dummy way but as effective to get the data.

Make a script which
1. build a pipo streamin file, example file /tmp/tmp.pipo
streamInKeys = '(nil
runDir "/tmp"
errFile "/tmp/PIPO.debug.100967565"
inFile "/home/ronald/mycellname/all.gds"
dataDump "/tmp/stout.ronald.100967565"
scale 0.001
units "micron"
caseSensitivity "preserve")
2. run "pipo strmin /tmp/tmp.pipo "
3. Parse /tmp/PIPO.debug.100967565 until you find the first line
with "1. scanning cellview"... This line indicates
the top cell name and its cell view.
Example:
1. scanning cellview (libcell_ronald layout)
You know that your top cell is libcell_ronald

 

[Rajeswaran M]

I am getting the following error when I try to netlist using VHDL tool
box,

vhdlNet: *E,349: Unable to netlist VHDL file
/user/test/cds446/bhas/TOP_CELL/entity/vhdl.vhd because it failed VHDL
compilation.
Please clean up the syntax errors before trying again.
vhdlNet: *E,346: Entity creation from pinList file 'TOP_CELL' is aborted
due to previous errors.

The error is coming to even for a simple block. Do I miss any setups?

 

[Andrew Beckett]

Is this for VHDL-AMS? (since you replied to that thread). VHDL-AMS views cannot
be used in VHDL toolbox - that's just for pure VHDL (no AMS).

Andrew.

On Wed, 25 Aug 2004 14:39:24 +0530, Rajeswaran M <m_rajeswaran@yahoo.com> wrote:

I am getting the following error when I try to netlist using VHDL tool
box,

vhdlNet: *E,349: Unable to netlist VHDL file
/user/test/cds446/bhas/TOP_CELL/entity/vhdl.vhd because it failed VHDL
compilation.
Please clean up the syntax errors before trying again.
vhdlNet: *E,346: Entity creation from pinList file 'TOP_CELL' is aborted
due to previous errors.

The error is coming to even for a simple block. Do I miss any setups?

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[A. B.]

Rick wrote:

How do you load the DFII keyboard into CCAR?

Thanks

Rick
I recall vaguely any way to do that directly. But you

can try "-virtuoso" as an option to inherit your layout sc.
HTH

 

[Rajeswaran M]

sorry for the post in wrong thread.

Its just pure VHDL flow. customer support, had provided solution for the
issue. I was missing CDS_VHDL environment.

Thanks!!

Andrew Beckett wrote:

Is this for VHDL-AMS? (since you replied to that thread). VHDL-AMS views cannot
be used in VHDL toolbox - that's just for pure VHDL (no AMS).

Andrew.

On Wed, 25 Aug 2004 14:39:24 +0530, Rajeswaran M <m_rajeswaran@yahoo.com> wrote:


I am getting the following error when I try to netlist using VHDL tool
box,

vhdlNet: *E,349: Unable to netlist VHDL file
/user/test/cds446/bhas/TOP_CELL/entity/vhdl.vhd because it failed VHDL
compilation.
Please clean up the syntax errors before trying again.
vhdlNet: *E,346: Entity creation from pinList file 'TOP_CELL' is aborted
due to previous errors.

The error is coming to even for a simple block. Do I miss any setups?


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

Hi Nikolaos,

Consider using a combo box instead (hiCreateComboField). Here's an example I put
together some time ago. You can make the combo fields non-editable which means
you can't type in a value, but just get the choices. The width of a combo field
is controlled by the field with in the 2D form.

Andrew.

/* abTryComboFields.il

Author A.D.Beckett
Group Custom IC (UK), Cadence Design Systems Ltd.
Language SKILL
Date Feb 18, 2002
Modified
By

***************************************************

*/

(defun abTryComboFields ()
(let (f1 f2)
(setq f1
(hiCreateComboField
?name 'f1
?items '("short" "very long" "extremely long and lengthy")
?editable nil
?value "very long"
?prompt "f1"
))
(setq f2
(hiCreateComboField
?name 'f2
?items '("a" "stuff" "c")
?editable nil
?value "c"
?prompt "f2"
))
(hiCreateAppForm
?name 'abTryComboForm
?fields (list
(list f1 0:0 300:30 100)
(list f2 0:30 300:30 100)
)
)
(hiDisplayForm abTryComboForm)
))


On 31 Aug 2004 01:57:09 -0700, redhavoc@yahoo.co.uk (Nikolaos Kasparidis) wrote:

Hello,
I am using Custom IC design 5.0.33 and 5.10.41 and have a small
problem in using hiCreateCyclicField. My problem is that I cannot
control its size but only its position when I define its 2D
attributes. Actual graphic tends to get long enough to hold the
largest object in the list, and so the GUI gets messy (the cyclic
field overlaps labels when very large names are used, or very large
gaps exist, when small names are used). I need a fixed size, which I
cannot get. Let me show a part of the code, where you might detect a
problem

Cyclic = hiCreateCyclicField(
?name 'Cyclic
?choices Elements
?prompt " ")
FormList = cons(list(Cyclic 100:20 160:30 1) FormList)

The variable FormList holds all the objects to be displayed. The sizes
of buttons and entry-fields can be controlled accuretly using the
above format. I also have the same problem with labels, but they are
more predictable so this is no real problem. Any help would be
appreciated.
Thank you
Nikolaos Kasparidis

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Pete nospam Zakel]

In article <4e44ab2a.0408310057.65f2cf0d@posting.google.com> redhavoc@yahoo.co.uk (Nikolaos Kasparidis) writes:

Hello,
I am using Custom IC design 5.0.33 and 5.10.41 and have a small
problem in using hiCreateCyclicField. My problem is that I cannot
control its size but only its position when I define its 2D
attributes. Actual graphic tends to get long enough to hold the
largest object in the list, and so the GUI gets messy

If you want to be able to control the width, a combo field may be the way to
go. If you make it non-editable (?editable nil) it essentially works like a
cyclic.

With cyclic fields you have to truncate the choices strings if you want to
limit the width.

-Pete Zakel
(phz@seeheader.nospam)

"The first rule of intelligent tinkering is to save all the parts."

-Paul Erlich

 

[Diva Physical Verificatio]

You have to have both the layout and schematic stop netlisting at the
same level of detail. The detail level of the layout is controlled by
how you extract. Flat gets you transistors and such. Macro gets you
logic blocks (macro cells). When you extract with macro cells, you also
have to have the schematic netlisting treat the equivalent symbols as
leaf nodes of the netlist. Usually you use macro cell mode because there
are no schematics to go with the low level symbols, so the level of
detail is not at the transistors.

I would say that your schematics expand all the way down to transistors,
which causes LVS to compare transistors to macro cells.

On 1 Sep 2004 21:08:58 -0700, tnk11@yahoo.com (tnk) wrote:

Hi all,
I used silicon ensemble to do layout and streamed to the layout
editor. When I did flat lvs, there is no error or warning. But when I
did macro lvs, some of the macro cells are not matched with schematic.
May I know why? I've already assigned ivCellType to macro to all the
normal cell and graphic to Filler cell. By the way, I am doing full
custom, so I am not using standard cell library. So the layout cell
view is not abstract_mlvs, but layout. Is it the root of problem...
the rule is diva lvs rule. Thanks in advance...

tnk

 

[Andrew Beckett]

Wiggles? What do you mean by that? I'm assume you mean that it moves about the
screen somehow -in which case I've not seen it.

What platform, window manager etc are you using - I suspect that could be
relevant.

Andrew.

On 1 Sep 2004 12:51:23 -0700, erikwanta@starband.net (Erik Wanta) wrote:

Has anyone noticed that in IC5141 the layout window wiggles when descending?
---
Erik

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Bernd Fischer]

Erik Wanta wrote:

Jay:
Are you running Assura 312 usr1?

Dear Andrew, dear Erik,

Is there something to say about 3.12 USR1,
I was to install it very soon?

Bernd

 

[Andrew Beckett]

Hi Jan,

By locking, do you mean Cadence locking (i.e. .cdslck files)? If so,
cdsMsgServer doesn't do that at all - so I'd be really surprised if cdsMsgServer
was the cause here. In fact I wouldn't think it was doing any sort of locking
(I'm pretty sure it doesn't).

So yes, it may (or rather will) still be running, but I don't think it can have
been the culprit for the symptoms you're describing.

Best Regards,

Andrew.

On 2 Sep 2004 08:02:09 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Andrew,

The "filelocking" problem occured in our make-flow. At a certain part
in this flow we (automatically) start cadence in a temporary area in
"no gui" mode, for example to extract the latest gds2 from a block if
the makefile decided that already existing one is outdated compared to
the cadence source). After this cadence job has finished the make
process continues which also implies removing the temporary cadence
workarea. This however fails because the cdsMsgServer is still running
(and app. locking some database files in it, even though cadence has
already finished).

This was the reason for me asking the original question..... hope this
explains it a bit more.

Rgds,

Jan.

Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<qn7ji0hbs41av5m2h9uq8gpiq8o0qrlvmp@4ax.com>...
Hi Jan,

Apologies again for the lateness of my original reply - I got a bit backlogged
in processing things (they day job got in the way ;-> )

One situation I've seen where daemons started by DFII causign trouble
occasionally is with LSF. From my understanding LSF doesn't see a job as
finished if it still has child processes running (i.e. processes in the same
process group). Not sure if that's the case here, but I know in the past some
customers have had to do various things with some daemons (like explicitly
starting them on a machine in a compute farm) to get around this.

There may be ways around it in LSF too - but I'm not really that familiar with
LSF.

Andrew.

On 20 Aug 2004 13:03:23 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

daytripper <day_trippr@REMOVEyahoo.com> wrote in message news:<emiai01vgfgfpc883468jir1f0ijlfd8fa@4ax.com>...
On Thu, 19 Aug 2004 05:58:54 +0100, Andrew Beckett
andrewb@DELETETHISBITcadence.com> wrote:
On 14 Jul 2004 01:24:32 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Hello,

Does anybody know what the function is of "cdsMsgServer" daemon? I've
been searching in source link but couldn't find any usefull
information on this (certainly not "446" related). I ask because we
use cadence in a non-gui mode in our makefile driven designflow in
which this cdsMsgServer daemon is bothering us (it keeps files open).
I know it will automatically exit after a certain period but I would
like to be able to end the application by hand (in a gracefull manner
that is :&gt)

[snipped]
Why do you want them to end? What files would it keep open (I don't think
they open any files)?

I think I know what the OP is referring to, and I see the same behavior: if I
have a project open, then close the project and try to delete or rename
certain project files and/or folders, the OS bitches that the files cannot be
manipulated because some process still has them open.

I see this particularly when switching back and forth between major Cadence
versions and related projects. Killing the nameserver and messageserver
processes allows switching versions or manipulating these same files without
any other headaches...

/daytripper

Sorry for this late reply. I wasn't aware there finally was some
response on this question. Unfortunately I can't recall what the exact
reason was for this posting (sorry Andrew can't give you a
name/example) but it indeed was a locking issue after exiting your
cadence environment. The problem surfaced in our attempt to automate
our synchronicity based makefile flow in which we directly have to
access files in the cadence design database.
Andrew, I have to consult my collegue again (he ran into this problem)
for the details (in the meantime he already found a workaround for
it).


Rgds,

Jan.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

It's probably a matter of arranging a switch/stop list for Diva LVS netlisting
so that it stops at the gate level.

Take a look at the example .simrc file in <instdir>/tools/dfII/cdsuser
and look for lvsSchematicStopList - you can set these variables in your
own .simrc file to override the default. Of course, there would need to be
some sort of view at the level you want to stop at (and this view must
be in both the switch (lvsSchematicViewList) and the stop list
(lvsSchematicStopList) for it to stop there. Also, the lvsSchematicViewList
(like other view switch lists in DFII netlisting) is searched in order from
left to right, descending into the first view it finds in that list for each
cell.

Regards,

Andrew.

On 2 Sep 2004 05:04:50 -0700, tnk11@yahoo.com (tnk) wrote:

actually I imported the schematic from verilog file and I have every
symbols view. What I want is hierarchical hspice file of layout. Is
there any way to stop the schematics expanding all the way down to
transistors level? I thought by setting macro LVS will do the trick,
but pratically it is not...

tnk


Diva Physical Verification <diva@cadence.com> wrote in message news:<qhbdj0lvqgvv9448pphmjg0dgmkfblfdk5@4ax.com>...
You have to have both the layout and schematic stop netlisting at the
same level of detail. The detail level of the layout is controlled by
how you extract. Flat gets you transistors and such. Macro gets you
logic blocks (macro cells). When you extract with macro cells, you also
have to have the schematic netlisting treat the equivalent symbols as
leaf nodes of the netlist. Usually you use macro cell mode because there
are no schematics to go with the low level symbols, so the level of
detail is not at the transistors.

I would say that your schematics expand all the way down to transistors,
which causes LVS to compare transistors to macro cells.

On 1 Sep 2004 21:08:58 -0700, tnk11@yahoo.com (tnk) wrote:

Hi all,
I used silicon ensemble to do layout and streamed to the layout
editor. When I did flat lvs, there is no error or warning. But when I
did macro lvs, some of the macro cells are not matched with schematic.
May I know why? I've already assigned ivCellType to macro to all the
normal cell and graphic to Filler cell. By the way, I am doing full
custom, so I am not using standard cell library. So the layout cell
view is not abstract_mlvs, but layout. Is it the root of problem...
the rule is diva lvs rule. Thanks in advance...

tnk

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

leSetEnv is not being discontinued as far as I know. It's still used quite
extensively in the code.

It should keep the env vars in sync with the envSetVal() settings anyway, so it
shouldn't really make any difference.

Where did that Cadence recommendation come from? Is that in the docs somewhere,
or was it something an AE told you?

(I'll do some experimentation with this orientation issue when I can get in
front of a workstation, or boot my laptop up in Linux).

Regards,

Andrew.

On 2 Sep 2004 08:18:21 -0700, erikwanta@starband.net (Erik Wanta) wrote:

Looks like leSetEnv is being discontinued. The following didn't seem
to work however:
hiSetBindKey("Layout" "<Key>5" "envSetVal(\"layout\" \"orientation\"
'cyclic \"MX\") leHiMove()")

Any ideas why envSetVal("layout" "orientation" 'cyclic "MX") isn't
working?

Note: There are a number of environment variables that are no longer
compatible with leSetEnv and leGetEnv. The setting methods for the
environment variables are noted in this Appendix under the heading
Setting Method, which is included with the description of each
environment variable. Cadence recommends that you use only envSetVal
and envGetVal to determine the setting of, set, or reset environment
variables.
---
Erik

erikwanta@starband.net (Erik Wanta) wrote in message news:<84018314.0409020211.e5e86d9@posting.google.com>...
The following works in IC5033 but not in IC5141:
hiSetBindKey("Layout" "<Key>5" "leSetEnv(\"orientation\" \"MX\")
leHiMove()")

In IC5141 it just does the leHiMove(). Any ideas why it is not
changing the orientation in IC5141?
---
Erik

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

Bernd,

I don't understand what you're asking here.

Andrew.

On Thu, 02 Sep 2004 13:38:22 +0200, Bernd Fischer
<""bernd.fischer\"@xignal-A%&HY%$v#&G=.de> wrote:

Erik Wanta wrote:
Jay:
Are you running Assura 312 usr1?

Dear Andrew, dear Erik,

Is there something to say about 3.12 USR1,
I was to install it very soon?

Bernd

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Diva Physical Verificatio]

Just off hand, I'd say you have not tied your substrate and wells to
power properly.

On 2 Sep 2004 22:38:47 -0700, mail9900@yahoo.com (Jay Smith) wrote:

Greetings,
I did a couple of Assura LVS checks lately. All of my layouts match
the schematics. However, among them, I got some "error messages" from
within the ELW. Seems these errors won't affect RCX run, but what
exactly do these messages (from the ELW) mean?
------------------------------------------------
nxwell_StampErrorMult
nxwell_StampErrorConnect
psub_term_StampErrorMult
psub_term_StampErrorConnect
psub_StampErrorMult
psub_StampErrorConnect
------------------------------------------------
Thanks a lot for your inputs!
Jay

 

[Bernd Fischer]

You have more than one net connected to one layer area 'nxwell',
means more than one net connected to the same NWell, I guess.
And the same for 'psub' which should be your p+ substrate.

Assura does not flag shorts over high resistive areas like wells
or substrate layers as short in the lvs report. Most of the time
the connection to these kind of layers are defined in your rules
with a geomStamp command, which then outputs these kind of error messages.

Look in your LVS run directory for a file <runName>.err there you
will find more details and coordinates for this errors.

Bernd

Jay Smith wrote:

Greetings,
I did a couple of Assura LVS checks lately. All of my layouts match
the schematics. However, among them, I got some "error messages" from
within the ELW. Seems these errors won't affect RCX run, but what
exactly do these messages (from the ELW) mean?
------------------------------------------------
nxwell_StampErrorMult
nxwell_StampErrorConnect
psub_term_StampErrorMult
psub_term_StampErrorConnect
psub_StampErrorMult
psub_StampErrorConnect
------------------------------------------------
Thanks a lot for your inputs!
Jay

 

[Andrew Beckett]

Jan,

I did some checks on a running session, using fuser, and found that the only
filesystems it seemed to be referring to (cdsMsgServer) were /tmp (which is its
working directory) and the installation of Cadence (because it has the
executable memory mapped).

Also, as soon as I exit DFII, cdsMsgServer ends (I forgot, cdsMsgServer is
one-per-session; cdsNameServer is one-per-host).

So I'm not sure what the problem was...

Regards,

Andrew.

On 3 Sep 2004 08:49:02 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Andrew,

No there was no cadence locking involved in this case. As said, after
finishing the cadence job the make flow wants to remove the temporary
workspace (using unix "rm") and at this point it fails because files
are locked by a process on OS level. We found out that it appeared to
be cdsMsgServer by using the solaris8 'fuser' command

As said, it was one of my collegues who encountered this problem back
then and in the meantime he already has a workaround but it made us
wonder what the functionality of this daemon was and whether we could
control its behaviour.

Rgds,

Jan.
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<a2mfj0hl7g4bl0esjoi43tbj6k5mi2nbgj@4ax.com>...
Hi Jan,

By locking, do you mean Cadence locking (i.e. .cdslck files)? If so,
cdsMsgServer doesn't do that at all - so I'd be really surprised if cdsMsgServer
was the cause here. In fact I wouldn't think it was doing any sort of locking
(I'm pretty sure it doesn't).

So yes, it may (or rather will) still be running, but I don't think it can have
been the culprit for the symptoms you're describing.

Best Regards,

Andrew.

On 2 Sep 2004 08:02:09 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Andrew,

The "filelocking" problem occured in our make-flow. At a certain part
in this flow we (automatically) start cadence in a temporary area in
"no gui" mode, for example to extract the latest gds2 from a block if
the makefile decided that already existing one is outdated compared to
the cadence source). After this cadence job has finished the make
process continues which also implies removing the temporary cadence
workarea. This however fails because the cdsMsgServer is still running
(and app. locking some database files in it, even though cadence has
already finished).

This was the reason for me asking the original question..... hope this
explains it a bit more.

Rgds,

Jan.

Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<qn7ji0hbs41av5m2h9uq8gpiq8o0qrlvmp@4ax.com>...
Hi Jan,

Apologies again for the lateness of my original reply - I got a bit backlogged
in processing things (they day job got in the way ;-> )

One situation I've seen where daemons started by DFII causign trouble
occasionally is with LSF. From my understanding LSF doesn't see a job as
finished if it still has child processes running (i.e. processes in the same
process group). Not sure if that's the case here, but I know in the past some
customers have had to do various things with some daemons (like explicitly
starting them on a machine in a compute farm) to get around this.

There may be ways around it in LSF too - but I'm not really that familiar with
LSF.

Andrew.

On 20 Aug 2004 13:03:23 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

daytripper <day_trippr@REMOVEyahoo.com> wrote in message news:<emiai01vgfgfpc883468jir1f0ijlfd8fa@4ax.com>...
On Thu, 19 Aug 2004 05:58:54 +0100, Andrew Beckett
andrewb@DELETETHISBITcadence.com> wrote:
On 14 Jul 2004 01:24:32 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Hello,

Does anybody know what the function is of "cdsMsgServer" daemon? I've
been searching in source link but couldn't find any usefull
information on this (certainly not "446" related). I ask because we
use cadence in a non-gui mode in our makefile driven designflow in
which this cdsMsgServer daemon is bothering us (it keeps files open).
I know it will automatically exit after a certain period but I would
like to be able to end the application by hand (in a gracefull manner
that is :&gt)

[snipped]
Why do you want them to end? What files would it keep open (I don't think
they open any files)?

I think I know what the OP is referring to, and I see the same behavior: if I
have a project open, then close the project and try to delete or rename
certain project files and/or folders, the OS bitches that the files cannot be
manipulated because some process still has them open.

I see this particularly when switching back and forth between major Cadence
versions and related projects. Killing the nameserver and messageserver
processes allows switching versions or manipulating these same files without
any other headaches...

/daytripper

Sorry for this late reply. I wasn't aware there finally was some
response on this question. Unfortunately I can't recall what the exact
reason was for this posting (sorry Andrew can't give you a
name/example) but it indeed was a locking issue after exiting your
cadence environment. The problem surfaced in our attempt to automate
our synchronicity based makefile flow in which we directly have to
access files in the cadence design database.
Andrew, I have to consult my collegue again (he ran into this problem)
for the details (in the meantime he already found a workaround for
it).


Rgds,

Jan.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

Hi Erik,

I did some experiments, and found that the behaviour changed in IC5033 USR2 and
IC5141. It now always resets to R0 within the move function.

It's nothing to do with differences between leSetEnv and envSetVal. In fact,
there should be no usage differences between using these two functions (the
environments should always stay in sync; both exist for historical reasons -
primarily that leSetEnv existed before the common environment capability that
was added many releases back).

Anyway, a bit of research showed that the behaviour changed as a result of

PCR: 658273
Title: Set environment var orientation to R0 in first creation.

This was considered a bug by the customer in that case (with good reason - it
was rather inconsistent in its behaviour - setting the environment variable only
affected the first command, and was reset for subsequent commands). It was
changed to always reset each time - the point is that this environment variable
is used as an action rather than a state, and is used to communicate internally
between different parts of the tool.

However, it seems that your usage wasn't taken into account - effectively you
were taking advantage of this "bug" (not perceived as a bug by you).

So the following PCR was filed (for another customer originally, but also linked
to from an SR from one of your colleagues):

PCR: 726455
Title: leHiMove/leSetEnv function

This is fixed in IC5033 USR3, and I believe IC5141 USR1. The fix is to have
another env setting:

layout resetOrientation boolean t

(the default is above) - you can set it to nil if you don't want it to reset the
orientation in the move command, but pick up the orientation env var
directly.

Regards,

Andrew.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd