Plotting frequency with time...

[fogh]

Thethys wrote:

Hello, all!

I'm trying to compare Gilbert cell mixers topologies, as in the title.
I'm not sure there's a "best" one, but I'd like to compare them in
term of feedthrough, isolation, gain, noise or others...
If you have any advices, knowledges about this domain, in integrated
technology, or webpages, it would be very kind if you could share it!
Thanks in advance

Steve
No no, Thethys,

you can not mix cells from Dilbert, because he is not a real person. He is a cartoon guy, Hmkay ? So you can only mix the ink.
And even if you could, would that be bioethically correct ?

http://www.ieee.org/

 

[Diva Physical Verificatio]

You check for errors using the abstract view, as I said. A properly
built abstract can be used for that purpose. You do not need the layout
to check for routing to cell problems.

On 5 Aug 2004 07:25:25 -0700, yxl4444@louisiana.edu (Lee) wrote:

Hi,

Thanks for your answer.

More questions,

How can I check for problems between the routing and the cell content
without layout view?

How can I extract the wire parasitics only?

You know, the current library I am using doesn't have the layout view.
I want to make sure everything is OK before I pay money to the library
vendor and get the layout view and simulate the design again. What is
the best design flow?

Best regards,

Diva Physical Verification <diva@cadence.com> wrote in message news:<frg2h0hagku075c9hb7dsbb73dgtr1q6ho@4ax.com>...
While Andrew's solution does work, it does not check for problems
between the routing and the cell content. Every layer in the abstract
view should have keepout shapes that represent the area occupied by the
internal shapes without actually being those shapes. This lets you check
for DRC violations between the cell and the routing.

As for parasitics, you can have the abstract view switch to a schematic
or symbol view during netlisting for the simulator. Assuming the
schematic or symbol have the appropriate information, the simulator
should have everything it needs without any annotation on your part.

On 4 Aug 2004 12:58:30 -0700, yxl4444@louisiana.edu (Lee) wrote:

Andrew,

This solution definitely works. Thanks.

One more question. If I do DRC in this way, how can I extract
parasistics for post-layout simulation?

I am thinking one way: extract the wire parasistics and replace
wireload models in Synopsys by annotating the parasistics to the
design in Synopsys.Is it right?Or better way exist?

Best regards,


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<uep0h05bfca3l2jrtjikpkfmc2h2egga73@4ax.com>...
Adrian,

Assuming you're using Diva (I wish people would say which tool they are using,
since there are often alternatives. Here it could have been Diva, Assura,
Dracula or non-Cadence tools like Calibre), then one thing you could do
is to ensure that all your abstract views have a cellView property called
ivIncludeValue, with a value of (say) 2. Then run Diva DRC (flat) with the
inclusion limit set to less than that value (say 1).

Then it will omit checking any of the cells with an ivIncludeValue greater
than the specified inclusion limit value, and you'd just be checking the
routing.

Andrew.

 

[fogh]

It means there is less terminals in extracted than in layout. Because 2 terminals can not be on the same net, the extractor has to discard one of 2 terminals that are shorted.

So, did you have a short ?

Lee wrote:

I don't understand it. Could you please to tell me in more details?I
really cannot understand why this error means short.


Thanks,

fogh <cad_support@skipthisandunderscores.catena.nl> wrote in message news:<41135d8f$0$88495$e4fe514c@dreader15.news.xs4all.nl>...

"Terminal in the layout is not present in the extracted view"
Is diva's way of saying you probably have a short. This is the way it is pronounced in Transilvania.

Open the extracted view and probe where you expect this terminal, or use the short locator if you have mastered the thing, or use series resistance parasitic extraction to narrow dow to the short location...

Lee wrote:

Hi,

Sorry to bother you. I knew how to solve the stupid question now.

One more question. When I did DRC, no errors. Then I did Extraction in
Diva, I got the error "Terminal in the layout is not presented in the
extracted view". How can I fix it?

Thanks,

Adrian

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0408051415.76a45e70@posting.google.com>...


Hi,

I already solved all the DRC errors in my design. But the method to
solve the following problem seems stupid.



\o 1 Label/Pin "A" is causing two nets to
have the same name.
\o 1 Label/Pin "D" is causing two nets to
have the same name.
\o 3 Label/Pin "Q" is causing two nets to
have the same name.
\o 5 Label/Pin "gnd!" is causing two nets
to have the same name.
\o 13 Label/Pin is on a net with a different
name

The reason for these problems is,

I use standard cells and every standard cell has the same the input
pin name and output pin name. In my design I don't want to connect
them each other. I delete them one by one. Is there any better way to
delete them?

Thanks,

Adrian

 

[Diva Physical Verificatio]

avSwitch is a function that allows the rules to test if a switch has
been set to get conditional compilation of rules in the same way
ivIf(switch) does. This is a moderately new feature so it would seem you
have an older build of the software.

On 7 Aug 2004 12:19:26 -0700, yxl4444@louisiana.edu (Lee) wrote:

Hi,

During LVS, I got

"undefined function: avSwitch"

What is wrong?How can I define the function?

Thanks,

 

[Diva Physical Verificatio]

You cannot run LVS without both netlists being at the same level of
detail. You handle this by having transistor level schematic views of
the gates. This is the normal case in PDK libraries.

It is difficult to say what is happening with your DRC. If full, flat
DRC does not give you an error, then it should be considered to be
correct. Hierarchical DRC is not designed to be 100% correct. It is a
way to quickly find and fix errors in a design that is larger than Diva
can handle quickly. Simply ignore any hierarchical mode errors that do
not make sense.

On 8 Aug 2004 06:37:11 -0700, yxl4444@louisiana.edu (Lee) wrote:

Hi,

In my schematic view, I use gate level netlist. In my layout view, if
I flatten the design, the extracted view will be transistor level
netlist. Can I do LVS for the gate level netlist and the transistor
level netlist in Diva? In the Cadence manual, it said that LVS should
be done in the same level. I am not quite sure about this.

One more question. Can I get the gate level netlist from layout view?

I also feel confused. In the layout view of my design, if I don't
flatten the design, diva DRC (flat method or hierachy method, full
check) of the layout has errors such as "INFO:hot well" "minimum NDIFF
to NTUB spacing = 2.6". But If I do flatten the design, diva DRC (flat
method and full check) of the layout has no errors. Why? Can this
problem be fixed?

Thanks,

 

[Andrew Beckett]

Erik,

The Tcl variable $simvision_attached will tell you if simvision is attached to
your simulation session (thanks to my colleague Kevin Chong for this).

Andrew.

On 6 Aug 2004 11:29:08 -0700, erikwanta@starband.net (Erik Wanta) wrote:

I am loading a tcl script at a project level in the project ams.env
with amsDirect.prep simVisScriptFile. I would like it to do one
thing if the simulation is run in tcl mode and another when run in the
interactive GUI mode. Is there a way to get the run mode and do an
if/then on it in the tcl script?
---
Erik

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[G Vandevalk]

Have a look at exactly how the geomConnect command is written!

It is worth it to check that the globalLabel command is not used!!!!
This command will override the labeling that comes from the top level
only!!!!
Also check the label layers. If they are not crucial, try commenting
them out!! (or restricting them to a few layers)
(My favorite way to limit this situation is to use LPPS per layer such
as "M1" "label" for M1 .... )


Also if cells are "flattened" in macro mode, the labels may then look
like the top level.
(i.e. ivPcell = "graphic" prop )

Both these (unlikely but possible) scenarios will cause the greif
described below!!!

-- Hope you have a simpler problem!!!!

-- Gerry



Diva Physical Verification wrote:

The most common cause of this error is having a terminal with a pin on a
layer which was not specified as being connected in the geomConnect
rule. The error message includes the terminal name. Find the terminal
and it's pin shape, which usually has the same name as the terminal.
From the pin shape, determine the graphics layer. Make sure there is a
layer derivation path from the graphic layer to a connected layer in the
geomConnect. See the manual section "Connectivity Extraction Concepts"
under the heading "Labeling" for an explanation of how pins get
associated to connected layers.

One very common mistake in rule writing is to leave the well and
substrate out of the geomConnect. This causes the terminal missing error
when well and substrate pins are in the layout. The geomStamp rule is
often used to create the connections to well and substrate, but that is
too late for the missing terminal analysis in geomConnect. It is much
better to include the well and substrate in the geomConnect and use the
"soft" clause to get the soft-connect error checking people use
geomStamp for.

On 5 Aug 2004 19:28:05 -0700, yxl4444@louisiana.edu (Lee) wrote:



Hi,

Sorry to bother you. I knew how to solve the stupid question now.

One more question. When I did DRC, no errors. Then I did Extraction in
Diva, I got the error "Terminal in the layout is not presented in the
extracted view". How can I fix it?

Thanks,

Adrian

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0408051415.76a45e70@posting.google.com>...


Hi,

I already solved all the DRC errors in my design. But the method to
solve the following problem seems stupid.



\o 1 Label/Pin "A" is causing two nets to
have the same name.
\o 1 Label/Pin "D" is causing two nets to
have the same name.
\o 3 Label/Pin "Q" is causing two nets to
have the same name.
\o 5 Label/Pin "gnd!" is causing two nets
to have the same name.
\o 13 Label/Pin is on a net with a different
name


The reason for these problems is,

I use standard cells and every standard cell has the same the input
pin name and output pin name. In my design I don't want to connect
them each other. I delete them one by one. Is there any better way to
delete them?

Thanks,

Adrian

 

[Andrew Beckett]

Peter,

Apologies for the delay in responding to this.

You can created VHDL-AMS textual views in DFII by using File->New->CellView
and selecting "VHDLAMS-Editor" as the tool. Any view created this way will be
compiled using ncvhdl with the -ams option.

However, with AMS Designer, schematics are always netlisted as Verilog-AMS,
and not as VHDL-AMS. This was a conscious decision, for a few main reasons:

1. Verilog-AMS allows automatic insertion of connectmodules when disparate
disciplines are connected to each other; VHDL-AMS doesn't allow this, and
so by netlisting schematics in Verilog-AMS you get more flexibility.
Because VHDL is strongly typed, the types of signals connected together
have to match, whereas Verilog-AMS's connectmodules allow you to
automatically convert one type to another.
2. The simulator supports mixed-language, so there's no real benefit in it
netlisting to VHDL-AMS.
3. It would require another netlister to be written, and since there were no
compelling reasons to have the netlist in VHDL-AMS, that hasn't been done
yet (I guess this third point is a little tautological).

So practically it all works together, but if you're using VHDL-AMS for religious
reasons (choice of VHDL or Verilog is often a religious thing rather than for
any particular language capability), then this lack of rigour may disturb
you ;-)

Andrew.

On 4 Aug 2004 10:38:44 -0700, prw@ecs.soton.ac.uk (Peter Wilson) wrote:

Yes, I have read the docs, obviously they are aimed at Verilog-A(MS),
but there is no detail for VHDL-AMS.

I can see the general principles, but getting , for example, the -AMS
option in ncvhdl is not clear in either the documentation or the GUI
(it works fine at the command line).

All I need now is an example of how to set up a resistor, say, and
then netlist a schematic containing VHDL-AMS elements targetted to
ncvhdl, with the AMS options. Then I can extend this to pretty much
any block. I have figured out the simulator (including options) and
SimVision, so getting the netlister working would be brilliant.

Thanks,
Peter

Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<o71lg090tfkfc439s7t4c9f1a5h4liutm7@4ax.com>...
Have you read the documentation on AMS Designer?

There is a tutorial included as well (may not use VHDL-AMS, but Verilog-AMS, but
you should be able to get the point).

Andrew.

On 27 Jul 2004 18:43:30 -0700, prw@ecs.soton.ac.uk (Peter Wilson) wrote:

Hi,

I would like to simulate a schematic/layout generated in Cadence using
VHDL-AMS models. How do I set this up using IC5.0/LDV5.0 and how do I
run simulations?

Also, how can I run the simulations from the command line as in
Spectre or VerilogAMS?

Thanks in advance,
Peter Wilson

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

Also, there's a problem on Linux where the form ends up rather shrunk sometimes,
and you need to stretch it to see the contents...

Andrew.

On 13 Aug 2004 02:19:03 -0700, hsingh@ece.pdx.edu (harry) wrote:

Hi shaun,
when u open the object properties form,there are few buttons over
there ,namely system ,user ,CDF.Try clicking on CDF properties u will
find,
your properties over there.
Also make sure that your transistor or instance is selected ,then
click on object and properties.
Other thing could be that on one of cyclic field ,there could be "all
or allselected" selected ,make it only current and u should be able to
see your properties.
I am assuming that u are using cadence for ur designs.

have fun
harry

sbjsale@hotmail.com (Shaun Johnson) wrote in message news:<5122ff99.0408101004.259eeda0@posting.google.com>...
When I query an instance in Composer the Object Properties form has
nothing in it. However, AnalogArtist will netlist the schematic fine,
with all default values as they should be.

Thanks for any help, Shaun

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

As I said, this is not really my area of expertise. I was just basing my answer
on memory, which may well be wrong...

Perhaps someone else can answer your questions?

Andrew.

On 13 Aug 2004 02:26:17 -0700, hsingh@ece.pdx.edu (harry) wrote:

Hi Andrew ,
thanks for ur feedback.I have selected netlist switch RC option in my
netlisting options.But I still don't see any timing parameters in my
verilog netlist.
I am using NCSU CDK design kit.I use version IC5.0.It still shiws me
netlist switch RC option ,in verilog XL netlisting Options.
If cadence has stopped supporting it.do u have any idea in which
version they stopped supporting it.
If it is not supported in my version of cadence,Do u know any other
switch-level simulator that is supported by cadence or atleast
compatible with cadence
(leaving IRSIM).
thanks again for ur help

Harry
hsingh@ece.pdx.edu

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Sporkman]

Anybody been brave (or stupid) enough to actually install this?
Personally I'm not anxious to run into a Trojan, but I wouldn't mind a
free shootemup.

garycameron@hotmail.com wrote:

Quite simpily the best shootemup ever!
http://www.tomhayesproductions.com/xenon2.zip

 

[Karl Fritz]

Oh boy, you are defnitely singing my tune! We too have this same problem
when we design larger circuits, and are looking for a solution. Spectre and
HSpice are definitely a pretty good way to get a good look at what is going
on, but it does take alot of time and horsepower(and memory). The thing we
usually do is break it into smaller blocks and do an analog simulation on
the critical areas. I have used Verilog in the past to simulate basic
delays extracted from analog simulations, but that won't give you power or
drive numbers.

I too would be curious as to what other folks do. Our designs are mainly
digital that operate from DC->80Gbps, so analog simulation is a must, and
extracted parasitics from the layout is a must! Our flow right now is to
use Composer for the schematic, LayoutXL for layout and Analog Artist(HSpice
or Spectre) for simulation while using Diva for verification.

--------------------------------------------------------------
Karl Fritz
Design Engineer
fritz.karl@mayo.edu
Special Purpose Processor Development Group - Mayo Foundation
--------------------------------------------------------------

"Lee" <yxl4444@louisiana.edu> wrote in message
news:5c3c88bc.0408120718.1b4f847a@posting.google.com...

Deat all,

If I design a big chip that includes several parts (layout) designed
by different groups, I can consider each part as a cell and do P&R and
fit it into a Padframe.

But I have a question about verification,

How can I do timing analysis and power analysis for the entire chip?If
I extract the netlist for the entire chip and do circuit level
simulation in Hspice, the simulation speed is too slow. What is the
good way to verify the entire chip in industry?

Thanks,

Adrian

 

[Andrew Beckett]

That does work - I've done it many, may times (and in fact described it on this
forum). What you need to do is look in the results browser, and look in
your normal transient output tran.tran - and navigate to the device, and it will
expand to show all the operating point data. Right click on MN0.gm and it will
plot the gm versus time.

The alternative is to use the infotimes option on transient, which allows you
specify a set of times at which it will compute the operating point. Having done
this, you can backannotate the operating point at these times back onto the
schematic.

Andrew.

On 18 Aug 2004 03:56:55 -0700, Nadine@MailSys.de (Nadine) wrote:

Hi all,

I'd like to save transistor parameters during a transient analysis. At the
moment I only get the final time data from finalTimeOP-info. I found a hint in
the net that writing a model file with save MN0 should work. But it doesn't.
The file gets read, since when I put nonsense in it, I get syntax errors.
Maybe this behaviour changed between versions? I'm using 5.0.33 and spectre.

Please tell me how I can get the data. Solutions involving either ADE or OCEAN
are both fine.

Nadine

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[A. B.]

Kumar Yelamarthi wrote:

Hello Everyone,

I am creating a design with 64 inputs and 64 outputs. While simulating
the design using Spectre, is there any procedure I could follow to
display the 64 bit output in hex format rather than displaying the
just voltage swing of each signal independently.
I searched the previous docs and was not able to find anything on
this.

Please help him in this issue.

Thank you,
Kumar
If you mean by displaying, seeing them in a waveform viewer,

independently of spectre, you can look into the menus and there
should be there something like create a bus. After creating
the bus you can change its radix to hex for example.
HTH.

 

[Andrew Beckett]

Hi Jan,

Just realised that I never responded to this (and I meant to).

Anyway, cdsMsgServer is part of MPS (Message Passing Subsystem, sometimes known
as Multi-Process SKILL), together with cdsNameServer.

cdsNameServer is a place where services can advertise, and it means that
processes within a session can advertise how they can be communicated with. This
then allows SKILL remote procedure calls between sessions, which is a protocol
used for communication between Cadence tools. For example, between DFII and the
library manager or library browser, between DFII and the hierarchy editor,
between ADE and spectre.

cdsMsgServer is a bulletin board. It is used for messages to be sent by one
process in the session, and retrieved later by another process in the session.
Useful for situations where a direct connection is not needed, but something
needs to check to see if some information has been provided yet.

Neither of these services are available for end-user use. They are used by
various tools within DFII (and other tools as well).

cdsMsgServer and cdsNameServer are started as needed, and will continue until
they have not been used for some time (I think it is 10 hours of idle time, if
memory serves me correctly). There is only one cdsMsgServer and cdsNameServer
per host, and so they will usually persist after a session has completed.

Why do you want them to end? What files would it keep open (I don't think
they open any files)?

Andrew.

On 14 Jul 2004 01:24:32 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Hello,

Does anybody know what the function is of "cdsMsgServer" daemon? I've
been searching in source link but couldn't find any usefull
information on this (certainly not "446" related). I ask because we
use cadence in a non-gui mode in our makefile driven designflow in
which this cdsMsgServer daemon is bothering us (it keeps files open).
I know it will automatically exit after a certain period but I would
like to be able to end the application by hand (in a gracefull manner
that is :&gt)

Any help/suggestion is welcome!

Rgds,

Jan Hovius

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

A couple of things:

1. in analogLib there is now nport which is a parameterised component and
supports a variable number of ports.

2. If you want to do specifically what you describe, copy (say) n2port from
analogLib into your library, and then use this as the netlisting procedure.
Remove dataFile from the CDF parameters of your cell - because the file
will be netlisted specifically by the netlisting procedure.

This code assumes that the sparam.sp file will be in the stopping cellView
(e.g. the spectre view).

defun( abNportNetlistProc (inst)
let((formatter netlister pathName)
;----------------------------------------------------------------
; Get hold of the formatter and netlister objects
;----------------------------------------------------------------
formatter=nlGetFormatter(inst)
netlister=nlGetNetlister(formatter)
;----------------------------------------------------------------
; Print the standard instance line
;----------------------------------------------------------------
nlPrintInst(formatter inst)
;----------------------------------------------------------------
; Add on the path to the sparam.sp within the cellView
;----------------------------------------------------------------
pathName=nlGetCurrentSwitchMaster(netlister)~>view~>readPath
nlPrintString(netlister
sprintf(nil " file=\"%s/sparam.sp\"" pathName)
) ; nlPrintString
t
)
)

If there's a schematic view, then the normal view switching will be used, and
it won't use the netlisting procedure in that case. So nothing special is
needed to support schematics.

Andrew.


On 12 Aug 2004 00:40:28 -0700, ercan@vlsi.itu.edu.tr (Ercan Altuntas) wrote:

Hi Erik,

That is a good idea but my s parameter file is for a 6 port device and
I have to change analogLib for this and also file path has to be an absolote
path for nXport device. If the component is copied to another cell, then it
will use the original cell's s parameter file.

Thanks.



erikwanta@starband.net (Erik Wanta) wrote in message news:<84018314.0408101642.3737f259@posting.google.com>...
Ercan:
We typically just use a schematic and place down a nXport component
from analogLib for something like this. If you have a schematic view
and s parameters for the cell you could create schematic_sp view that
has the nXport component and use the hierarchy editor to switch to
schematic_sp for that cell.
---
Erik

ercan@vlsi.itu.edu.tr (Ercan Altuntas) wrote in message news:<108fadf.0408092242.499a8228@posting.google.com>...
Hi,

I am trying to write a netlistProcedure for spectre. If a schematic view exits for
the cellview, it will netlist this schematic a subcircuit. Otherwise a NPORT
device will be netlisted. s parameters are saved a text view in the cell view.
I couldn't find any examples for netlistProcedure. Can you give some hints for me?

Thanks

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

On Fri, 20 Aug 2004 00:55:08 GMT, daytripper <day_trippr@REMOVEyahoo.com> wrote:

On Thu, 19 Aug 2004 05:58:54 +0100, Andrew Beckett
[snipped]
Why do you want them to end? What files would it keep open (I don't think
they open any files)?

I think I know what the OP is referring to, and I see the same behavior: if I
have a project open, then close the project and try to delete or rename
certain project files and/or folders, the OS bitches that the files cannot be
manipulated because some process still has them open.

I see this particularly when switching back and forth between major Cadence
versions and related projects. Killing the nameserver and messageserver
processes allows switching versions or manipulating these same files without
any other headaches...

/daytripper

I'm sorry, but I don't think cdsNameServer and cdsMsgServer have anything to
do with this. I change versions extremely frequently (since I'm in customer
support, it is many times per day), and _never_ see problems like this.

Killing cdsNameServer/cdsMsgServer can be problematic if there are processes
running which are still using their services - it can cause those other
still-running processes (things like cdsdoc for example) to then get stuck, or
fail to communicate with each other.

So, some details of what these files are would be useful before making such a
statement...

Andrew.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Diva Physical Verificatio]

On Fri, 20 Aug 2004 04:08:50 +0100, Andrew Beckett
<andrewb@DELETETHISBITcadence.com> wrote:

On Fri, 20 Aug 2004 00:55:08 GMT, daytripper <day_trippr@REMOVEyahoo.com> wrote:

On Thu, 19 Aug 2004 05:58:54 +0100, Andrew Beckett
[snipped]
Why do you want them to end? What files would it keep open (I don't think
they open any files)?

I think I know what the OP is referring to, and I see the same behavior: if I
have a project open, then close the project and try to delete or rename
certain project files and/or folders, the OS bitches that the files cannot be
manipulated because some process still has them open.

I see this particularly when switching back and forth between major Cadence
versions and related projects. Killing the nameserver and messageserver
processes allows switching versions or manipulating these same files without
any other headaches...

/daytripper

I'm sorry, but I don't think cdsNameServer and cdsMsgServer have anything to
do with this. I change versions extremely frequently (since I'm in customer
support, it is many times per day), and _never_ see problems like this.

Killing cdsNameServer/cdsMsgServer can be problematic if there are processes
running which are still using their services - it can cause those other
still-running processes (things like cdsdoc for example) to then get stuck, or
fail to communicate with each other.

So, some details of what these files are would be useful before making such a
statement...

Andrew.

I have to agree with Andrew. I currently have 4.4.5, 4.4.6, 5.0.0,
5.0.32, 5.0.33ISR, 5.0.33USR2 (before, during, and after the cdsVia
fiasco), 5.0.33USR3, 5.0.41, 5.1.41ISR, 5.1.41USR1, 5.2.51, and 5.2.51OA
installed and/or built on my workstation. They all play together,
occasionally at the same time, without ever needing to kill anything.

Of course, I have the latest versions available installed, or things
that are not yet available, so maybe your problem is you are running
code that still has some of the bugs that have been fixed since the
initial release. I seem to recall there being a bug in the early builds
of 5.0.32 that might be what you are seeing.

 

[Andrew Beckett]

Hi Jan,

Apologies again for the lateness of my original reply - I got a bit backlogged
in processing things (they day job got in the way ;-> )

One situation I've seen where daemons started by DFII causign trouble
occasionally is with LSF. From my understanding LSF doesn't see a job as
finished if it still has child processes running (i.e. processes in the same
process group). Not sure if that's the case here, but I know in the past some
customers have had to do various things with some daemons (like explicitly
starting them on a machine in a compute farm) to get around this.

There may be ways around it in LSF too - but I'm not really that familiar with
LSF.

Andrew.

On 20 Aug 2004 13:03:23 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

daytripper <day_trippr@REMOVEyahoo.com> wrote in message news:<emiai01vgfgfpc883468jir1f0ijlfd8fa@4ax.com>...
On Thu, 19 Aug 2004 05:58:54 +0100, Andrew Beckett
andrewb@DELETETHISBITcadence.com> wrote:
On 14 Jul 2004 01:24:32 -0700, Jan.Hovius@nsc.com (Jan Hovius) wrote:

Hello,

Does anybody know what the function is of "cdsMsgServer" daemon? I've
been searching in source link but couldn't find any usefull
information on this (certainly not "446" related). I ask because we
use cadence in a non-gui mode in our makefile driven designflow in
which this cdsMsgServer daemon is bothering us (it keeps files open).
I know it will automatically exit after a certain period but I would
like to be able to end the application by hand (in a gracefull manner
that is :&gt)

[snipped]
Why do you want them to end? What files would it keep open (I don't think
they open any files)?

I think I know what the OP is referring to, and I see the same behavior: if I
have a project open, then close the project and try to delete or rename
certain project files and/or folders, the OS bitches that the files cannot be
manipulated because some process still has them open.

I see this particularly when switching back and forth between major Cadence
versions and related projects. Killing the nameserver and messageserver
processes allows switching versions or manipulating these same files without
any other headaches...

/daytripper

Sorry for this late reply. I wasn't aware there finally was some
response on this question. Unfortunately I can't recall what the exact
reason was for this posting (sorry Andrew can't give you a
name/example) but it indeed was a locking issue after exiting your
cadence environment. The problem surfaced in our attempt to automate
our synchronicity based makefile flow in which we directly have to
access files in the cadence design database.
Andrew, I have to consult my collegue again (he ran into this problem)
for the details (in the meantime he already found a workaround for
it).


Rgds,

Jan.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Spaller]

"Ronald" <rkdocc@yahoo.com> wrote in message
news:f96c3977.0407230849.3cca9ab7@posting.google.com...

Some of the gds reader tool defined before are good.

In Cadence flow, you could use pipo to get the top cell name.
This is a dummy way but as effective to get the data.

Make a script which
1. build a pipo streamin file, example file /tmp/tmp.pipo
streamInKeys = '(nil
runDir "/tmp"
errFile "/tmp/PIPO.debug.100967565"
inFile "/home/ronald/mycellname/all.gds"
dataDump "/tmp/stout.ronald.100967565"
scale 0.001
units "micron"
caseSensitivity "preserve")
2. run "pipo strmin /tmp/tmp.pipo "
3. Parse /tmp/PIPO.debug.100967565 until you find the first line
with "1. scanning cellview"... This line indicates
the top cell name and its cell view.
Example:
1. scanning cellview (libcell_ronald layout)
You know that your top cell is libcell_ronald

This is true only in the case where the gdsII file is created as a streamOut
of a given top cell, and that particular file was created in top-down order.

The later versions of pipo stream out in bottom-up order, so the last cell
would be the "top cell".

The "top cell" is in quotes since an entire library could have been streamed
out, and so there could be multiple top cells in the gdsII file.

In that case, the top cells would be those which are not referenced by any
other cell, but that is an entirely different thing that pipo will not tell
you.

spaller

--

....