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Mike Monett VE3BTI wrote:
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
An alternative is to design the part out. Two 7404 inverters with
feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.
But not at subnanosecond speed!
Of course not. I expect you to substitute your favorite AUC or AVC.
Besides,
Lasse found the TI part at LCSC.
A schmidt part is usually only needed on I/O ports. These rarely go to
1GHz.
I rack my brain, but I can\'t find any need for non-inverting
hysteresis on
internal circuitry, except for RC multivibrators. These normally don\'t
go to
1GHz.
Squaring up slower logic before reclocking, for instance.
On Thu, 01 Sep 2022 13:58:21 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:
On Thu, 1 Sep 2022 13:10:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
torsdag den 1. september 2022 kl. 21.46.46 UTC+2 skrev John Larkin:
On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:
Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.
I wish there were disctete flops with a CE input.
an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.
https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.
one part in a tiny package and maybe a nanosecond or two
We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.
if the signals are not synchronous there is no way around it, there will
be hazards
Any async trigger requires two flip-flops in series to reclock into the
local clock domain.
Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.
We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.
We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.
Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.
http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm
2002, time flies...
A couple ns of added delay every billion years is a risk that I am
inclined to take.
Yes.
Metastability plagued folk back in the day, until exactly what was
going on was understood (by a colleague of mine in the late 1970s to
early 1980s). Then metastability became just another design checklist
item.
Joe Gwinn
On Thu, 01 Sep 2022 17:25:36 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
On Thu, 01 Sep 2022 13:58:21 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:
On Thu, 1 Sep 2022 13:10:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
torsdag den 1. september 2022 kl. 21.46.46 UTC+2 skrev John Larkin:
On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:
Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.
I wish there were disctete flops with a CE input.
an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.
https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.
one part in a tiny package and maybe a nanosecond or two
We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.
if the signals are not synchronous there is no way around it, there will
be hazards
Any async trigger requires two flip-flops in series to reclock into the
local clock domain.
Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.
We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.
We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.
Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.
http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm
2002, time flies...
A couple ns of added delay every billion years is a risk that I am
inclined to take.6
Yes.
Metastability plagued folk back in the day, until exactly what was
going on was understood (by a colleague of mine in the late 1970s to
early 1980s). Then metastability became just another design checklist
item.
Joe Gwinn
Some flops, famously LSTTL, had wild oscillatory metastability. An
LS74 would make audible ticks into a nearby FM radio; it would
oscillate for microseconds. There are times when symmetry is the
enemy.
Transmission-gate CMOS flops tend to not oscillate, just have extended
prop delay that resolves quickly.
I\'ll be using a discrete Tiny Logic flop, the 1 ns NC7SV74, and I know
nothing about its metastability behavior. But most of the time the
customer clocks it true, we do what he wants, we reset the flop, and
it\'s ready for another trigger. There\'s no hazard there.
On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:
Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.
I wish there were disctete flops with a CE input.
an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.
https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.
one part in a tiny package and maybe a nanosecond or two
We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.
if the signals are not synchronous there is no way around it, there will
be hazards
Any async trigger requires two flip-flops in series to reclock into the
local clock domain.
Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.
We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.
We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.
Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.
Also, the ones designed for schmidt input has lower cross conduction
rail current, which in other cases can be huge when the input is mid level
Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:
Also, the ones designed for schmidt input has lower cross conduction
rail current, which in other cases can be huge when the input is mid level
Any CMOS device has high conduction when the input is at mid level. This is
what causes to switching glitches and ground bounce. For example, a 74AC
device is much noisier than a 74AH.
On Thu, 01 Sep 2022 15:07:01 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:
On Thu, 01 Sep 2022 17:25:36 -0400, Joe Gwinn <joegwinn@comcast.net
wrote:
On Thu, 01 Sep 2022 13:58:21 -0700, John Larkin
jlarkin@highland_atwork_technology.com> wrote:
On Thu, 1 Sep 2022 13:10:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
torsdag den 1. september 2022 kl. 21.46.46 UTC+2 skrev John Larkin:
On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:
Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.
I wish there were disctete flops with a CE input.
an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.
https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.
one part in a tiny package and maybe a nanosecond or two
We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.
if the signals are not synchronous there is no way around it, there will
be hazards
Any async trigger requires two flip-flops in series to reclock into the
local clock domain.
Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.
We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.
We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.
Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.
http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm
2002, time flies...
A couple ns of added delay every billion years is a risk that I am
inclined to take.6
Yes.
Metastability plagued folk back in the day, until exactly what was
going on was understood (by a colleague of mine in the late 1970s to
early 1980s). Then metastability became just another design checklist
item.
Joe Gwinn
I think I found the reference:
\"Theoretical and Experimental Behavior of Synchronizers Operating in
the Metastable Region\", GEORGE R. COURANZ and DONALD F. WANN, IEEE
TRANSACTIONS ON COMPUTERS, VOL. c-24, NO. 6, June 1975, pages 604-616.
Now DOI: 10.1109/T-C.1975.224273.
Couranz was my colleague in the 1980s.
Some flops, famously LSTTL, had wild oscillatory metastability. An
LS74 would make audible ticks into a nearby FM radio; it would
oscillate for microseconds. There are times when symmetry is the
enemy.
Yeah. LSTTL was introduced in 1976.
Transmission-gate CMOS flops tend to not oscillate, just have extended
prop delay that resolves quickly.
I\'ll be using a discrete Tiny Logic flop, the 1 ns NC7SV74, and I know
nothing about its metastability behavior. But most of the time the
customer clocks it true, we do what he wants, we reset the flop, and
it\'s ready for another trigger. There\'s no hazard there.
A big reason that metastability is so much less of a problem is the
greatly reduced internal delay times due to the considerable
improvements in semiconductor technology. The effect of delay on
metastability is exponential, and this makes it easy to simply wait
long enough for things to have settled.
Joe Gwinn