NC7WZ17 schmitt...

[John Larkin]

On Wed, 31 Aug 2022 16:38:35 -0000 (UTC), Mike Monett VE3BTI
<spamme@not.com> wrote:

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs

WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.

Making hysteresis with external resistors is dicey. You can usually
couple a whoopie-doo through a gate or two before the external
hysteresis makes it around.

Any designer is going to check availability before designing a part in, so
the problem is confined to old units. Repair means only one or two may be
needed at a time, or simply scrap the unit.

Logic glue is going away, so the function may be replaced with an FPGA or
ASIC, or a microcontroller such as the STM32. There\'s all kinds of options,
so the solution is to not throw up your hands and say it can\'t be done.

FPGAs are getting faster internally and slower in and out. And they
have a ton of jitter if there are multiple signals and clocks on the
chip. Sometimes glue logic is much better. Minimal FPGA pin-pin delays
are in the 6 ns ballpark.

We sometimes wrap an FPGA around a discrete flop, to do its gating and
reset and stuff, but keep the CLK>Q critical, fast, low jitter path
discrete.

I wish there were disctete flops with a CE input. And an LVDS logic
family.

 

[Lasse Langwadt Christensen]

onsdag den 31. august 2022 kl. 21.51.51 UTC+2 skrev John Larkin:

On Wed, 31 Aug 2022 16:38:35 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs

WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.
Making hysteresis with external resistors is dicey. You can usually
couple a whoopie-doo through a gate or two before the external
hysteresis makes it around.

Any designer is going to check availability before designing a part in, so
the problem is confined to old units. Repair means only one or two may be
needed at a time, or simply scrap the unit.

Logic glue is going away, so the function may be replaced with an FPGA or
ASIC, or a microcontroller such as the STM32. There\'s all kinds of options,
so the solution is to not throw up your hands and say it can\'t be done.
FPGAs are getting faster internally and slower in and out. And they
have a ton of jitter if there are multiple signals and clocks on the
chip. Sometimes glue logic is much better. Minimal FPGA pin-pin delays
are in the 6 ns ballpark.

We sometimes wrap an FPGA around a discrete flop, to do its gating and
reset and stuff, but keep the CLK>Q critical, fast, low jitter path
discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ?

>And an LVDS logic family.

https://www.onsemi.com/products/timing-logic-memory/clock-data-distribution/logic-gates/nb7l86a

 

[Phil Hobbs]

John Larkin wrote:

On Wed, 31 Aug 2022 14:22:53 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Lasse Langwadt Christensen wrote:
onsdag den 31. august 2022 kl. 19.52.23 UTC+2 skrev Phil Hobbs:
Lasse Langwadt Christensen wrote:
onsdag den 31. august 2022 kl. 18.38.52 UTC+2 skrev Mike Monett VE3BTI:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs
WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0


https://lcsc.com/product-detail/Buffers-Drivers_Texas-Instruments-SN74LVC2G17DBVR_C10429.html

16791 in stock, US$0.0884 for 1000+


Would be worth checking out, but there\'s no guarantee they\'re fast like
the ones JL posted. The onsemi ones were several times faster than the
datasheet limit.

the SN74LVC2G17 datasheet list 2.2ns/5.4ns min/max @ 3.3V and 1.5ns/4.3ns min/max @ 5V -40\'C-85\'C, 50pf/500R

the NC7WZ17 datasheet list 7.3ns max @3.3V and 6.2ns max @5V with no minimums -40\'C-85\'C, 50pf/500R


so on paper Johns part look slower, but who knows

His pictures are showing 600 ps edges. Some LVDS line receivers are
faster--my late fave FIN1018 is around 400 ps.

Cheers

Phil Hobbs

This tiny flop is crazy:

https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0

Prop delay is spec\'d 1 ns typ.

Interesting that the rise is so much faster than the fall--128 ps vs.
400 ps. Since the NFETs are faster than the PFETs, one gathers that it
has more to do with the turn-off time than the turn-on.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Lasse Langwadt Christensen]

torsdag den 1. september 2022 kl. 00.42.49 UTC+2 skrev Phil Hobbs:

John Larkin wrote:
On Wed, 31 Aug 2022 14:22:53 -0400, Phil Hobbs
pcdhSpamM...@electrooptical.net> wrote:

Lasse Langwadt Christensen wrote:
onsdag den 31. august 2022 kl. 19.52.23 UTC+2 skrev Phil Hobbs:
Lasse Langwadt Christensen wrote:
onsdag den 31. august 2022 kl. 18.38.52 UTC+2 skrev Mike Monett VE3BTI:
Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs
WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0


https://lcsc.com/product-detail/Buffers-Drivers_Texas-Instruments-SN74LVC2G17DBVR_C10429.html

16791 in stock, US$0.0884 for 1000+


Would be worth checking out, but there\'s no guarantee they\'re fast like
the ones JL posted. The onsemi ones were several times faster than the
datasheet limit.

the SN74LVC2G17 datasheet list 2.2ns/5.4ns min/max @ 3.3V and 1.5ns/4.3ns min/max @ 5V -40\'C-85\'C, 50pf/500R

the NC7WZ17 datasheet list 7.3ns max @3.3V and 6.2ns max @5V with no minimums -40\'C-85\'C, 50pf/500R


so on paper Johns part look slower, but who knows

His pictures are showing 600 ps edges. Some LVDS line receivers are
faster--my late fave FIN1018 is around 400 ps.

Cheers

Phil Hobbs

This tiny flop is crazy:

https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0

Prop delay is spec\'d 1 ns typ.



Interesting that the rise is so much faster than the fall--128 ps vs.
400 ps. Since the NFETs are faster than the PFETs, one gathers that it
has more to do with the turn-off time than the turn-on.
Cheers

the datasheet also list slightly lower dropout for Voh than Vol

 

[John Larkin]

On Wed, 31 Aug 2022 13:25:05 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

onsdag den 31. august 2022 kl. 21.51.51 UTC+2 skrev John Larkin:
On Wed, 31 Aug 2022 16:38:35 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs

WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.
Making hysteresis with external resistors is dicey. You can usually
couple a whoopie-doo through a gate or two before the external
hysteresis makes it around.

Any designer is going to check availability before designing a part in, so
the problem is confined to old units. Repair means only one or two may be
needed at a time, or simply scrap the unit.

Logic glue is going away, so the function may be replaced with an FPGA or
ASIC, or a microcontroller such as the STM32. There\'s all kinds of options,
so the solution is to not throw up your hands and say it can\'t be done.
FPGAs are getting faster internally and slower in and out. And they
have a ton of jitter if there are multiple signals and clocks on the
chip. Sometimes glue logic is much better. Minimal FPGA pin-pin delays
are in the 6 ns ballpark.

We sometimes wrap an FPGA around a discrete flop, to do its gating and
reset and stuff, but keep the CLK>Q critical, fast, low jitter path
discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ?

Close but maybe a little squirrely.

And an LVDS logic family.

https://www.onsemi.com/products/timing-logic-memory/clock-data-distribution/logic-gates/nb7l86a

Yes, PECL logic is mostly LVDS compatible. But that one is $32 and the
cmos flop is 12 cents. We do use some GigaComm parts when we really
need the speed. Fast, expensive power hogs.


We\'ll fake a CE function on an NC7SV74 by bashing preset and clear; we
just had a meeting about that. I\'ve been assigned to dremel up a test
board to see if it behaves itself. I\'ve seen flops that can propagate
a glitch from a clocked input even when held clear.

 

[Lasse Langwadt Christensen]

torsdag den 1. september 2022 kl. 01.33.53 UTC+2 skrev John Larkin:

On Wed, 31 Aug 2022 13:25:05 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

onsdag den 31. august 2022 kl. 21.51.51 UTC+2 skrev John Larkin:
On Wed, 31 Aug 2022 16:38:35 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs

WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.
Making hysteresis with external resistors is dicey. You can usually
couple a whoopie-doo through a gate or two before the external
hysteresis makes it around.

Any designer is going to check availability before designing a part in, so
the problem is confined to old units. Repair means only one or two may be
needed at a time, or simply scrap the unit.

Logic glue is going away, so the function may be replaced with an FPGA or
ASIC, or a microcontroller such as the STM32. There\'s all kinds of options,
so the solution is to not throw up your hands and say it can\'t be done.
FPGAs are getting faster internally and slower in and out. And they
have a ton of jitter if there are multiple signals and clocks on the
chip. Sometimes glue logic is much better. Minimal FPGA pin-pin delays
are in the 6 ns ballpark.

We sometimes wrap an FPGA around a discrete flop, to do its gating and
reset and stuff, but keep the CLK>Q critical, fast, low jitter path
discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ?
Close but maybe a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.png

 

[server]

On Wed, 31 Aug 2022 18:15:53 -0000 (UTC), Mike Monett VE3BTI
<spamme@not.com> wrote:

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.

But not at subnanosecond speed!

Of course not. I expect you to substitute your favorite AUC or AVC. Besides,
Lasse found the TI part at LCSC.

A schmidt part is usually only needed on I/O ports. These rarely go to 1GHz.

I rack my brain, but I can\'t find any need for non-inverting hysteresis on
internal circuitry, except for RC multivibrators. These normally don\'t go to
1GHz.

One use is for making delays, with an RC or RLC. We use this schmitt
on about 50 different boards.

I\'m now using them as a 1to8 clock fanout, which doesn\'t need the
schmitt function, but it\'s free.

 

[server]

On Wed, 31 Aug 2022 16:40:18 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 1. september 2022 kl. 01.33.53 UTC+2 skrev John Larkin:
On Wed, 31 Aug 2022 13:25:05 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

onsdag den 31. august 2022 kl. 21.51.51 UTC+2 skrev John Larkin:
On Wed, 31 Aug 2022 16:38:35 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs

WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.
Making hysteresis with external resistors is dicey. You can usually
couple a whoopie-doo through a gate or two before the external
hysteresis makes it around.

Any designer is going to check availability before designing a part in, so
the problem is confined to old units. Repair means only one or two may be
needed at a time, or simply scrap the unit.

Logic glue is going away, so the function may be replaced with an FPGA or
ASIC, or a microcontroller such as the STM32. There\'s all kinds of options,
so the solution is to not throw up your hands and say it can\'t be done.
FPGAs are getting faster internally and slower in and out. And they
have a ton of jitter if there are multiple signals and clocks on the
chip. Sometimes glue logic is much better. Minimal FPGA pin-pin delays
are in the 6 ns ballpark.

We sometimes wrap an FPGA around a discrete flop, to do its gating and
reset and stuff, but keep the CLK>Q critical, fast, low jitter path
discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ?
Close but maybe a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.png

Sure, but that adds parts and delay and maybe hazards.

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

 

[Lasse Langwadt Christensen]

torsdag den 1. september 2022 kl. 04.37.25 UTC+2 skrev jla...@highlandsniptechnology.com:

On Wed, 31 Aug 2022 16:40:18 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 1. september 2022 kl. 01.33.53 UTC+2 skrev John Larkin:
On Wed, 31 Aug 2022 13:25:05 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

onsdag den 31. august 2022 kl. 21.51.51 UTC+2 skrev John Larkin:
On Wed, 31 Aug 2022 16:38:35 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Nobody but the grey market folks has any stock. Mouser is expecting 12
parts in February 2024.

Cheers

Phil Hobbs

WinSource has plenty. They are based in Hong Kong, but so what. Most
semiconductors are made in China anyway.

Yes, you have to worry about counterfeits, but you can get them from
anywhere. That\'s the reason for using Mouser or Digi-Key for production.

Texas Instruments has a drop-in replacement that is readily available, but
it is pricey:

https://octopart.com/search?q=SN74LVC2G17&currency=CAD&specs=0

An alternative is to design the part out. Two 7404 inverters with feedback
can give just about any amount of hysteresis needed, or a 7414 followed
with a 7404.
Making hysteresis with external resistors is dicey. You can usually
couple a whoopie-doo through a gate or two before the external
hysteresis makes it around.

Any designer is going to check availability before designing a part in, so
the problem is confined to old units. Repair means only one or two may be
needed at a time, or simply scrap the unit.

Logic glue is going away, so the function may be replaced with an FPGA or
ASIC, or a microcontroller such as the STM32. There\'s all kinds of options,
so the solution is to not throw up your hands and say it can\'t be done.
FPGAs are getting faster internally and slower in and out. And they
have a ton of jitter if there are multiple signals and clocks on the
chip. Sometimes glue logic is much better. Minimal FPGA pin-pin delays
are in the 6 ns ballpark.

We sometimes wrap an FPGA around a discrete flop, to do its gating and
reset and stuff, but keep the CLK>Q critical, fast, low jitter path
discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ?
Close but maybe a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.png
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will be hazards

 

[Mike Monett VE3BTI]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.




--
MRM

 

[Lasse Langwadt Christensen]

torsdag den 1. september 2022 kl. 20.03.28 UTC+2 skrev Mike Monett VE3BTI:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards
Any async trigger requires two flip-flops in series to reclock into the
local clock domain.

usually, but it depends

 

[Mike Monett VE3BTI]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.


usually, but it depends

on what?



--
MRM

 

[Ricky]

On Thursday, September 1, 2022 at 2:30:56 PM UTC-4, Mike Monett VE3BTI wrote:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.


usually, but it depends
on what?

If there are more than one data or enable lines, it is a race condition. The synchronizing FFs can capture a change in one signal, while not the other. If it were only a single data line, fine, that\'s no problem. Otherwise, the clock needs to be synchronized into the clock domain of the data/enable. If that\'s not realistic because of the specifications, then you may have a problem.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christensen]

torsdag den 1. september 2022 kl. 20.30.56 UTC+2 skrev Mike Monett VE3BTI:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.


usually, but it depends
on what?

what you are going to do with the signal

if something happens on a clock edge and you are the only one looking at it, it doesn\'t matter if you miss it, you\'ll see it next edge.
if you and three others look at it and some see it and some miss it all hell might break loose

two flops are the safe way, but it isn\'t always required

 

[Joe Gwinn]

On Thu, 1 Sep 2022 11:18:28 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 1. september 2022 kl. 20.03.28 UTC+2 skrev Mike Monett VE3BTI:
Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards
Any async trigger requires two flip-flops in series to reclock into the
local clock domain.


usually, but it depends

On metastability, for one:

..<https://en.wikipedia.org/wiki/Metastability_(electronics)>


Joe Gwinn

 

[John Larkin]

On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
<spamme@not.com> wrote:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.

Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.

We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.

We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.

Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.

 

[Lasse Langwadt Christensen]

torsdag den 1. september 2022 kl. 21.46.46 UTC+2 skrev John Larkin:

On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.

Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.

We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.

We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.

Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.

http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm

2002, time flies...

 

[Mike Monett VE3BTI]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

what you are going to do with the signal

if something happens on a clock edge and you are the only one looking at
it, it doesn\'t matter if you miss it, you\'ll see it next edge. if you
and three others look at it and some see it and some miss it all hell
might break loose

two flops are the safe way, but it isn\'t always required

Your link:

http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm

Every time I tried to skip the second flop, I got my fingers rapped. You need
two flops in series.




--
MRM

 

[John Larkin]

On Thu, 1 Sep 2022 13:10:32 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 1. september 2022 kl. 21.46.46 UTC+2 skrev John Larkin:
On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.

Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.

We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.

We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.

Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.

http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm

2002, time flies...

A couple ns of added delay every billion years is a risk that I am
inclined to take.

 

[Joe Gwinn]

On Thu, 01 Sep 2022 13:58:21 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

On Thu, 1 Sep 2022 13:10:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 1. september 2022 kl. 21.46.46 UTC+2 skrev John Larkin:
On Thu, 1 Sep 2022 18:03:20 -0000 (UTC), Mike Monett VE3BTI
spa...@not.com> wrote:

Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

We sometimes wrap an FPGA around a discrete flop, to do its
gating and reset and stuff, but keep the CLK>Q critical, fast,
low jitter path discrete.

I wish there were disctete flops with a CE input.

an FF and a 1 of 2 mux on the data? SN74LVC1G19 ? Close but maybe
a little squirrely.

https://asicdigitaldesign.files.wordpress.com/2008/10/enable_flops_01.p
ng
Sure, but that adds parts and delay and maybe hazards.

one part in a tiny package and maybe a nanosecond or two

We\'re not building a synchronous machine. The flop\'s clock is an async
trigger from a customer input, and enable comes from a mostly clocked
FPGA.

if the signals are not synchronous there is no way around it, there will
be hazards

Any async trigger requires two flip-flops in series to reclock into the
local clock domain.

Not necessarily. It\'s a matter of calculated probability and effects
of a possible metastability.

We have to trigger on a customer\'s rising edge. We don\'t have two
clocks. But we do have to enable triggers and reset the HIT flop, so
there are hazards. The issue is in the numbers.

We might evaluate the flop for metastability behavior. That\'s a tricky
measurememnt.

Sadly-missed Peter Alfke told me to never worry about the flops inside
an FPGA. He said that metastability was basically impossible.

http://xilinx.pe.kr/_xilinx/html/tip/metastability.htm

2002, time flies...




A couple ns of added delay every billion years is a risk that I am
inclined to take.

Yes.

Metastability plagued folk back in the day, until exactly what was
going on was understood (by a colleague of mine in the late 1970s to
early 1980s). Then metastability became just another design checklist
item.

Joe Gwinn