A
Alain
Guest
Hi NG
I'm trying to use the arithmetic modulo in an index assignement within a
generate block.
Modelsim and Xilinx ISE seem not to understand this.
data_IQ_c, data_I_b are std_logic_vector(111 downto 0)
Here's the code:
datamapping : for i in 0 to 7 generate
-- write either I or Q alternating to linebuffer
-- with every address, words get shifted by one word. This is to
make sure
-- that a column-continuous data stream can be read out by port b
of linebuffer
begin
data_IQ_c <= data_I_b(14*(i+7)+13 mod 112 downto 14*(i+7) mod 112)&
data_I_b(14*(i+6)+13 mod 112 downto 14*(i+6) mod 112)&
data_I_b(14*(i+5)+13 mod 112 downto 14*(i+5) mod 112)&
data_I_b(14*(i+4)+13 mod 112 downto 14*(i+4) mod 112)&
data_I_b(14*(i+3)+13 mod 112 downto 14*(i+3) mod 112)&
data_I_b(14*(i+2)+13 mod 112 downto 14*(i+2) mod 112)&
data_I_b(14*(i+1)+13 mod 112 downto 14*(i+1) mod 112)&
data_I_b(14*(i+0)+13 mod 112 downto 14*(i+0) mod 112)
when word_shift_i = int2vec(i,3) and iqsel_i = '0';
end generate datamapping;
----
And here's the modelsim error:
# ------------------- simulate! ---------------------------
# vsim -lib tb3k_tb -t 1ps line_buffer_tb
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: D:/work/QMFLIM/FPGA/sim/../vhdl/line_buf_ctrl_fsm.vhd(184):
(vopt-1167) Index value 112 is out of
ieee.std_logic_1164.std_logic_vector range 111 downto 0.
.....
------------------------------------------------------
can anyone tell me what the problem is?
kind regards
Alain
I'm trying to use the arithmetic modulo in an index assignement within a
generate block.
Modelsim and Xilinx ISE seem not to understand this.
data_IQ_c, data_I_b are std_logic_vector(111 downto 0)
Here's the code:
datamapping : for i in 0 to 7 generate
-- write either I or Q alternating to linebuffer
-- with every address, words get shifted by one word. This is to
make sure
-- that a column-continuous data stream can be read out by port b
of linebuffer
begin
data_IQ_c <= data_I_b(14*(i+7)+13 mod 112 downto 14*(i+7) mod 112)&
data_I_b(14*(i+6)+13 mod 112 downto 14*(i+6) mod 112)&
data_I_b(14*(i+5)+13 mod 112 downto 14*(i+5) mod 112)&
data_I_b(14*(i+4)+13 mod 112 downto 14*(i+4) mod 112)&
data_I_b(14*(i+3)+13 mod 112 downto 14*(i+3) mod 112)&
data_I_b(14*(i+2)+13 mod 112 downto 14*(i+2) mod 112)&
data_I_b(14*(i+1)+13 mod 112 downto 14*(i+1) mod 112)&
data_I_b(14*(i+0)+13 mod 112 downto 14*(i+0) mod 112)
when word_shift_i = int2vec(i,3) and iqsel_i = '0';
end generate datamapping;
----
And here's the modelsim error:
# ------------------- simulate! ---------------------------
# vsim -lib tb3k_tb -t 1ps line_buffer_tb
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: D:/work/QMFLIM/FPGA/sim/../vhdl/line_buf_ctrl_fsm.vhd(184):
(vopt-1167) Index value 112 is out of
ieee.std_logic_1164.std_logic_vector range 111 downto 0.
.....
------------------------------------------------------
can anyone tell me what the problem is?
kind regards
Alain