modulo seems not to work when using in index

[Alain]

Hi NG

I'm trying to use the arithmetic modulo in an index assignement within a
generate block.
Modelsim and Xilinx ISE seem not to understand this.

data_IQ_c, data_I_b are std_logic_vector(111 downto 0)
Here's the code:


datamapping : for i in 0 to 7 generate
-- write either I or Q alternating to linebuffer
-- with every address, words get shifted by one word. This is to
make sure
-- that a column-continuous data stream can be read out by port b
of linebuffer

begin
data_IQ_c <= data_I_b(14*(i+7)+13 mod 112 downto 14*(i+7) mod 112)&
data_I_b(14*(i+6)+13 mod 112 downto 14*(i+6) mod 112)&
data_I_b(14*(i+5)+13 mod 112 downto 14*(i+5) mod 112)&
data_I_b(14*(i+4)+13 mod 112 downto 14*(i+4) mod 112)&
data_I_b(14*(i+3)+13 mod 112 downto 14*(i+3) mod 112)&
data_I_b(14*(i+2)+13 mod 112 downto 14*(i+2) mod 112)&
data_I_b(14*(i+1)+13 mod 112 downto 14*(i+1) mod 112)&
data_I_b(14*(i+0)+13 mod 112 downto 14*(i+0) mod 112)
when word_shift_i = int2vec(i,3) and iqsel_i = '0';
end generate datamapping;

----

And here's the modelsim error:

# ------------------- simulate! ---------------------------
# vsim -lib tb3k_tb -t 1ps line_buffer_tb
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: D:/work/QMFLIM/FPGA/sim/../vhdl/line_buf_ctrl_fsm.vhd(184):
(vopt-1167) Index value 112 is out of
ieee.std_logic_1164.std_logic_vector range 111 downto 0.
.....
------------------------------------------------------

can anyone tell me what the problem is?

kind regards
Alain

 

[Pascal Peyremorte]

Alain a écrit :

Hi NG
data_IQ_c <= data_I_b(14*(i+7)+13 mod 112 downto 14*(i+7) mod 112)&
data_I_b(14*(i+6)+13 mod 112 downto 14*(i+6) mod 112)&

[...]

(vopt-1167) Index value 112 is out of
ieee.std_logic_1164.std_logic_vector range 111 downto 0.

Hi

mod have precedence over +

I bet that 14*(i+7)+13 mod 112
is interpreted as (14*(i+7)) + (13 mod 112)
rather than (14*(i+7)+13) mod 112

Pascal

 

[mn_monkey]

On Dec 23, 9:21 am, Alain <bre...@phaethon.ch> wrote:

Hi NG
...

kind regards
Alain

When I'm doing big generates, I find it useful to write a script to
unroll the indexes and see exactly what's going on. In your case
here's some tcl code that does what your VHDL is doing :

for {set i 7} {$i >= 0} {incr i -1} {

puts "data_I_b([expr {14*($i+7)+13 % 112}] downto [expr {14*($i+7) %
112}])
data_I_b([expr {14*($i+6)+13 % 112}] downto [expr {14*($i+6) % 112}])
data_I_b([expr {14*($i+5)+13 % 112}] downto [expr {14*($i+5) % 112}])
data_I_b([expr {14*($i+4)+13 % 112}] downto [expr {14*($i+4) % 112}])
data_I_b([expr {14*($i+3)+13 % 112}] downto [expr {14*($i+3) % 112}])
data_I_b([expr {14*($i+2)+13 % 112}] downto [expr {14*($i+2) % 112}])
data_I_b([expr {14*($i+1)+13 % 112}] downto [expr {14*($i+1) % 112}])
data_I_b([expr {14*($i+0)+13 % 112}] downto [expr {14*($i+0) % 112}])"

}

This outputs :

data_I_b(209 downto 84)
data_I_b(195 downto 70)
data_I_b(181 downto 56)
data_I_b(167 downto 42)
data_I_b(153 downto 28)
data_I_b(139 downto 14)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(195 downto 70)
data_I_b(181 downto 56)
data_I_b(167 downto 42)
data_I_b(153 downto 28)
data_I_b(139 downto 14)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(181 downto 56)
data_I_b(167 downto 42)
data_I_b(153 downto 28)
data_I_b(139 downto 14)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(83 downto 70)
data_I_b(167 downto 42)
data_I_b(153 downto 28)
data_I_b(139 downto 14)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(83 downto 70)
data_I_b(69 downto 56)
data_I_b(153 downto 28)
data_I_b(139 downto 14)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(83 downto 70)
data_I_b(69 downto 56)
data_I_b(55 downto 42)
data_I_b(139 downto 14)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(83 downto 70)
data_I_b(69 downto 56)
data_I_b(55 downto 42)
data_I_b(41 downto 28)
data_I_b(125 downto 0)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(83 downto 70)
data_I_b(69 downto 56)
data_I_b(55 downto 42)
data_I_b(41 downto 28)
data_I_b(27 downto 14)
data_I_b(111 downto 98)
data_I_b(97 downto 84)
data_I_b(83 downto 70)
data_I_b(69 downto 56)
data_I_b(55 downto 42)
data_I_b(41 downto 28)
data_I_b(27 downto 14)
data_I_b(13 downto 0)

which, when &'ed together, is way more than 112 bits. I think that's
your problem.

 

[Mike Treseler]

Alain wrote:

# ** Error: D:/work/QMFLIM/FPGA/sim/../vhdl/line_buf_ctrl_fsm.vhd(184):
(vopt-1167) Index value 112 is out of
ieee.std_logic_1164.std_logic_vector range 111 downto 0.

*That* error says that the rollover bit
112 is needed in the description range.
This will not cost anything in synthesis
as long as this bit is not output to
a port.

a related example:
http://mysite.verizon.net/miketreseler/count_enable.vhd

-- Mike Treseler

 

[Alain]

thanks for this reply, solved my problem.

kind regards
Alain

Pascal Peyremorte schrieb:

Alain a écrit :
Hi NG
data_IQ_c <= data_I_b(14*(i+7)+13 mod 112 downto 14*(i+7) mod 112)&
data_I_b(14*(i+6)+13 mod 112 downto 14*(i+6) mod 112)&

[...]

(vopt-1167) Index value 112 is out of
ieee.std_logic_1164.std_logic_vector range 111 downto 0.

Hi

mod have precedence over +

I bet that 14*(i+7)+13 mod 112
is interpreted as (14*(i+7)) + (13 mod 112)
rather than (14*(i+7)+13) mod 112

Pascal