Low voltage negative resistance oscillator design, lessons l

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

What's bothering me is that about 650pA still flows in the simulation
when the bridge is in balance. That's odd, either Is is ~100pA or there
is leakage somewhere.

The model for the 2N3904 shows IS = 1e-14:

..model 2N3904 NPN(IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=
8E-12 RB=20 RC=0.1 RE=0.1 TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40
Icrating=200m mfg=NXP)

 

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet wrote:

When used with overrall feedback of course the input voltage will be
essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no effect on the
input current into the bridge

What's bothering me is that about 650pA still flows in the simulation
when the bridge is in balance. That's odd, either Is is ~100pA or there
is leakage somewhere.

 

On Saturday, September 7, 2019 at 9:01:32 PM UTC+2, Steve Wilson wrote:

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet wrote:

When used with overrall feedback of course the input voltage will be
essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no effect on the
input current into the bridge

What's bothering me is that about 650pA still flows in the simulation
when the bridge is in balance. That's odd, either Is is ~100pA or there
is leakage somewhere.

That's local feedback inside the unit. The feedback around the unit itself reduces the input error to the output voltage divided by the open-loop gain, which the datasheet says is at least 100dB. So 150uV max if you observe the supply rating (if the loop is unbroken).

The model for the 2N3904 shows IS = 1e-14:

.model 2N3904 NPN(IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE>8E-12 RB=20 RC=0.1 RE=0.1 TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40
Icrating=200m mfg=NXP)

I was wrong about the bias current I previously mentioned: that term is the peak collector current, ignoring capacitive effects (i.e. 1/gm < 1/2pifoscC). The actual current would be the difference in collector currents, so quite a bit less.
If I step the input error and run a transient analysis I get about 9fA peak for a 150uV input. I'm not sure what causes the difference in your simulation file.

 

On Saturday, September 7, 2019 at 9:52:40 PM UTC+2, j.p...@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 9:01:32 PM UTC+2, Steve Wilson wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet wrote:

When used with overrall feedback of course the input voltage will be
essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no effect on the
input current into the bridge

What's bothering me is that about 650pA still flows in the simulation
when the bridge is in balance. That's odd, either Is is ~100pA or there
is leakage somewhere.

That's local feedback inside the unit. The feedback around the unit itself reduces the input error to the output voltage divided by the open-loop gain, which the datasheet says is at least 100dB. So 150uV max if you observe the supply rating (if the loop is unbroken).

The model for the 2N3904 shows IS = 1e-14:

.model 2N3904 NPN(IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE> >8E-12 RB=20 RC=0.1 RE=0.1 TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40
Icrating=200m mfg=NXP)

I was wrong about the bias current I previously mentioned: that term is the peak collector current, ignoring capacitive effects (i.e. 1/gm < 1/2pifoscC). The actual current would be the difference in collector currents, so quite a bit less.
If I step the input error and run a transient analysis I get about 9fA peak for a 150uV input. I'm not sure what causes the difference in your simulation file.

Oops, I had forgotten the 33k resistor to ground on the transformer side of the bridge. The current now simulates as 15pA peak for a 150uV input error..

I wonder what the exact conditions for the 10fA bias current spec are, they don't give an input error or output level.

 

[Steve Wilson]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

I haven't looked at it yet, but it sounds like a riff off the usual
transformer-based differential capacitive position gauge. You can get
down to picometer displacement sensitivities if you don't mind waiting a
bit.

The patent was filed on Dec 28, 1966:

https://www.google.ca/patents/US3530390

I can't find patents related to the position gauge. The best I have is a
Wikipedia article:

https://en.wikipedia.org/wiki/Capacitive_displacement_sensor

It states the gauge can measure the position of objects down to the
nanometer level (1e-9).

The radius of a hydrogen atom is known as the Bohr Radius, which is equal
to 0.529e-10 meters.

A picometer is 1e-12 meters, or about 26.4 hydrogen atoms:

0.529e-10/1e-12 = 52.9

52.9/2 = 26.45

Pretty hard for a displacement gauge to get down to that level.

Cheers

Phil Hobbs

 

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 9:52:40 PM UTC+2,
j.p...@student.utwente.nl wrote:
On Saturday, September 7, 2019 at 9:01:32 PM UTC+2, Steve Wilson wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet wrote:

When used with overrall feedback of course the input voltage will
be
essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no
effect on the input current into the bridge

That's local feedback inside the unit. The feedback around the unit
itsel
f reduces the input error to the output voltage divided by the open-loop
ga in, which the datasheet says is at least 100dB. So 150uV max if you
observe the supply rating (if the loop is unbroken).

There is no global feedback shown on your schematic. How is that arranged?

I have to admit I can't make heads or tails of your hand drawn schematic.
The top portion is darkened, so you can't tell where the links go.

[...]

Oops, I had forgotten the 33k resistor to ground on the transformer side
of the bridge. The current now simulates as 15pA peak for a 150uV input
error.

I wish you could show that in a LTspice file. I have no idea where you want
the resistor.

I wonder what the exact conditions for the 10fA bias current spec are,
they don't give an input error or output level.

 

On Saturday, September 7, 2019 at 10:40:55 PM UTC+2, Steve Wilson wrote:

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 9:52:40 PM UTC+2,
j.p...@student.utwente.nl wrote:
On Saturday, September 7, 2019 at 9:01:32 PM UTC+2, Steve Wilson wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet wrote:

When used with overrall feedback of course the input voltage will
be
essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no
effect on the input current into the bridge

That's local feedback inside the unit. The feedback around the unit
itsel
f reduces the input error to the output voltage divided by the open-loop
ga in, which the datasheet says is at least 100dB. So 150uV max if you
observe the supply rating (if the loop is unbroken).

There is no global feedback shown on your schematic. How is that arranged?

It is applied by the customer :^)

I have to admit I can't make heads or tails of your hand drawn schematic.
The top portion is darkened, so you can't tell where the links go.

[...]

I'll admit it's quite bad, but I can follow the links plenty fine.
No matter, I've added an updated version of the digitally drawn schematic, you can find it here: https://imgur.com/pgaSDUd
It looks black in firefox for me, someone confirmed it was the same for them in chrome, you have to click it to see the image.

Oops, I had forgotten the 33k resistor to ground on the transformer side
of the bridge. The current now simulates as 15pA peak for a 150uV input
error.

I wish you could show that in a LTspice file. I have no idea where you want
the resistor.

I wonder what the exact conditions for the 10fA bias current spec are,
they don't give an input error or output level.

It's the same resistor you already put in, I had forgotten to add it in my simulation. Here is my file with the transient simulation and stepped (not temporally sweeped) input offset.

Version 4
SHEET 1 1204 680
WIRE 432 -16 352 -16
WIRE 608 -16 432 -16
WIRE 432 16 432 -16
WIRE 608 16 608 -16
WIRE 352 64 352 -16
WIRE 368 64 352 64
WIRE 144 160 96 160
WIRE 208 160 144 160
WIRE 352 160 288 160
WIRE 432 160 432 112
WIRE 432 160 352 160
WIRE 608 160 608 96
WIRE 704 160 608 160
WIRE 736 160 704 160
WIRE 816 160 736 160
WIRE 736 176 736 160
WIRE 96 192 96 160
WIRE 432 208 432 160
WIRE 608 224 608 160
WIRE 352 256 352 160
WIRE 368 256 352 256
WIRE 736 256 736 240
WIRE 816 256 816 240
WIRE 96 288 96 272
WIRE 432 320 432 304
WIRE 512 320 432 320
WIRE 608 320 608 304
WIRE 608 320 512 320
FLAG 512 320 Q2E
FLAG 96 288 0
FLAG 144 160 Vin
FLAG 736 256 0
FLAG 704 160 R2C1
FLAG 816 256 0
SYMBOL res 304 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL voltage 608 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 25m 200k)
SYMBOL voltage 96 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value {Vin}
SYMBOL cap 720 176 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage 608 208 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 25m 200k)
SYMBOL npn 368 208 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL npn 368 16 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 800 144 R0
SYMATTR InstName R2
SYMATTR Value 33k
TEXT 408 -104 Left 2 !.step param Vin -0.2 0.2 10m\n.tran 1m
TEXT 408 -136 Left 2 ;'AD310 Bipolar Bridge

 

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 10:40:55 PM UTC+2, Steve Wilson wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 9:52:40 PM UTC+2,
j.p...@student.utwente.nl wrote:
On Saturday, September 7, 2019 at 9:01:32 PM UTC+2, Steve Wilson
wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet
wrote:

When used with overrall feedback of course the input voltage
will be essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no
effect on the input current into the bridge

That's local feedback inside the unit. The feedback around the unit
itsel
f reduces the input error to the output voltage divided by the
open-loop ga in, which the datasheet says is at least 100dB. So 150uV
max if you observe the supply rating (if the loop is unbroken).

There is no global feedback shown on your schematic. How is that
arranged?

It is applied by the customer :^)

I thought you were joking, but that's exacty what the datasheet shows.

One thing that bothers me is the very high values of resistors required at
the inputs. With nA levels of current required to drive the bridge, I
wonder if there would be severe attenuation of the signal.

I have to admit I can't make heads or tails of your hand drawn
schematic. The top portion is darkened, so you can't tell where the
links go.

[...]

I'll admit it's quite bad, but I can follow the links plenty fine.
No matter, I've added an updated version of the digitally drawn
schematic, you can find it here: https://imgur.com/pgaSDUd It looks
black in firefox for me, someone confirmed it was the same for them in
chrome, you have to click it to see the image.

It downloads as a PNG file, also black. I used FastStone Photo Resizer to
convert it to JPG. Now it's clear with a white background.

https://www.faststone.org/

Oops, I had forgotten the 33k resistor to ground on the transformer
side of the bridge. The current now simulates as 15pA peak for a
150uV input error.

I wish you could show that in a LTspice file. I have no idea where you
want the resistor.

I wonder what the exact conditions for the 10fA bias current spec
are, they don't give an input error or output level.

They spec it as max.

It's the same resistor you already put in, I had forgotten to add it in
my simulation. Here is my file with the transient simulation and stepped
(not temporally sweeped) input offset.

Your sim shows zero offset at zero volts. Does that fix the 650nA you were
talking about?

[...]

Thanks

 

On Saturday, September 7, 2019 at 11:38:15 PM UTC+2, Steve Wilson wrote:

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 10:40:55 PM UTC+2, Steve Wilson wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 9:52:40 PM UTC+2,
j.p...@student.utwente.nl wrote:
On Saturday, September 7, 2019 at 9:01:32 PM UTC+2, Steve Wilson
wrote:
j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 5:40:05 PM UTC+2, piglet
wrote:

When used with overrall feedback of course the input voltage
will be essentially zero.

piglet

Yes that's a crucial point.

How? The feedback is to the source of the input jfet. It has no
effect on the input current into the bridge

That's local feedback inside the unit. The feedback around the unit
itsel
f reduces the input error to the output voltage divided by the
open-loop ga in, which the datasheet says is at least 100dB. So 150uV
max if you observe the supply rating (if the loop is unbroken).

There is no global feedback shown on your schematic. How is that
arranged?

It is applied by the customer :^)

I thought you were joking, but that's exacty what the datasheet shows.

Yes, the whole thing is just an exotic opamp.

One thing that bothers me is the very high values of resistors required at
the inputs. With nA levels of current required to drive the bridge, I
wonder if there would be severe attenuation of the signal.

Maybe at first when the error is still large. According to the specs in the datasheet it will settle to at most 150uV w.r.t. to the balanced condition, as per my previous post.

I have to admit I can't make heads or tails of your hand drawn
schematic. The top portion is darkened, so you can't tell where the
links go.

[...]

I'll admit it's quite bad, but I can follow the links plenty fine.
No matter, I've added an updated version of the digitally drawn
schematic, you can find it here: https://imgur.com/pgaSDUd It looks
black in firefox for me, someone confirmed it was the same for them in
chrome, you have to click it to see the image.

It downloads as a PNG file, also black. I used FastStone Photo Resizer to
convert it to JPG. Now it's clear with a white background.

https://www.faststone.org/

Oops, I had forgotten the 33k resistor to ground on the transformer
side of the bridge. The current now simulates as 15pA peak for a
150uV input error.

I wish you could show that in a LTspice file. I have no idea where you
want the resistor.

I wonder what the exact conditions for the 10fA bias current spec
are, they don't give an input error or output level.

They spec it as max.

Yes but under what condition? I doubt the current will stay below 10fA if I apply 1kV to the input.

It's the same resistor you already put in, I had forgotten to add it in
my simulation. Here is my file with the transient simulation and stepped
(not temporally sweeped) input offset.

Your sim shows zero offset at zero volts. Does that fix the 650nA you were
talking about?

The highish current at 0 input voltage in your sim is because of storage. Notice that it changes depending on how high the edges of the voltage sweep are (0.6pA for a -200uV to 200uV input voltage sweep).
In my simulation the input voltage doesn't change during the transient simulation. If you set the input voltage to 150uV DC you'll find the 15pA I mentioned earlier.

Still, I strongly question the accuracy of the simulation regarding the transistor beta behavior, the collector current is about 1/1000th of the base current.

Thanks

 

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

On Saturday, September 7, 2019 at 11:38:15 PM UTC+2, Steve Wilson wrote:
I wonder what the exact conditions for the 10fA bias current spec
are, they don't give an input error or output level.

They spec it as max.

Yes but under what condition? I doubt the current will stay below 10fA
if I apply 1kV to the input.

The Max Safe Differential Voltage is spec'd at ą300V

It's the same resistor you already put in, I had forgotten to add it
in my simulation. Here is my file with the transient simulation and
stepped (not temporally sweeped) input offset.

Your sim shows zero offset at zero volts. Does that fix the 650nA you
were talking about?

The highish current at 0 input voltage in your sim is because of
storage. Notice that it changes depending on how high the edges of the
voltage sweep are (0.6pA for a -200uV to 200uV input voltage sweep). In
my simulation the input voltage doesn't change during the transient
simulation. If you set the input voltage to 150uV DC you'll find the
15pA I mentioned earlier.

I get a differentiated square wave centered on -5pA. This makes me question
even more the operation with hundreds of megohms in global feedback. How
can they pass the sharp edges?

Still, I strongly question the accuracy of the simulation regarding the
transistor beta behavior, the collector current is about 1/1000th of the
base current.

I have had problems measuring the base current in other simulations.

The emitter current looks even weirder. Pulses instead of square waves.

It looks like the differentiated version of the square wave applied to the
collector-base junction. So capacitance defilitely plays a part in the
results. Maybe that helps explain the large base current you see.

 

[Steve Wilson]

Steve Wilson <no@spam.com> wrote:

Steve Wilson <no@spam.com> wrote:

j.ponte@student.utwente.nl wrote:
Still, I strongly question the accuracy of the simulation regarding
the transistor beta behavior, the collector current is about 1/1000th
of the base current.

The base current is the differentiated version of the square wave
applied to collector-base flowing through the base-emitter junction
capacitance.

The collector current is less because the collector is tied to the base so
there is no voltage applied to the collector-base junction.

 

[Steve Wilson]

Steve Wilson <no@spam.com> wrote:

j.ponte@student.utwente.nl wrote:
Still, I strongly question the accuracy of the simulation regarding the
transistor beta behavior, the collector current is about 1/1000th of
the base current.

The base current is the differentiated version of the square wave applied to
collector-base flowing through the base-emitter junction capacitance.

The collector current is less because presumably the collector-base junction
capacitance is less than the base-emitter junction capacitance.

 

[Phil Hobbs]

On 9/7/19 4:19 PM, Steve Wilson wrote:

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

I haven't looked at it yet, but it sounds like a riff off the usual
transformer-based differential capacitive position gauge. You can get
down to picometer displacement sensitivities if you don't mind waiting a
bit.

The patent was filed on Dec 28, 1966:

https://www.google.ca/patents/US3530390

I can't find patents related to the position gauge. The best I have is a
Wikipedia article:

snip

> Pretty hard for a displacement gauge to get down to that level.

It's commonly done to a few tens of picometers in the automatic
compensation systems for deep-UV and EUV wafer scanners. They use a
combination of interferometry and capacitive gauges.

Good transmission-line transformers can get down to accuracies of 1E-7
fairly routinely, which with a full-scale range of 0.5 mm gets you down
to that level.

Cheers

Phil Hobbs

(Coming to you from sunny Lisbon)


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

On 9/8/19 5:59 AM, Steve Wilson wrote:

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

On 9/7/19 4:19 PM, Steve Wilson wrote:
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

I haven't looked at it yet, but it sounds like a riff off the usual
transformer-based differential capacitive position gauge. You can get
down to picometer displacement sensitivities if you don't mind waiting
a
bit.

Pretty hard for a displacement gauge to get down to that level.

It's commonly done to a few tens of picometers in the automatic
compensation systems for deep-UV and EUV wafer scanners. They use a
combination of interferometry and capacitive gauges.

Good transmission-line transformers can get down to accuracies of 1E-7
fairly routinely, which with a full-scale range of 0.5 mm gets you down
to that level.

1e-7 <> 1e-12

You're just being thick.

1e-7 * 5e-4 = 5e-11.

A scanner making 5-nm features needs 50-pm adjustment granularity. YCLIU.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Steve Wilson]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

On 9/7/19 4:19 PM, Steve Wilson wrote:
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

I haven't looked at it yet, but it sounds like a riff off the usual
transformer-based differential capacitive position gauge. You can get
down to picometer displacement sensitivities if you don't mind waiting
a
bit.

Pretty hard for a displacement gauge to get down to that level.

It's commonly done to a few tens of picometers in the automatic
compensation systems for deep-UV and EUV wafer scanners. They use a
combination of interferometry and capacitive gauges.

Good transmission-line transformers can get down to accuracies of 1E-7
fairly routinely, which with a full-scale range of 0.5 mm gets you down
to that level.

1e-7 <> 1e-12

Cheers

Phil Hobbs

(Coming to you from sunny Lisbon)

 

On Sunday, September 8, 2019 at 8:08:31 AM UTC+2, Steve Wilson wrote:

Steve Wilson <no@spam.com> wrote:

j.ponte@student.utwente.nl wrote:
Still, I strongly question the accuracy of the simulation regarding the
transistor beta behavior, the collector current is about 1/1000th of
the base current.

The base current is the differentiated version of the square wave applied to
collector-base flowing through the base-emitter junction capacitance.

The collector current is less because presumably the collector-base junction
capacitance is less than the base-emitter junction capacitance.

I think you're right about the capacitance, I had overestimated its impedance. The model says CJE is 8pF, which roughly matches the current we're seeing.

>The Max Safe Differential Voltage is spec'd at ą300V

I don't think ~300V across 4.2MOhm would yield 10fA My 1kV was being hyperbolic.

 

[Steve Wilson]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

On 9/8/19 5:59 AM, Steve Wilson wrote:
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

On 9/7/19 4:19 PM, Steve Wilson wrote:
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

I haven't looked at it yet, but it sounds like a riff off the usual
transformer-based differential capacitive position gauge. You can
get down to picometer displacement sensitivities if you don't mind
waiting a bit.

Pretty hard for a displacement gauge to get down to that level.

It's commonly done to a few tens of picometers in the automatic
compensation systems for deep-UV and EUV wafer scanners. They use a
combination of interferometry and capacitive gauges.

Good transmission-line transformers can get down to accuracies of 1E-7
fairly routinely, which with a full-scale range of 0.5 mm gets you
down to that level.

1e-7 <> 1e-12

You're just being thick.

1e-7 * 5e-4 = 5e-11.

A scanner making 5-nm features needs 50-pm adjustment granularity.
YCLIU.

You stated:

"They use a combination of interferometry and capacitive gauges."

and

"Good transmission-line transformers can get down to accuracies of 1E-7"

I read that to understand the capacitive gauge would get it down to 1e-7,
or 100nm, and interferometry would take it the rest of the way.

Enjoy Lisbon. I understand it is a friendly city.

Boy, you are going to have some case of jet lag when you decide to come
home

Cheers

Phil Hobbs

 

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

On Sunday, September 8, 2019 at 8:08:31 AM UTC+2, Steve Wilson wrote:
Steve Wilson <no@spam.com> wrote:

j.ponte@student.utwente.nl wrote:
Still, I strongly question the accuracy of the simulation regarding
th e transistor beta behavior, the collector current is about
1/1000th of the base current.

The base current is the differentiated version of the square wave
applied to collector-base flowing through the base-emitter junction
capacitance.

The collector current is less because presumably the collector-base
junction capacitance is less than the base-emitter junction
capacitance.

I think you're right about the capacitance, I had overestimated its
impedance. The model says CJE is 8pF, which roughly matches the current
we're seeing.

My later post corrected this. The collector current is so low because it is
shorted to the base. There is no voltage across the collector-base junction
that would allow current to flow.

The Max Safe Differential Voltage is spec'd at +/-300V

I don't think ~300V across 4.2MOhm would yield 10fA

Where'd you get 4.2MOhm? I thought the 100dB of feedback would bring the
input impedance up to 10^14 Ohms.

 

On Sunday, September 8, 2019 at 1:50:40 PM UTC+2, Steve Wilson wrote:

j.ponte@student.utwente.nl wrote:

On Sunday, September 8, 2019 at 8:08:31 AM UTC+2, Steve Wilson wrote:
Steve Wilson <no@spam.com> wrote:

j.ponte@student.utwente.nl wrote:
Still, I strongly question the accuracy of the simulation regarding
th e transistor beta behavior, the collector current is about
1/1000th of the base current.

The base current is the differentiated version of the square wave
applied to collector-base flowing through the base-emitter junction
capacitance.

The collector current is less because presumably the collector-base
junction capacitance is less than the base-emitter junction
capacitance.

I think you're right about the capacitance, I had overestimated its
impedance. The model says CJE is 8pF, which roughly matches the current
we're seeing.

My later post corrected this. The collector current is so low because it is
shorted to the base. There is no voltage across the collector-base junction
that would allow current to flow.

The Max Safe Differential Voltage is spec'd at +/-300V

I don't think ~300V across 4.2MOhm would yield 10fA

Where'd you get 4.2MOhm? I thought the 100dB of feedback would bring the
input impedance up to 10^14 Ohms.

Nothing in the datasheet specifies feedback being applied, or anything for that matter, other than the temperature being 25C.
The 4.2MOhm is just the resistance in the path between the inverting and non-inverting inputs (it's actually 3.9Meg + 33k or something, not really relevant).

 

[Steve Wilson]

j.ponte@student.utwente.nl wrote:

Analog is absolutely my hobby and career path. I've read/scanned the
book, I liked it quite a lot.

If you like analog, you might also like oscillators. I have written an
article that gives detailed instructions on how to design Colpitts, Clap and
Pierce oscillators along with examples. (Pierce is the same as common-
collector Colpitts.)

It also shows how to speed up simulation of oscillators with high-Q tanks
such as crystal oscillators. The link is:

Oscillators.zip
https://drive.google.com/open?id=1ZsbpkV0aaKS5LURIb1dfu_ndshsSaYtf