How do I concatenate registers ?

[Daku]

Could some Verilog guru please help me ? I am stumped trying to
concatenate registers and not having much success.
I have:
`define A_W 8
`define B_W 8
`define C_W 8
`define MSB 23
`define LSB 0
.......
.......
reg [`A_W-1 : 0] ar;
reg [`B_W-1 : 0] br;
reg [`C_W-1 : 0] cr;
reg [`MSB : `LSB] rr;

Is there a way to concatenate ar. br and cr ? My goal is to be able to
set/reset 8 bit segments of
rr as per different conditions. Is there any way to
achieve this ? Any hints, suggestions or help would be greatly
appreciated.

 

[pallav]

On Oct 21, 11:01 pm, Daku <dakup...@gmail.com> wrote:

Could some Verilog guru please help me ? I am stumped trying to
concatenate registers and not having much success.
I have:
`define A_W 8
`define B_W 8
`define C_W 8
`define MSB 23
`define LSB 0
......
......
reg [`A_W-1 : 0] ar;
reg [`B_W-1 : 0] br;
reg [`C_W-1 : 0] cr;
reg [`MSB : `LSB] rr;

Is there a way to concatenate ar. br and cr ? My goal is to be able to
set/reset 8 bit segments of
rr as per different conditions. Is there any way to
achieve this ? Any hints, suggestions or help would be greatly
appreciated.

First off, I think you are using some very crypt ways to declare your
registers.
I think it is better to say the following:

module test;

parameter WIDTH = 8;
parameter TRIPLE_WIDTH = 24;

reg[WIDTH-1:0] ar, br, cr;
reg[TRIPLE_WIDTH-1:0] rr;

....
endmodule

Keeping the parameter definition within the module doesn't pollute the
global namespace.

To concatenate, assign rr[TRIPLE_WIDTH-1:0] = {ar[WIDTH-1:0], br
[WIDTH-1:0], cr[WIDTH-1:0]}.

You can get away with saying assign rr = {ar, br, cr} but it can
easily lead to errors with
different bits widths etc, so its better to be explicit.

I don't understand what set/reset has to do with concatenation....

A good verilog reference for operators:
http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html

 

[pallav]

Should have pointed to the newer 2001 reference:

http://www.sutherland-hdl.com/reference-guides.php

 

[Daku]

Thanks a lot. That was really very helpful.

On Oct 22, 8:42 am, pallav <pallavgu...@gmail.com> wrote:

On Oct 21, 11:01 pm, Daku <dakup...@gmail.com> wrote:



Could some Verilog guru please help me ? I am stumped trying to
concatenate registers and not having much success.
I have:
`define A_W 8
`define B_W 8
`define C_W 8
`define MSB 23
`define LSB 0
......
......
reg [`A_W-1 : 0] ar;
reg [`B_W-1 : 0] br;
reg [`C_W-1 : 0] cr;
reg [`MSB : `LSB] rr;

Is there a way to concatenate ar. br and cr ? My goal is to be able to
set/reset 8 bit segments of
rr as per different conditions. Is there any way to
achieve this ? Any hints, suggestions or help would be greatly
appreciated.

First off, I think you are using some very crypt ways to declare your
registers.
I think it is better to say the following:

module test;

parameter WIDTH = 8;
parameter TRIPLE_WIDTH = 24;

reg[WIDTH-1:0] ar, br, cr;
reg[TRIPLE_WIDTH-1:0] rr;

...
endmodule

Keeping the parameter definition within the module doesn't pollute the
global namespace.

To concatenate, assign rr[TRIPLE_WIDTH-1:0] = {ar[WIDTH-1:0], br
[WIDTH-1:0], cr[WIDTH-1:0]}.

You can get away with saying assign rr = {ar, br, cr} but it can
easily lead to errors with
different bits widths etc, so its better to be explicit.

I don't understand what set/reset has to do with concatenation....

A good verilog reference for operators:http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html