D
Daku
Guest
Could some Verilog guru please help me ? I am stumped trying to
concatenate registers and not having much success.
I have:
`define A_W 8
`define B_W 8
`define C_W 8
`define MSB 23
`define LSB 0
.......
.......
reg [`A_W-1 : 0] ar;
reg [`B_W-1 : 0] br;
reg [`C_W-1 : 0] cr;
reg [`MSB : `LSB] rr;
Is there a way to concatenate ar. br and cr ? My goal is to be able to
set/reset 8 bit segments of
rr as per different conditions. Is there any way to
achieve this ? Any hints, suggestions or help would be greatly
appreciated.
concatenate registers and not having much success.
I have:
`define A_W 8
`define B_W 8
`define C_W 8
`define MSB 23
`define LSB 0
.......
.......
reg [`A_W-1 : 0] ar;
reg [`B_W-1 : 0] br;
reg [`C_W-1 : 0] cr;
reg [`MSB : `LSB] rr;
Is there a way to concatenate ar. br and cr ? My goal is to be able to
set/reset 8 bit segments of
rr as per different conditions. Is there any way to
achieve this ? Any hints, suggestions or help would be greatly
appreciated.