Help with high input impedance amp....

[Fred Bloggs]

On Sunday, November 6, 2022 at 9:22:33 AM UTC-5, Lamont Cranston wrote:

On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote:
On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30kΩ not 500MΩ, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek
You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.
I installed a small cap right at the drain to ground, no change.
I\'m posting a picture of the PCB, to learn, not for harassment. Tempted to shrink the the picture, but no.
Note: I have changed semi conductors about 6 times.
https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0
I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8.
My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10MΩ meter impedance.)
This doesn\'t have much effect on Gain.
Mikek

Okay I was afraid of that. It\'s intrinsic to your FET/ construction, assuming your signal source is 50R or even remotely close. Looking at your circuit board, it looks like you may have significant coupling capacitance shunts to ac ground all over the place. The most damaging ones will be at high impedance nodes. That will do it.

 

[Fred Bloggs]

On Sunday, November 6, 2022 at 9:22:33 AM UTC-5, Lamont Cranston wrote:

On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote:
On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30kΩ not 500MΩ, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek
You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.
I installed a small cap right at the drain to ground, no change.
I\'m posting a picture of the PCB, to learn, not for harassment. Tempted to shrink the the picture, but no.
Note: I have changed semi conductors about 6 times.
https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0
I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8.
My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10MΩ meter impedance.)
This doesn\'t have much effect on Gain.
Mikek

You might consider re-doing the board. Use all leaded components. Keep about 100 mils clearance from every node to any of the power planes, keep the body of the components 100 mils up and away from the planes too. This should not present a problem at your frequency. Main thing is to eliminate stray shunts and couplings you have all over the place.

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 8:40:27 AM UTC-6, erichp...@hotmail.com wrote:

Thanks for the PCB photo - you said you determine input impedance by
adding series resistors, I cannot see them in the photo, where do you
place them?

piglet

I only did it as a test, I didn\'t leave them in.
Mikek

 

[John Larkin]

On Sun, 6 Nov 2022 03:10:40 -0800 (PST), Lamont Cranston
<amdx62@gmail.com> wrote:

On Saturday, November 5, 2022 at 11:22:27 PM UTC-5, John Larkin wrote:


Is the fet connected right?

I always write the pin out on the bag, so, I verified I wrote it correctly from a data sheet (3). I then rechecked the mounting on the pcb.
I have it right according to the data sheets. Although my cheap Chinese Tester reads out the Drain and Source reversed from the datasheet.
Mikek

If you swap source and drain on most jfets, it still acts like a jfet
but behaves really strangely. I wouldn\'t trust the CCT.

Other pin swaps can turn it into a diode, which would sure wreck Zin.
Your voltages suggest that\'s not happening here.

Most jfets develop a lot of gate current if the drain voltage goes
above, say, 5 volts. It\'s called \"hot carrier injection\" or something.
AoE mentions that effect and has some graphs.

I assume that you personally measured the voltages on the schematic.

Is the 16u cap an electrolytic?

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 8:50:16 AM UTC-6, erichp...@hotmail.com wrote:

BTW you really shouldn\'t need that huge tantalum bead input capacitor,
with a hi-z input in the tens kilohoms even 1nF would still be good down
to 10-20kHz. Tants have leakage and with the high DC impedance a few
hundred nA cap leakage will be significant. I don\'t see how cap leakage
could explain the phenomenon you see but it is a complication you can do
without?

piglet

I added that tantalum later because I had a capacitive divider with the original 27pf and gate capacitance.
I just wanted the same voltage on the input as the gate. If/when I get it to operate the way I want,
I will be putting a capacitive divider on it as it will go on a resonant LC circuit with a greatly magnified voltage.
Mikek

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 8:56:48 AM UTC-6, erichp...@hotmail.com wrote:

Speaking of caps - how big is the output cap? The schematic you posted
showed it as 0.1nF (which is 100pF) and seems way too small for a low-Z
output. I\'d suggest 0.1uF (100nF) as better and that looks like what you
did in the PCB photo?

piglet

It is a 0.1uf (104), no signal loss measuring on either side of that cap.
Mikek

 

[John Larkin]

On Sun, 6 Nov 2022 13:32:33 +0200, Dimiter_Popoff <dp@tgi-sci.com>
wrote:

On 11/6/2022 2:59, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30k? not 500M?, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek



For the low input impedance I would suspect that the FET you use
turns up forward biased gate-source, can\'t think of another
explanation if the FET is healthy etc.

Idss is 3 mA min on that fet, if it\'s good, so the gate shouldn\'t be
forward biased.

Who is Dagmar?

 

[John Larkin]

On Sun, 6 Nov 2022 05:22:20 -0800 (PST), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30k? not 500M?, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek

You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.

There is no LF rolloff.

The real problem is that the fet resents being called a T when it
knows it\'s a Q. It\'s a status thing.

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 9:16:28 AM UTC-6, John Larkin wrote:

I assume that you personally measured the voltages on the schematic.

Is the 16u cap an electrolytic?

Yes, I measured the dc voltages posted.
Not sure where 16u comes from the only big cap I have is the 22uf tantalum on the input,
and as discussed that is not need, I added that to stop the capacitive voltage divider affect of the
original 27pf and the gate capacitance.
B+ bap is a 104, then I added 180pf right at the drain/collector of the semis. No Change.
Mikek

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 9:21:35 AM UTC-6, John Larkin wrote:

For the low input impedance I would suspect that the FET you use
turns up forward biased gate-source, can\'t think of another
explanation if the FET is healthy etc.
Idss is 3 mA min on that fet, if it\'s good, so the gate shouldn\'t be
forward biased.

Forward biased, meaning more voltage on the Gate than source? I don\'t have that.
2.4V gate and 6.5V source.

Who is Dagmar?

He was a pretty heavy contributor here for quite awhile, he posted this 5 years ago, I have seen any posts from him
for a long time.
Mikek

 

[John Larkin]

On Sun, 6 Nov 2022 06:22:29 -0800 (PST), Lamont Cranston
<amdx62@gmail.com> wrote:

On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote:
On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30k? not 500M?, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek
You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.

I installed a small cap right at the drain to ground, no change.
I\'m posting a picture of the PCB, to learn, not for harassment. Tempted to shrink the the picture, but no.
Note: I have changed semi conductors about 6 times.
https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0
I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8.
My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10M? meter impedance.)
This doesn\'t have much effect on Gain.
Mikek

Looking at your board and the Onsemi data sheet, it looks like the
input signal is connected to the drain. You might check me on that.

Your scope probe is connected after that final RC, not to node C. That
will trash LF gain.

 

[piglet]

On 06/11/2022 15:15, John Larkin wrote:

Most jfets develop a lot of gate current if the drain voltage goes
above, say, 5 volts. It\'s called \"hot carrier injection\" or something.
AoE mentions that effect and has some graphs.

Is that \"impact ionization\"? Worsens gate current from pA to nA or
something? Could be happening here, OP could add a series resistor in
drain to drop D-S voltage below 5, can then try bypassing drain to
ground or bootstrapping it from emitter too. Tons of solder-smoke fun!

piglet

 

[piglet]

On 06/11/2022 15:21, John Larkin wrote:

Who is Dagmar?

Wasn\'t that James Arthur?

piglet

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 10:34:23 AM UTC-6, erichp...@hotmail.com wrote:

On 06/11/2022 15:21, John Larkin wrote:
Who is Dagmar?


Wasn\'t that James Arthur?

piglet

I think that is right.
Mikek

 

[piglet]

On 06/11/2022 15:03, Fred Bloggs wrote:

On Sunday, November 6, 2022 at 9:22:33 AM UTC-5, Lamont Cranston wrote:
On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote:
On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30kΩ not 500MΩ, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek
You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.
I installed a small cap right at the drain to ground, no change.
I\'m posting a picture of the PCB, to learn, not for harassment. Tempted to shrink the the picture, but no.
Note: I have changed semi conductors about 6 times.
https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0
I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8.
My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10MΩ meter impedance.)
This doesn\'t have much effect on Gain.
Mikek

Okay I was afraid of that. It\'s intrinsic to your FET/ construction, assuming your signal source is 50R or even remotely close. Looking at your circuit board, it looks like you may have significant coupling capacitance shunts to ac ground all over the place. The most damaging ones will be at high impedance nodes. That will do it.

Good point. If the pcb is double sided with vast ground plane then the
strays to ground might explain all. Perhaps Lamont/Mikek can try peeling
off a section of groundplane under the gate nodes and measure if there
is an improvement.

piglet

 

[John Larkin]

On Sun, 6 Nov 2022 07:32:42 -0800 (PST), Lamont Cranston
<amdx62@gmail.com> wrote:

On Sunday, November 6, 2022 at 9:21:35 AM UTC-6, John Larkin wrote:


For the low input impedance I would suspect that the FET you use
turns up forward biased gate-source, can\'t think of another
explanation if the FET is healthy etc.
Idss is 3 mA min on that fet, if it\'s good, so the gate shouldn\'t be
forward biased.

Forward biased, meaning more voltage on the Gate than source? I don\'t have that.
2.4V gate and 6.5V source.


Who is Dagmar?
He was a pretty heavy contributor here for quite awhile, he posted this 5 years ago, I have seen any posts from him
for a long time.
Mikek

Oh, that\'s my friend James. He skis in short pants.

I all the idiotic flaming and OT nastiness here drove him away.

 

[Lamont Cranston]

On Sunday, November 6, 2022 at 10:56:09 AM UTC-6, erichp...@hotmail.com wrote:

On 06/11/2022 15:03, Fred Bloggs wrote:

Okay I was afraid of that. It\'s intrinsic to your FET/ construction, assuming your signal source is 50R or even remotely close. Looking at your circuit board, it looks like you may have significant coupling capacitance shunts to ac ground all over the place. The most damaging ones will be at high impedance nodes. That will do it.
Good point. If the pcb is double sided with vast ground plane then the
strays to ground might explain all. Perhaps Lamont/Mikek can try peeling
off a section of groundplane under the gate nodes and measure if there
is an improvement.

piglet

The goal here is a high input impedance circuit flat from 50kHz to 30MHz.
I\'m willing to make another board, should I just remove all the copper and have a positive and ground rail on either side.
I can superglue islands for the connection points. I punch and cut islands from Rogers 5880 1/16\" teflon PCB and glue
it to the pcb. Or I can Dremel another board.
Should I use leaded components and space them off the board or just remove all the groundplane and stick with the surface mount resistors?
That\'s all I have, not smd caps or semiconductors.

Also, is this a better circuit to try, this one is tried and proven, I think it is out of Linear\'s databook or some other company.
https://www.dropbox.com/s/6n78s84gd9kaouu/High%20impedance%20input%20-%20Copy.jpg?dl=0
With the limitation of the parts I have BF256C, J310, 2N3819 2N5485 >> MPSH10, 2N3866, 2n4401, BC549.
Mikek

 

[John Larkin]

On Sun, 6 Nov 2022 16:31:12 +0000, piglet <erichpwagner@hotmail.com>
wrote:

On 06/11/2022 15:15, John Larkin wrote:
Most jfets develop a lot of gate current if the drain voltage goes
above, say, 5 volts. It\'s called \"hot carrier injection\" or something.
AoE mentions that effect and has some graphs.


Is that \"impact ionization\"?

Yeah, that\'s it.

Worsens gate current from pA to nA or
>something?

Microamps!

Could be happening here, OP could add a series resistor in

drain to drop D-S voltage below 5, can then try bypassing drain to
ground or bootstrapping it from emitter too. Tons of solder-smoke fun!

piglet

 

[John Larkin]

On Sun, 6 Nov 2022 07:09:58 -0800 (PST), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

On Sunday, November 6, 2022 at 9:22:33 AM UTC-5, Lamont Cranston wrote:
On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote:
On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30k? not 500M?, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek
You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.
I installed a small cap right at the drain to ground, no change.
I\'m posting a picture of the PCB, to learn, not for harassment. Tempted to shrink the the picture, but no.
Note: I have changed semi conductors about 6 times.
https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0
I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8.
My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10M? meter impedance.)
This doesn\'t have much effect on Gain.
Mikek

You might consider re-doing the board. Use all leaded components. Keep about 100 mils clearance from every node to any of the power planes, keep the body of the components 100 mils up and away from the planes too. This should not present a problem at your frequency. Main thing is to eliminate stray shunts and couplings you have all over the place.

You can do impedance-matched GHz circuits on dremeled copperclad with
surface-mount parts.

 

[John Larkin]

On Sun, 6 Nov 2022 16:56:02 +0000, piglet <erichpwagner@hotmail.com>
wrote:

On 06/11/2022 15:03, Fred Bloggs wrote:
On Sunday, November 6, 2022 at 9:22:33 AM UTC-5, Lamont Cranston wrote:
On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote:
On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote:
Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30k? not 500M?, and it rolls of way to early.
I may have created the problems, I don\'t have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance.
https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0
Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz?
Mikek
You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That\'s only way to explain the combination low input impedance and low frequency gain rolloff. If you can\'t do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there.
I installed a small cap right at the drain to ground, no change.
I\'m posting a picture of the PCB, to learn, not for harassment. Tempted to shrink the the picture, but no.
Note: I have changed semi conductors about 6 times.
https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0
I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8.
My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10M? meter impedance.)
This doesn\'t have much effect on Gain.
Mikek

Okay I was afraid of that. It\'s intrinsic to your FET/ construction, assuming your signal source is 50R or even remotely close. Looking at your circuit board, it looks like you may have significant coupling capacitance shunts to ac ground all over the place. The most damaging ones will be at high impedance nodes. That will do it.

Good point. If the pcb is double sided with vast ground plane then the
strays to ground might explain all. Perhaps Lamont/Mikek can try peeling
off a section of groundplane under the gate nodes and measure if there
is an improvement.

piglet

At 30 MHz, capacitance to the backside copper won\'t matter. At a
couple GHz, trace impedances might matter some.

It might benefit from vias from top to bottom ground. I like 2-56
screws, which are good ground lugs too.