GreenPAK speed test...

[Lasse Langwadt Christensen]

søndag den 30. august 2020 kl. 07.23.33 UTC+2 skrev Ricketty C:

On Saturday, August 29, 2020 at 10:25:18 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 01.58.15 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:50:46 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.39.05 UTC+2 skrev boB:
On Sat, 29 Aug 2020 14:27:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla....@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf


How fast will that FPGA programmed as an ARM Cortex M3 run and how
much will it cost ? Seems to me that a 20,000+ LUT FPGA is not
going to be cheap ? Compared to just buying an ARM processor of the
same complexity at least.

yeh you have to have some special need to put it in the fpga when you
can buy an MCU with more memory and preformance for a fraction of the price

I don\'t know why people get this backwards so often. You must have a special need to want a processor when you have a perfectly good FPGA.

and vice versa


Actually, an FPGA contains many, many tiny multiplexers connecting many, many tiny bits of RAM in contrast to a processor which has the power of the humongous multiplexer manipulating very large blocks of RAM and Flash. So the processor has to run very, very fast to create virtual connections between the many portions of memory. The FPGA in contrast has wires connected by routing FETs that can be used to connect the tiny multiplexers and bits of RAM as selected by the multiplexers.

While the processor can do many slow tasks by switching between them with its humongous multiplexer selecting which task to emulate now, the FPGA is actually processing each task in parallel using much simpler resources for each task, fast or slow, it doesn\'t care.


sure, but do you want to write something like a UI or a language interpreter
in rtl?

In this vent device the alarms are based on UI settings. To be able to say this is all hardware the UI will be controlled by the FPGA. So yes, an HDL UI is no big deal.

What are you thinking of that would be a big deal in HDL?

I\'m not taking a few leds, think graphical UI, icons, graphs, text formatting

and if you need memory it is going to be much cheaper in an MCU

All memory in a device is free once the device is selected. Why would it be more expensive in an FPGA???

because an FPGA with the same amount of available memory is going to be
much more expensive

Which is better...? usually the one we are more familiar with. People often talk as if it is silly to design something in an FPGA that doesn\'t require high speed or some other feature that makes it impossible to do in an MCU. I look at problems from the other perspective, I only put in an MCU the parts that are awkward to do in an FPGA.

sure if you have only an FPGA you try to put it in the FPGA, if you have an MCU you try yo put it in the MCU, if you have both you put it where it makes the most sense, keeping in mind that a lot more people can write code than HDL and the turn around for code it a lot shorter than HDL

In the board I sell by the thousands (making lots of money in the process) there was nothing that could not be done in the FPGA, so no MCU needed. Of course it is a daughter board in a bigger system with lots of processors running operating systems virtualizing other operating systems... and then they have bigger FPGAs than mine to do the real work.


I don\'t know what your board does, maybe an FPGA is the perfect fit

It was absolutely. But you fail to understand my point. Many, many designs can be done in FPGAs with no more trouble than in processors. But people who use processors are used to thinking in the messy, complex techniques of making a sequentially executing machine appear to execute many processes at the same time.

This is a bias based on familiarity. I would have though the same way 20 years ago. Now that I have done some more complex designs in FPGAs I realize it really isn\'t harder necessarily and can be easier since FPGA tools are optimized for simulation. Working in simulation allows so much to be verified without turning on power to a board. I think people underestimate that as well.

I realize now I\'m not going to win any converts by talking about it. People will keep using the tools they were taught. Now that they know the complex rules of making processors appear to process in parallel, there is little incentive to change their thinking. So they will continue to fight the same fights over and over.

you don\'t have to convert me, I have used FPGAs for 20+ years, but just because you have a hammer not everything is a nail, sometimes a screw is better

 

[Lasse Langwadt Christensen]

søndag den 30. august 2020 kl. 07.27.30 UTC+2 skrev Ricketty C:

On Saturday, August 29, 2020 at 10:31:21 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 02.05.33 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:56:22 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.27.48 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 5:27:27 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf

I found similar info on the ARM web site without the restriction to Xilinx parts, but I could not find out how to get it. I\'m sure there are many qualifications. Ts & Cs.


You have been able to get the cores for evaluation and design from ARM
for a long time, so you didn\'t need to get a license and pay until you
actually use it

as I understand it they have then made a deal with Xilinx that long as
it is used in a Xilinx fpga a license is included

So no T&C to read, review by lawyers and sign? Bet there is. Just from Xilinx rather than ARM.


why would it be any different than if you bought a Zynq that has a hardcore
ARM cpu? the license is included with the chip

No, there is no license to sign to use a Zynq. Are you telling me you have to sign paperwork or click on the web page link that acknowledges you agree to the contract to use a Zynq?

no, that just like buying a zynq includes a license to use the hardcore ARM, buying a, say, spartan7 includes a license to use a softcore ARM

 

[Lasse Langwadt Christensen]

søndag den 30. august 2020 kl. 10.50.09 UTC+2 skrev Ricketty C:

On Sunday, August 30, 2020 at 3:30:46 AM UTC-4, boB wrote:
On Sat, 29 Aug 2020 22:27:25 -0700 (PDT), Ricketty C
gnuarm.deletethisbit@gmail.com> wrote:

On Saturday, August 29, 2020 at 10:31:21 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 02.05.33 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:56:22 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.27.48 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 5:27:27 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude.. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf

I found similar info on the ARM web site without the restriction to Xilinx parts, but I could not find out how to get it. I\'m sure there are many qualifications. Ts & Cs.


You have been able to get the cores for evaluation and design from ARM
for a long time, so you didn\'t need to get a license and pay until you
actually use it

as I understand it they have then made a deal with Xilinx that long as
it is used in a Xilinx fpga a license is included

So no T&C to read, review by lawyers and sign? Bet there is. Just from Xilinx rather than ARM.


why would it be any different than if you bought a Zynq that has a hardcore
ARM cpu? the license is included with the chip

No, there is no license to sign to use a Zynq. Are you telling me you have to sign paperwork or click on the web page link that acknowledges you agree to the contract to use a Zynq?

I had a GPS that required acknowledgement of the contract to make it work. Otherwise I\'ve never seen that, web pages excepted. Digikey makes me agree to something with each new tab I open. Silly.


Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209


I\'m not sure why anyone would need to put an ARM processor on an FPGA
instead of just using an ARM processor and a less expensive and
complicated FPGA in addition to the ARM processor, if it would work.

I can see if being useful maybe if that FPGA would allow the ARM core
to run at an equivelant clock of sever gigaHz maybe.

You might set me straight on how much better an ARM micro running
sequenced code on an FPGA would be if that were the only thing being
done in that FPGA. Not talking about parallel operations but maybe
there is something to that in addition ?

If it\'s a soft core, the ARM would likely run slower in an FPGA unless the bottle neck in the ARM chip were something like Flash. In general an FPGA will run more slowly than any manner of dedicated chip. The routing adds delay to every path. FPGAs can be fast simply because they can be tailored to the task rather than executing general code to do what you want. Think of a processor with one instruction, your task. Maybe that\'s not a good analogy. But FPGAs aren\'t faster than processors, just more targeted so less wasted time doing things that aren\'t accomplishing the task, like fetching instructions.

For me it\'s not about speed. I just prefer the simplicity of coding the hardware to do what you need directly rather than thinking of what the processor is capable of or how the language is going to generate code to do the task. With HDL, if you describe the hardware properly, it will give you exactly what you ask for. That\'s way it\'s a Hardware Description Language.

so it is an extreme case of not invented here, instead of understanding a language, processor and peripherals, just reimplement everything from scratch

 

[Ricketty C]

On Sunday, August 30, 2020 at 9:12:52 AM UTC-4, Lasse Langwadt Christensen wrote:

søndag den 30. august 2020 kl. 07.23.33 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 10:25:18 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 01.58.15 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:50:46 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.39.05 UTC+2 skrev boB:
On Sat, 29 Aug 2020 14:27:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf


How fast will that FPGA programmed as an ARM Cortex M3 run and how
much will it cost ? Seems to me that a 20,000+ LUT FPGA is not
going to be cheap ? Compared to just buying an ARM processor of the
same complexity at least.

yeh you have to have some special need to put it in the fpga when you
can buy an MCU with more memory and preformance for a fraction of the price

I don\'t know why people get this backwards so often. You must have a special need to want a processor when you have a perfectly good FPGA.

and vice versa


Actually, an FPGA contains many, many tiny multiplexers connecting many, many tiny bits of RAM in contrast to a processor which has the power of the humongous multiplexer manipulating very large blocks of RAM and Flash. So the processor has to run very, very fast to create virtual connections between the many portions of memory. The FPGA in contrast has wires connected by routing FETs that can be used to connect the tiny multiplexers and bits of RAM as selected by the multiplexers.

While the processor can do many slow tasks by switching between them with its humongous multiplexer selecting which task to emulate now, the FPGA is actually processing each task in parallel using much simpler resources for each task, fast or slow, it doesn\'t care.


sure, but do you want to write something like a UI or a language interpreter
in rtl?

In this vent device the alarms are based on UI settings. To be able to say this is all hardware the UI will be controlled by the FPGA. So yes, an HDL UI is no big deal.

What are you thinking of that would be a big deal in HDL?


I\'m not taking a few leds, think graphical UI, icons, graphs, text formatting

You seem to be stuck in a rut that there is something difficult about HDL vs sequential languages. Icons are just bit blit. Why do you think any of the above is harder in an FPGA?

and if you need memory it is going to be much cheaper in an MCU

All memory in a device is free once the device is selected. Why would it be more expensive in an FPGA???


because an FPGA with the same amount of available memory is going to be
much more expensive

A processor with as much logic will be much more expensive. This is just a red herring. Use what gets the job done.

If you are talking about MB of memory, I\'ve already conceded that such tasks are not suited to HDL. Processors are uniquely suited for such tasks because the primary element in the devices is a large block of memory. The processor is just the little bit required to do the processing in that memory.. Think of the processing element in a Turing machine.

But in any event, memory is memory. It is neither more or less expensive in FPGAs vs. processors.

Which is better...? usually the one we are more familiar with. People often talk as if it is silly to design something in an FPGA that doesn\'t require high speed or some other feature that makes it impossible to do in an MCU. I look at problems from the other perspective, I only put in an MCU the parts that are awkward to do in an FPGA.


sure if you have only an FPGA you try to put it in the FPGA, if you have an MCU you try yo put it in the MCU, if you have both you put it where it makes the most sense, keeping in mind that a lot more people can write code than HDL and the turn around for code it a lot shorter than HDL

Fallacy! HDL is not inherently slower to produce than sequential code. Sequential code often requires considerable thought about sharing the processor. But you are stuck in a rut where you want to compare the trivial sequential cases without considering the complex cases in the real world. The vent we are working on has no \"OS\", but it has a \"scheduler\". I don\'t know how they are implementing it, but probably a round robin thing. This code simply would not exist in the FPGA and no one would need to give it any though.

In the board I sell by the thousands (making lots of money in the process) there was nothing that could not be done in the FPGA, so no MCU needed. Of course it is a daughter board in a bigger system with lots of processors running operating systems virtualizing other operating systems... and then they have bigger FPGAs than mine to do the real work.


I don\'t know what your board does, maybe an FPGA is the perfect fit

It was absolutely. But you fail to understand my point. Many, many designs can be done in FPGAs with no more trouble than in processors. But people who use processors are used to thinking in the messy, complex techniques of making a sequentially executing machine appear to execute many processes at the same time.

This is a bias based on familiarity. I would have though the same way 20 years ago. Now that I have done some more complex designs in FPGAs I realize it really isn\'t harder necessarily and can be easier since FPGA tools are optimized for simulation. Working in simulation allows so much to be verified without turning on power to a board. I think people underestimate that as well.

I realize now I\'m not going to win any converts by talking about it. People will keep using the tools they were taught. Now that they know the complex rules of making processors appear to process in parallel, there is little incentive to change their thinking. So they will continue to fight the same fights over and over.

you don\'t have to convert me, I have used FPGAs for 20+ years, but just because you have a hammer not everything is a nail, sometimes a screw is better

Sure, but poor analogies are pointless here. My point is that people often don\'t understand the pros and cons and how they are really a reflection of preferences rather than real advantages.

You tell me of your 20 years experience and in the same post tell me that HDL takes longer to code... that says something very clearly to me about your biases.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

 

[Ricketty C]

On Sunday, August 30, 2020 at 9:16:06 AM UTC-4, Lasse Langwadt Christensen wrote:

søndag den 30. august 2020 kl. 07.27.30 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 10:31:21 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 02.05.33 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:56:22 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.27.48 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 5:27:27 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf

I found similar info on the ARM web site without the restriction to Xilinx parts, but I could not find out how to get it. I\'m sure there are many qualifications. Ts & Cs.


You have been able to get the cores for evaluation and design from ARM
for a long time, so you didn\'t need to get a license and pay until you
actually use it

as I understand it they have then made a deal with Xilinx that long as
it is used in a Xilinx fpga a license is included

So no T&C to read, review by lawyers and sign? Bet there is. Just from Xilinx rather than ARM.


why would it be any different than if you bought a Zynq that has a hardcore
ARM cpu? the license is included with the chip

No, there is no license to sign to use a Zynq. Are you telling me you have to sign paperwork or click on the web page link that acknowledges you agree to the contract to use a Zynq?


no, that just like buying a zynq includes a license to use the hardcore ARM, buying a, say, spartan7 includes a license to use a softcore ARM

I\'m willing to bet there is a bunch of \"paperwork\" to sign in order to obtain the softcore. If nothing else you will need to put up your first born as collateral that you won\'t use the design in other brands. Then there are probably agreements regarding the ARM restrictions. Everyone has to protect their IP. It\'s nothing like buying a Zync chip or any other hardware ARM.

--

Rick C.

+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209

 

[server]

On Sun, 30 Aug 2020 06:12:47 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

søndag den 30. august 2020 kl. 07.23.33 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 10:25:18 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 01.58.15 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:50:46 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.39.05 UTC+2 skrev boB:
On Sat, 29 Aug 2020 14:27:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf


How fast will that FPGA programmed as an ARM Cortex M3 run and how
much will it cost ? Seems to me that a 20,000+ LUT FPGA is not
going to be cheap ? Compared to just buying an ARM processor of the
same complexity at least.

yeh you have to have some special need to put it in the fpga when you
can buy an MCU with more memory and preformance for a fraction of the price

I don\'t know why people get this backwards so often. You must have a special need to want a processor when you have a perfectly good FPGA.

and vice versa


Actually, an FPGA contains many, many tiny multiplexers connecting many, many tiny bits of RAM in contrast to a processor which has the power of the humongous multiplexer manipulating very large blocks of RAM and Flash. So the processor has to run very, very fast to create virtual connections between the many portions of memory. The FPGA in contrast has wires connected by routing FETs that can be used to connect the tiny multiplexers and bits of RAM as selected by the multiplexers.

While the processor can do many slow tasks by switching between them with its humongous multiplexer selecting which task to emulate now, the FPGA is actually processing each task in parallel using much simpler resources for each task, fast or slow, it doesn\'t care.


sure, but do you want to write something like a UI or a language interpreter
in rtl?

In this vent device the alarms are based on UI settings. To be able to say this is all hardware the UI will be controlled by the FPGA. So yes, an HDL UI is no big deal.

What are you thinking of that would be a big deal in HDL?


I\'m not taking a few leds, think graphical UI, icons, graphs, text formatting


and if you need memory it is going to be much cheaper in an MCU

All memory in a device is free once the device is selected. Why would it be more expensive in an FPGA???


because an FPGA with the same amount of available memory is going to be
much more expensive

That\'s usually the show-stopper in a soft core: program and data
memory. uPs often have a lot of both.

So, use a separate uP or add a DRAM chip and cache. Yuk.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

 

[Ricketty C]

On Sunday, August 30, 2020 at 11:59:52 AM UTC-4, jla...@highlandsniptechnology.com wrote:

On Sun, 30 Aug 2020 06:12:47 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

søndag den 30. august 2020 kl. 07.23.33 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 10:25:18 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 01.58.15 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 6:50:46 PM UTC-4, Lasse Langwadt Christensen wrote:
søndag den 30. august 2020 kl. 00.39.05 UTC+2 skrev boB:
On Sat, 29 Aug 2020 14:27:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 29. august 2020 kl. 23.13.05 UTC+2 skrev Ricketty C:
On Saturday, August 29, 2020 at 4:44:24 PM UTC-4, Lasse Langwadt Christensen wrote:
lørdag den 29. august 2020 kl. 21.57.41 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sat, 29 Aug 2020 20:38:31 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

jlarkin@highlandsniptechnology.com wrote:

There have been many programmable mixed-type (analog+digital) chips
over the years, but they don\'t seem to survive. Probably because they
don\'t do analog or digital very well.

Some of them are very interesting, e.g. the PSOC5LP family.
Unfortunately, its maximum IO frequency is 33MHz and it has only one PLL.

A small ARM with a bunch of *good* analog i/o might be interesting.

The ARM would need to host some programmable hardware LUTs to compete
with even this small mixed-type device. It escapes me why the MCUs with
even ~100 LUTs either do not exist at all at the lower end or are as
huge as Cyclone V/ZYNQ. If the signal frequency is ~50MHz, the MCU has
simply no chance to react. One needs to deploy an FPGA, which bumps up
the overengineering factor by two orders of magnitude. I see a lot of
applications for a mix of an ARM and a 1kLUT MACHXO3 device.

Best regards, Piotr

I think there are some SOCs (modest FPGA plus a small ARM) in the $20
range now.

We\'ll be seeing smallish FPGAs with a soft RISC-V core soon too. Soft
cores have been pretty bad up to now. Program space will still be a
restriction, but maybe a small FPGA with a megabyte of RAM or flash
and soft RISC-V would be a good product.

I believe Xilinx has a soft cortex M0/M3 that is free to use in their FPGAs

I\'ve seen several MB RAM in an SO8 package with a 133MHz QSPI interface,
that might be fast enough for some code

M1 perhaps? That\'s the core from ARM that is intended for such uses. Looks like they also have M3 for FPGAs as well, they even mention using them for \"free\" which I assume means evaluation.


yes M1 is M0 optimized for FPGA

as far as I can tell it is really free for use in Xilinx FPGAs

\"
Free to use on FPGA
Free use on FPGA for Cortex-M1 and Cortex-M3
For prototyping, research and commercial use
\"

https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/bringing-the-benefits-of-cortex-m-processors-to-fpga.pdf


How fast will that FPGA programmed as an ARM Cortex M3 run and how
much will it cost ? Seems to me that a 20,000+ LUT FPGA is not
going to be cheap ? Compared to just buying an ARM processor of the
same complexity at least.

yeh you have to have some special need to put it in the fpga when you
can buy an MCU with more memory and preformance for a fraction of the price

I don\'t know why people get this backwards so often. You must have a special need to want a processor when you have a perfectly good FPGA.

and vice versa


Actually, an FPGA contains many, many tiny multiplexers connecting many, many tiny bits of RAM in contrast to a processor which has the power of the humongous multiplexer manipulating very large blocks of RAM and Flash. So the processor has to run very, very fast to create virtual connections between the many portions of memory. The FPGA in contrast has wires connected by routing FETs that can be used to connect the tiny multiplexers and bits of RAM as selected by the multiplexers.

While the processor can do many slow tasks by switching between them with its humongous multiplexer selecting which task to emulate now, the FPGA is actually processing each task in parallel using much simpler resources for each task, fast or slow, it doesn\'t care.


sure, but do you want to write something like a UI or a language interpreter
in rtl?

In this vent device the alarms are based on UI settings. To be able to say this is all hardware the UI will be controlled by the FPGA. So yes, an HDL UI is no big deal.

What are you thinking of that would be a big deal in HDL?


I\'m not taking a few leds, think graphical UI, icons, graphs, text formatting


and if you need memory it is going to be much cheaper in an MCU

All memory in a device is free once the device is selected. Why would it be more expensive in an FPGA???


because an FPGA with the same amount of available memory is going to be
much more expensive

That\'s usually the show-stopper in a soft core: program and data
memory. uPs often have a lot of both.

So, use a separate uP or add a DRAM chip and cache. Yuk.

If you need so much memory that you can\'t fit it on an FPGA you are probably using the wrong tool for the job. Use an MCU or an integrated part. Talking about memory as if it is a bottle neck means you did a poor job of partitioning the design.

There are some parts in the Gowin lineup that include various forms of memory, system in package, multi-die, whatever they want to call it. Each solution has strengths and limitations. It\'s good to understand them well before choosing.

--

Rick C.

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209