EDK : FSL macros defined by Xilinx are wrong

[AL]

Hi, I take that back, it works for always @(posedge CLK_IN) as well as always @(CLK_IN), but only for very simple logic, if else and case statement, etc. For harder logic such as a counter, it read back 00000000. Does anyone know why?

 

[AL]

Hi, I take that back, it works for always @(posedge CLK_IN) as well as always @(CLK_IN), but only for very simple logic, if else and case statement, etc. For harder logic, it doesn't work, only read back 00000000 . Does anyone know why?

 

[Göran Bilski]

Hi,

If you connect four MicroBlazes to the same opb bus, I suspect that the last two
MicroBlaze will get very little access to the bus.

Not uploading firmware for the first one, will not stop them from executing.

So what communication do you need between the MicroBlazes?
Have you looked at using the FSL as the inter communication channel?

Göran Bilski

sergio.tota wrote:

Dear all,

I'm a new member of this board so a big hello to everybody.

I'm experiencing some problems with a multiprocessor architecture
based on the MicroBlaze.

I'm using ISE 6.3 and EDK 6.3.

I made 2 working multiprocessor systems with 2 CPUs.

The first use only one OPB bus and both the processors are linked to
such bus,

The second implementation use ONE OPB bus for each processor, for a
total of 2 processors and 2 OPB bus.
In this version obviously each processor lives "stand-alone" with no
interaction with the other.
(I used 2 ethernet IPs to let talk each-other...)

My problems started when I tried to implement a system with 4
processors linked to the same OPB bus.

The synthesis and P&R flow worked correctly and no errors were
given.

I then wrote 4 similar applications, one for each processor.

What I found was that only the first 2 processors worked and the other
2 seemed to be "dead".

What I thought first is that due to collisions, the last 2 processors
were never able to access to the bus,
So I tried to "disable" the first 2 processors ( not uploading the
firmware into the blockram) to see if the other 2 were able to
"scream" but nothing happened.

It seams that for some strange reason, if I use more than 2 processor
on an OPB bus, I can let them working correctly....( I don't want to
use the FSL for now...)

Any idea?

Thanks a lot!

Sergio

 

[Yaju N]

Apart from the current requirements, it seems that I have to worry
about the real estate for heat sinking.
The new TI TPS75003 seems to be good device, but it basically consists
of a linear regulator and not a switching one as I had thought.

I guess I will have to compromise on the real estate for heat sinking.
Maybe I will include a "finned" heat sink.

The search for the best voltage regulator continues.....

 

[Antonio Pasini]

The new TI TPS75003 seems to be good device, but it basically consists
of a linear regulator and not a switching one as I had thought.

Could you please be more specific on this ?

I was thinking of using it myself. I just quickly read the datasheets.

To me, it seems to have two buck regulators for core and I/O, where you
usually have most of the current, and a linear regulator for VCCAUX.

Given that VCCAUX powers also DCM modules, and its quiescent current is not
so big, perhaps you would have choosen an LDO in any case, to have it less
noisy.

Am I missing something obvious here ?

 

[glen herrmannsfeldt]

AL wrote:

Hi, I take that back, it works for always @(posedge CLK_IN)
as well as always @(CLK_IN), but only for very simple logic,
if else and case statement, etc. For harder logic such as a
counter, it read back 00000000. Does anyone know why?

always @(posedge CLK_IN)

says that the statements within the block are executed on the
rising edge of CLK_IN. If they are not doing that, or if the
are getting executed at other times then you have found a bug.

reg q;
always @(posedge clk) q=d;

implements the usual edge triggered flip-flop like the 74LS74.
If you put more in the always block you will get extra logic
before your flip-flop;

always @(posedge clk) q=d1 & d2;

is an AND gate and a FF.

reg [3:0] q;
always @(posedge clk) q=q+1;

is a four bit adder followed by four FFs, otherwise known as a
synchronous counter. (If you add up/down it could be a 74LS193)

-- glen

 

[Andrea]

I'm not so sure, but you can try to use the "configuration" in both your
modules and top level HDL, for example:

(in module)

architecture A of Module is
begin
....
end A;

architecture B of Module is
begin
....
end B

configuration CFG_A of Module is
for A
end for;
end CGF_A;

configuration CFG_B of Module is
for B
end for;
end CGF_B;

(in top-level)

architecture C of TOP is
....
U_Module: Module
port map( ..... );
....
end C;

configuration CFG_TOP of TOP is
for C
for U_module: Module
use configuration A work.CFG_A (for example)
end for;
end for;
end CFG_TOP;

I hope it's not so far from the solution, bye!

Andrea

Hi,

I have an VHDL toplevel entity with multiple architectures. If I try
to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
then only the last architecture will be synthesized.

Therefore my question: Is it possible to select the architecture that
will be synthesized and how this work?

Best Regards
Mathias

 

[Sewook Wee]

Hello digi,

I am using ML310, but still working with ppc_405.
Recently, I used uart_interrupt. In my case, the following step was needed
to initialize interrupt hanlder.

1. initialize the exception handler (XExc_Init(); )
2. register the external interrupt handler(noncritical intc) to
Exception handler. (XExc_RegisterHandler( ..... ))
3. register uart interrupt handler to the external interrupt
handler.(Xintc_RegisterHandler (.... ))
4. And followed enabling commands (please see PPC_ML310_Tutorial_6_3.pdf
and Platfor Studio User Guide)

If your vectortable failed to calculate your interrupt handler,
I think you should check the handler registration part first.

good luck.

Sewook

"digi" <digitreaco@yahoo-dot-de.no-spam.invalid> wrote in message
news:NpmdnaUEYJ9LpIHfRVn_vg@giganews.com...

Hallo to all!

I use memec development boart with virtexIIpro with ppc_405. I have
designed my own IPCore witch a interrupt signal.
And there i have a problem witch the Interrupt Handler. When a
Noncritical Interrup accur the ppc stops and only way go further is
to turn it off. I have debugg it and i saw that, when the interrupt
accur it goes to vectrortable 0x0500 store the register and then
begin calculate the address of my handler. And there is the
Problem!!! By calculating it stops and the PowerPC make notihng more
:-(

I think it could be a timing problem with my external SDRAM but i'm
not sure.
Can me somebody help there?
Thanks!

 

[KCL]

I don't know if you are still looking for IP to write text but I have finish
the pre-version of my VGA display , it takes input smbole code save it into
a rom that save all the caracter code to display on the screen and then
adress the rom with the font
the actual configuration is:
640*480 pixels screen
8*8 pixel caracter (so the screen could display 80*60symbols)
25MHz/pixel

actually not all the font is integrated (only A->Z)
http://kclo4.free.fr/FPGA/vga.zip
here is you could find the *.vhd files the top integrate the display
function called afficheur_vga and dummy for test (DCM for dividing frequency
and others stuff ) the constraint file is for spartan 3 digilent board
if you want to test the design just P&R and program your board
=>reset is the last slide switch
=>the 3 first slide switch are for color of screen
=>the push button are for the are respectevely a, b, c , enter (1sec refresh
frequency, could be change by changing the test value of cpt in top.vhd)

The design is not yet finish because I have to change some little thing as
complet the font, make generic all I can and make a documentation.

Regards

Alexis


"Marco" <marcotoschi@email.it> a écrit dans le message de news:
ee8bfb0.-1@webx.sUN8CHnE...

I should interface the my SoC with an HITACHI SP14Q005 display, 320x240
pixel.

There is someone who could tell me what to do to write text on display?

 

[rickman]

Yaju N wrote:

Apart from the current requirements, it seems that I have to worry
about the real estate for heat sinking.
The new TI TPS75003 seems to be good device, but it basically consists
of a linear regulator and not a switching one as I had thought.

I guess I will have to compromise on the real estate for heat sinking.
Maybe I will include a "finned" heat sink.

The search for the best voltage regulator continues.....

I found a new company that is making a very advanced surface mount
regulator module. They have combined everything onto the chip except
for the capacitors and run it at 5 MHz. This includes the *inductor*!
The module is only 0.5" x 0.32" and can provide up to 3 Amps.

www.enpirion.com

I just took another look at the web site and they now also have 1 Amp
and 6 Amp versions. The 6 Amp version is only 0.67" x 0.32"!



Rick Collins

rick.collins@XYarius.com

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design http://www.arius.com
4 King Ave. 301-682-7772 Voice
Frederick, MD 21701-3110 GNU tools for the ARM http://www.gnuarm.com

 

[Newman]

newman5382 wrote:

"nospam" <nospam@nospam.invalid> wrote in message
news:dq2n015ge9pgefno5jl0rlod7d7aao9m74@4ax.com...
Alex <uksb@greenbank.org> wrote:

Alex <uksb@greenbank.org> wrote:
[ SNIP original request ]

Thank you for all of the replies. I've ordered directly
from Xilinx and I'm looking forward to my new toy
arriving.

Did you or anyone else get the now bundled EDK evaluation (and 6.3i
ISE
evaluation I presume because the 6.3i EDK appears to need it)?


I have not got my EDK either. The Spartan III starter kit came with
the ISE
eval CD's I emailed the online store on Feb 07, 2005 and got the
same
answer as Carsten did on Jan 30, 2005 :

"quote"
The EDK eval is being sent to all who have purchased the Spartan 3
Starter kit and will begin shipping within the next couple of weeks.

"unquote"

I replied :

On or before Jan 30, 2005, you gave the same exact answer to another
customer.My question is, has your schedule slipped.


The answer on Feb 08, 2005 was :
The only information I have at this time is what was provided to us
by our
Marketing group. If possible, please send me your ship to address and
ship
to address of the other customer.I will then forward that information

directly to the department responsible for the eval.

I replied back on Feb 08, 2005 with the information requested. I
have yet
to receive an answer back as of Feb 10, 2005.

- Newman

I heard the EDK 6_3 Eval CD's have started to ship.

- Newman

 

[Göran Bilski]

Hi,

When using Xilinx, the SRL16 is a very good candidate for prescaler implementation.

Göran

Preben Holm wrote:

Hi everyone..

I wonder how to build a prescaled counter! That is a counter that can be
prescaled by fx. a factor 1.000.000 or less!

Any nice ideas how to do this?


Thanks
Preben

 

[TheMightyShaman]

Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cv294c$bmv3@cliff.xsj.xilinx.com>...

Since both processors starts at address 0, they will start to execute the same
initialization code.
You need to use a FSL port with different constant signals for each MicroBlaze.

Dear Mr. Bilski, sorry for the intromission. Just a question: how you
can declare a FSL port with constant signals without defining a custom
FSL core?

Thank you very much!

 

[Peter Alfke]

Prescalers are mostly used to increase the max frequency resolution.
What is it you are after?
Peter Alfke

 

[Göran Bilski]

Hi,

That is simple.
In the .mhs file if I want to assign a constant value of 1 to fsl port 0 and
also to make it always ready, I just add this to the MicroBlaze block.

PORT FSL0_S_DATA = 0b00000000000000000000000000000001
PORT FSL0_S_CONTROL = 0b0
PORT FSL0_S_EXISTS = 0b1

Göran

TheMightyShaman wrote:

Göran Bilski <goran.bilski@xilinx.com> wrote in message news:<cv294c$bmv3@cliff.xsj.xilinx.com>...

Since both processors starts at address 0, they will start to execute the same
initialization code.
You need to use a FSL port with different constant signals for each MicroBlaze.


Dear Mr. Bilski, sorry for the intromission. Just a question: how you
can declare a FSL port with constant signals without defining a custom
FSL core?

Thank you very much!

 

[Göran Bilski]

Hi,

If you don't want to express the constant value as binary, you can also do this.

PORT FSL0_S_DATA = 0x00000001

Göran

Göran Bilski wrote:

Hi,

That is simple.
In the .mhs file if I want to assign a constant value of 1 to fsl port 0
and also to make it always ready, I just add this to the MicroBlaze block.

PORT FSL0_S_DATA = 0b00000000000000000000000000000001
PORT FSL0_S_CONTROL = 0b0
PORT FSL0_S_EXISTS = 0b1

Göran

TheMightyShaman wrote:

Göran Bilski <goran.bilski@xilinx.com> wrote in message
news:<cv294c$bmv3@cliff.xsj.xilinx.com>...

Since both processors starts at address 0, they will start to execute
the same initialization code.
You need to use a FSL port with different constant signals for each
MicroBlaze.



Dear Mr. Bilski, sorry for the intromission. Just a question: how you
can declare a FSL port with constant signals without defining a custom
FSL core?

Thank you very much!

 

[Mike Treseler]

morpheus wrote:

I'm kinda new in the business so this question may be very rookie.
Anyways, I was wondering if all synchronous designs need to be state
machine based designed or the synchronous behaviour can be modelled
using multiple clocked processes like always (in Verilog) blocks
activated by clock to do the same thing.

A synchronous design entity (module)
contains one or more
clocked processes (always blocks).
A clocked process that updates an
enumerated local variable rather than
a vector or integer is sometimes called
a state machine. A single clocked process
can also update multiple process variables.

-- Mike Treseler

 

[gkirilov]

is it possible to have a sequences of bursts in the user logic instead
of using the DMA?

 

[Mike Treseler]

James wrote:

To this end, I've used a dual clock FIFO, with the write port connected
to the sensor, and the read port to the avalon interface (+ glue logic,
of course).

Consider a synchronous fifo on the fastest clock.
Synchronize the slow side to the fast clock.

Now the problem appears when I use Nios to transfer the contents of the
FIFO directly to the UART (and to a computer for some post-processing);
after a few 1000 pixels (around 15% of the total), the stream of data to
the computer stops.

Smells like a logic race.
Bogus full or empty from the fifo?

After some debugging with Nios' GDB/Eclipse getup

and SignalTap it appears that the constructed FSM is in no state (since
the signaltap signals <state_signal>.<state_name> for each of the 3
states were low).

Consider binary encoding.

During the compilation process, I received no warnings/errors regarding
timing constraints etc. or anything else for that matter. I am at a
complete loss as to how to even begin fixing this. Thoughts anyone?

Logic races come without warning to
teach the lessons of synchronization.

-- Mike Treseler

 

[Ben Twijnstra]

Hi Rob,

Looking at the voltage differences between the Spartan3 and the IDE
interface, it is my guess that I don't need to do any fancy voltage level
adjustments, just put 10 Ohm resistors in the path for unidirectional
lines, and 100 Ohm resistors for the bi-directional lines.

I hooked an old HDD to an Altera Cyclone without any resistors to write/port
an IDE interface myself. This took about three days to do, and both the
Cyclone and the HDD survived this period. But, I have no experience with
Spartan, so your mileage may vary.

Also, I will be starting a senior design project soon. My primary goal
when I graduate is to move in to embedded devices/FPGA's.

I'd say, do something with System-on-a-chip stuff. From my perspective this
would be using an an embedded processor plus custom logic/custom
instructions in VHDL or Verilog to do something useful in the DSP arena,
like decoding MP3 audio from a hard disk and filtering out the voice during
playback (for karaoke or music annotation).

If you go for this, make sure you don't quite finish the project - you'll be
worth a lot if you can state in your job interview that you can properly
implement this functionality now that you've learned from your past
experiences.

Best regards,


Ben