EDK : FSL macros defined by Xilinx are wrong

[Symon]

On 4/16/2011 2:53 PM, Phil Jessop wrote:

"Symon"<symon_brewer@hotmail.com> wrote in message
news:ioc0t1$8h2$1@dont-email.me...
On 4/16/2011 10:37 AM, Phil Jessop wrote:
"Symon"<symon_brewer@hotmail.com> wrote in message
news:ioalgd$vho$1@dont-email.me...
On 4/15/2011 9:36 PM, Morten Leikvoll wrote:
Im looking for an analog oscilloscope in the 2Ghz+ analog bw range and
wonder if you have any experience to share. Im used to the infiniium
54825,
but want to go faster (but not spend a fortune on a new one). I've seen
a
couple of "old" 54846 on ebay, and one recently went for $2800 wich is
a
price I can handle, but the next price on the list is not that nice.
I want to probe LVDS@1-2GHz signals, DVI and ddr3 memory buses at
533Mhz.


Hi Morten,
How much is Hyperlynx?
HTH, Syms.

More than the cost of a decent scope - and it's only a simulation so
garbage
in -> garbage out.

HTH

Phil


Hi Phil,
Perhaps you can explain how you would use a 'scope to measure the OP's
"LVDS@1-2GHz signals"?
Thanks, Symon.

Hi Symon,

???

Use a 2GHz scope with a differential probe. (Tek P7500 series or similar)

Are you new to this game?

Thanks

Phil


Hi Phil,

Is it true that the signal in the middle of a transmission line may not
be the same as it is at the receiver circuitry? Apparently, so I've
heard, there can be 'reflections', whatever they are?! These may make
the mid-trace measured signal different to the signal at the receiver.
Who would've thought it!

How would you probe on the input IOBs of the IC's receiver circuit with
a differential probe of a Tek P5700 series or similar?

Thanks, Symon.

p.s. What do you mean by 'new' and 'game'? xx

 

[Phil Jessop]

"Symon" <symon_brewer@hotmail.com> wrote in message
news:iock9m$j6s$1@dont-email.me...

On 4/16/2011 2:53 PM, Phil Jessop wrote:
"Symon"<symon_brewer@hotmail.com> wrote in message
news:ioc0t1$8h2$1@dont-email.me...
On 4/16/2011 10:37 AM, Phil Jessop wrote:
"Symon"<symon_brewer@hotmail.com> wrote in message
news:ioalgd$vho$1@dont-email.me...
On 4/15/2011 9:36 PM, Morten Leikvoll wrote:
Im looking for an analog oscilloscope in the 2Ghz+ analog bw range
and
wonder if you have any experience to share. Im used to the infiniium
54825,
but want to go faster (but not spend a fortune on a new one). I've
seen
a
couple of "old" 54846 on ebay, and one recently went for $2800 wich
is
a
price I can handle, but the next price on the list is not that nice.
I want to probe LVDS@1-2GHz signals, DVI and ddr3 memory buses at
533Mhz.


Hi Morten,
How much is Hyperlynx?
HTH, Syms.

More than the cost of a decent scope - and it's only a simulation so
garbage
in -> garbage out.

HTH

Phil


Hi Phil,
Perhaps you can explain how you would use a 'scope to measure the OP's
"LVDS@1-2GHz signals"?
Thanks, Symon.

Hi Symon,

???

Use a 2GHz scope with a differential probe. (Tek P7500 series or similar)

Are you new to this game?

Thanks

Phil


Hi Phil,

Is it true that the signal in the middle of a transmission line may not be
the same as it is at the receiver circuitry? Apparently, so I've heard,
there can be 'reflections', whatever they are?! These may make the
mid-trace measured signal different to the signal at the receiver. Who
would've thought it!

How would you probe on the input IOBs of the IC's receiver circuit with a
differential probe of a Tek P5700 series or similar?

Thanks, Symon.

p.s. What do you mean by 'new' and 'game'? xx

Rookie xxxx

 

[Morten Leikvoll]

"Symon" <symon_brewer@hotmail.com> wrote in message
news:iock9m$j6s$1@dont-email.me...

How would you probe on the input IOBs of the IC's receiver circuit with a
differential probe of a Tek P5700 series or similar?

I would route the lvds signal out to a TP basically.. And maybe even to a
LVDS TP if needed..
I also often generate redundant testpoints to check for errors in the logic
(buffer under/overflows and similar).
This is not ment to be used to check SI, but rather test the logic.
Unfortunately simulating what I do has to be limited to smaller blocks,
cause the complexity is huge!

 

[Symon]

On 4/18/2011 8:37 AM, Morten Leikvoll wrote:

"Symon"<symon_brewer@hotmail.com> wrote in message
news:iock9m$j6s$1@dont-email.me...
How would you probe on the input IOBs of the IC's receiver circuit with a
differential probe of a Tek P5700 series or similar?

I would route the lvds signal out to a TP basically.. And maybe even to a
LVDS TP if needed..
I also often generate redundant testpoints to check for errors in the logic
(buffer under/overflows and similar).
This is not ment to be used to check SI, but rather test the logic.
Unfortunately simulating what I do has to be limited to smaller blocks,
cause the complexity is huge!


Hi Morten,

Have you considered using something like ChipScope or SignalTap?
HTH, Syms.

 

[Morten Leikvoll]

"Symon" <symon_brewer@hotmail.com> wrote in message
news:ioh0nl$8nq$1@dont-email.me...

On 4/18/2011 8:37 AM, Morten Leikvoll wrote:
"Symon"<symon_brewer@hotmail.com> wrote in message
news:iock9m$j6s$1@dont-email.me...
How would you probe on the input IOBs of the IC's receiver circuit with
a
differential probe of a Tek P5700 series or similar?

I would route the lvds signal out to a TP basically.. And maybe even to a
LVDS TP if needed..
I also often generate redundant testpoints to check for errors in the
logic
(buffer under/overflows and similar).
This is not ment to be used to check SI, but rather test the logic.
Unfortunately simulating what I do has to be limited to smaller blocks,
cause the complexity is huge!


Hi Morten,
Have you considered using something like ChipScope or SignalTap?
HTH, Syms.

Yes, I have.. They may have their function but what kills it is the
limitations.
When I used xilinx I was a fan of the FPGA editor and often used it to tap
signals and route it to testpoints.
Now Im on an Altera project, and I am still looking for a similar simple
method to probe, without having to rebuild the entire code.

But I'm a bit disappointed that there is no reply to my original Q. Does
this mean that not a lot of fpga coders use oscilloscopes any more? (who
does?)

 

[maxascent]

I think the big problem, unless you are part of a large or well off compan
is the cost of the scope. I work for myself and would love to have a 10 GH
scope for the odd time I need it but the cost is just ridiculuos. Sayin
that I have found that the majority of the time with good design and pc
layout I havent really needed a scope as things have worked pretty much ok
If you can't afford something it makes you try harder to find other ways t
do the job so you dont need it. Probably ebay would be your best shot o
getting a scope but I would think you are still talking quite a fe
dollars.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Symon]

On 4/18/2011 11:32 AM, maxascent wrote:

I think the big problem, unless you are part of a large or well off company
is the cost of the scope. I work for myself and would love to have a 10 GHz
scope for the odd time I need it but the cost is just ridiculuos. Saying
that I have found that the majority of the time with good design and pcb
layout I havent really needed a scope as things have worked pretty much ok.
If you can't afford something it makes you try harder to find other ways to
do the job so you dont need it. Probably ebay would be your best shot of
getting a scope but I would think you are still talking quite a few
dollars.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

What he said! ^^^

We have a 10 Gsps 'scope. We rarely use it, and even when we do fire it
up, it rarely helps us solve the problem! I really should pack it away
somewhere inaccessible. Then we would debug much more quickly. It also
makes the office get very warm...

Cheers, Syms.

 

[Morten Leikvoll]

"colin" <colin_toogood@yahoo.com> wrote in message
news:0703993f-e992-4700-bc72-b52c978fe4fc@a11g2000pro.googlegroups.com...

We work at the edge, Gigabit ethernet, MGts, screaming DDR3s Virtex 7
and we know what's after 7 and roughly what's after that and we never
look at waveforms. Protocol analyzers perhaps but almost entirely
simulation.

How do you debug very complex systems? By spending months on finding and
setting up a failing environment?
I work with a video processor having an unknown number of unknown inputs
(with uknown clk domains and vertical scan phases) and outputs at configured
resolutions and quite a few handfuls of registers. I understand that for
some end use scenarios the verification is much more important than in my
case, but for video processing where we have lots of "visual probes" in
shape of monitors connected, I want to utilize them. The most effective way
of capturing bugs is to actually SEE the bug first, and then probe the fpga
to see where things didn't go as planned. Trying to make a testbench for all
these umlimited combinations is not necessary or possible.
Simulation has been very useful to get it up and running in the first place,
but scope is priceless to capture the bugs. I could use logic analyzers as
well, but that gives me less information and needs more pcb infrastructure
to have any use. I can do most tests in 4ch, and just add TP multiplexers.

 

[colin]

On Apr 16, 2:53 pm, "Phil Jessop" <p...@noname.org> wrote:

"Symon" <symon_bre...@hotmail.com> wrote in message

news:ioc0t1$8h2$1@dont-email.me...









On 4/16/2011 10:37 AM, Phil Jessop wrote:
"Symon"<symon_bre...@hotmail.com>  wrote in message
news:ioalgd$vho$1@dont-email.me...
On 4/15/2011 9:36 PM, Morten Leikvoll wrote:
Im looking for an analog oscilloscope in the 2Ghz+ analog bw range and
wonder if you have any experience to share. Im used to the infiniium
54825,
but want to go faster (but not spend a fortune on a new one). I've seen
a
couple of "old" 54846 on ebay, and one recently went for $2800 wich is
a
price I can handle, but the next price on the list is not that nice.
I want to probe LVDS@1-2GHz signals, DVI and ddr3 memory buses at
533Mhz.

Hi Morten,
How much is Hyperlynx?
HTH, Syms.

More than the cost of a decent scope - and it's only a simulation so
garbage
in ->  garbage out.

HTH

Phil

Hi Phil,
Perhaps you can explain how you would use a 'scope to measure the OP's
"LVDS@1-2GHz signals"?
Thanks, Symon.

Hi Symon,

???

Use a 2GHz scope with a differential probe. (Tek P7500 series or similar)

Are you new to this game?

Thanks

Phil

A 2 GHz signal has a fundamental frequency of 1GHz and to be worth
looking at you need to see the 5th harmonic. Looking at a sine wave
with your P7500 or similar is a complete waste of time. Usenet would
be a much nicer place if everyone responded to snipes like your "new
to this game" in the way that Symon did.
We work at the edge, Gigabit ethernet, MGts, screaming DDR3s Virtex 7
and we know what's after 7 and roughly what's after that and we never
look at waveforms. Protocol analyzers perhaps but almost entirely
simulation.

Colin

 

[Nico Coesel]

"Morten Leikvoll" <mleikvol@yahoo.nospam> wrote:

"Symon" <symon_brewer@hotmail.com> wrote in message
news:ioh0nl$8nq$1@dont-email.me...
On 4/18/2011 8:37 AM, Morten Leikvoll wrote:
"Symon"<symon_brewer@hotmail.com> wrote in message
news:iock9m$j6s$1@dont-email.me...
How would you probe on the input IOBs of the IC's receiver circuit with
a
differential probe of a Tek P5700 series or similar?

I would route the lvds signal out to a TP basically.. And maybe even to a
LVDS TP if needed..
I also often generate redundant testpoints to check for errors in the
logic
(buffer under/overflows and similar).
This is not ment to be used to check SI, but rather test the logic.
Unfortunately simulating what I do has to be limited to smaller blocks,
cause the complexity is huge!


Hi Morten,
Have you considered using something like ChipScope or SignalTap?
HTH, Syms.

Yes, I have.. They may have their function but what kills it is the
limitations.
When I used xilinx I was a fan of the FPGA editor and often used it to tap
signals and route it to testpoints.
Now Im on an Altera project, and I am still looking for a similar simple
method to probe, without having to rebuild the entire code.

But I'm a bit disappointed that there is no reply to my original Q. Does
this mean that not a lot of fpga coders use oscilloscopes any more? (who
does?)

I mostly use a logic analyzer. Still probing can be the killer. An
oscilloscope is one thing but beyond 100MHz you'll need special probes
which can cost major $$$.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[colin]

On Apr 18, 12:12 pm, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:

"colin" <colin_toog...@yahoo.com> wrote in message

news:0703993f-e992-4700-bc72-b52c978fe4fc@a11g2000pro.googlegroups.com...

We work at the edge, Gigabit ethernet, MGts, screaming DDR3s Virtex 7
and we know what's after 7 and roughly what's after that and we never
look at waveforms. Protocol analyzers perhaps but almost entirely
simulation.

How do you debug very complex systems? By spending months on finding and
setting up a failing environment?
I work with a video processor having an unknown number of unknown inputs
(with uknown clk domains and vertical scan phases) and outputs at configured
resolutions and quite a few handfuls of registers. I understand that for
some end use scenarios the verification is much more important than in my
case, but for video processing where we have lots of "visual probes" in
shape of monitors connected, I want to utilize them. The most effective way
of capturing bugs is to actually SEE the bug first, and then probe the fpga
to see where things didn't go as planned. Trying to make a testbench for all
these umlimited combinations is not necessary or possible.
Simulation has been very useful to get it up and running in the first place,
but scope is priceless to capture the bugs. I could use logic analyzers as
well, but that gives me less information and needs more pcb infrastructure
to have any use. I can do most tests in 4ch, and just add TP multiplexers..

I used the term "protocol analyser" in its loosest sense. If you want
to look at video use a CRT if that is all you can afford but a video
protocol analyser will tell you what is wrong fundamentally quicker
than hooking up a scope. I also meant hyperlynx simulation rather than
modelsim. You said you wanted to look at DDR3 and gigabit stuff. If
you spend less than $2K on a probe the act of looking at the signal
will mess it up. I've designed DDR2 96bit wide stuff and never probed
it, you can't because the chips are on both sides of the board and the
routing is on internal layers. The lousiest design on the planet will
work at 25 centigrade so you don't need a scope. Your welcome to hook
a scope up in an oven and see why it doesn't work at 55 or -5. Instead
make darn sure your at 50 ohms and you have simulated and have
chipscope report all the timing parameters that the mig is using. If
none of the timings are at an end of their scale you have a design you
can build a thousand of.

hmm, sorry that was a bit of a rant but I'm not going to reword it

Colin

 

[NeedCleverHandle]

On Apr 15, 2:58 pm, Rick <richardcort...@gmail.com> wrote:

On Apr 15, 1:35 am, Rick <richardcort...@gmail.com> wrote:

Still lost in the woods.

I came across the Simili download so I searched the newsgroup. Hasn't
been a post in the newsgroup for 3 years. Is there a fatal flaw of
some kind with this software that would make it something to be
avoided? I kind of like the fact it is only a 9 meg zip as opposed to
installing fistfuls of Webpack gigs.

I'm not needing anything beyond being able to program/debug stuff in
the 22V10 range.

Rick

OK, looks like you need to add the manufacturers definitions which
would have meant downloading gigs of info. If I have it right the
program looks on your hard drive for most of the popular manufacturers
installs and compiles from there.

I finally backed off to WinCUPL from Atmel. Still only 20 megs and
seems beginner enough for me to use. Managed to get my first try
compiled and trying to learn the simulator now.

Rick

Cypress Warp => 22V10's in VHDL or Verilog.

Support dropped by Cypress, but it's still available on the grey
market.

RK.

 

[Morten Leikvoll]

"colin" <colin_toogood@yahoo.com> wrote in message
news:89a1ef5f-ddbd-4be2-84e8-ce5f12d1f013@b13g2000prf.googlegroups.com...

I used the term "protocol analyser" in its loosest sense. If you want
to look at video use a CRT if that is all you can afford but a video
protocol analyser will tell you what is wrong fundamentally quicker
than hooking up a scope. I also meant hyperlynx simulation rather than

Im not so sure that would work better than a monitor. Maybe on some types of
errors, but having a moving image shown will reveal much of the REAL
problems. We can accept for example pixel blip in 1 of 10000 frames, but
errors that only occur at certain pixelrates and on certain patterns
(revealing SSO issues) is better just to view. An analyzer would need to
know far too much and would be equivalent complex as a sim testbench to set
up.

modelsim. You said you wanted to look at DDR3 and gigabit stuff. If
you spend less than $2K on a probe the act of looking at the signal
will mess it up. I've designed DDR2 96bit wide stuff and never probed

I'm not as digital as you. I can live with seing the signal 50% correct.
There is still a lot of information in the pulse, but you have to know you
are using a probe with low spec when you interpret the result. (I also use
the cheapest soldering iron you can find to do very complex soldering; you
don't HAVE to use the most expensive)

it, you can't because the chips are on both sides of the board and the
routing is on internal layers. The lousiest design on the planet will
work at 25 centigrade so you don't need a scope. Your welcome to hook
a scope up in an oven and see why it doesn't work at 55 or -5. Instead

Our current design has 4 dimms of 72bits and its working without ever being
probed, but many times in the process, I would like to probe it to rule out
some issues we had, mostly on ck and ctrl bus. As an example I can tell
there was a left shift in a color and I wanted to probe if it happened
during read or write. It appeared to be a timing issue as we have laid out
the pcb with inverted clk pair, and couldn't get the IP to cooperate with
that. It got solved without probing in the end.

make darn sure your at 50 ohms and you have simulated and have
chipscope report all the timing parameters that the mig is using. If
none of the timings are at an end of their scale you have a design you
can build a thousand of.

No problem, it runs at 533Mhz with two Spartan3 E110's (and a E50) I'ts a
huge board and it was laid out on Cadsoft's Eagle(!), and worked on first
rev (well, the memory did. We screwed up a couple of connector pinouts, but
we got it running with some adapters).

hmm, sorry that was a bit of a rant but I'm not going to reword it

I like ranting It's an efficient way of communicating if its two-way and
as long as nobody takes it personal.

 

[Pratap]

On May 18, 11:06 pm, Pratap <pratap.i...@gmail.com> wrote:

Hi,
I need to take out two square wave signals from the Virtex II Pro FPGA
board(XC2VP30, package ff896) with good signal shape and less jitter
value. The frequency of the two square wave signals are around 40MHz
and one is the delayed version of the other. I am trying to evaluate
the performance of a delay generator block inside the FPGA. Hence, the
shape and precision of the delays is of greater importance to me. I
have tried to take the signals through various pins on the board
including the high speed expansion connector. But I found that only
when the signals are routed out through the EXT_CLK_P(G15) and
EXT_CLK_N(F15) pins, the jitter performance is the best. But there is
a funny thing happening when I observe the two waveforms on a scope.
Below are the two cases. Looks like, when the signal levels of the two
signals are different, the signal with ZERO logic goes up to around
0.2*Vsupply and at the same time the signal with logic '1' goes down
by around 0.2Vsupply. Can anybody suggest how can I avoid such a
situation? I feel there is some sort of resistor coupling between
these two signals. But, can I  disable this coupling by changing some
setting in the ucf file? This is the entry in the ucf file
corresponding to the two pins mentioned above.

NET "clk_in_copy"  LOC = "G15" | IOSTANDARD = LVTTL  | SLEW = FAST |
DRIVE = 12 ;
#EXTERNAL_CLOCK_P=G15

NET "op_from_delay_chip_copy"  LOC = "F15" | IOSTANDARD = LVTTL | SLEW
= FAST | DRIVE = 12 ;
#EXTERNAL_CLOCK_N=F15

Please suggest a way to set these signals such that the coupling
between these two signals is nullified and I can use them as two true
single ended outputs.

Here is an illustration of the case.https://picasaweb.google.com/lh/webUpload?uname=pratap.iisc&aid=56081...

Waiting for some helpful answers.
Thanks and regards,
Pratap

Sorry...The link for the picture was wrogly pasted...Here is the
correct link.
https://picasaweb.google.com/pratap.iisc/May182011?authkey=Gv1sRgCMjQ85X3q5O50gE#5608112742914669794

 

[Ed McGettigan]

On May 18, 11:14 am, Pratap <pratap.i...@gmail.com> wrote:

On May 18, 11:06 pm, Pratap <pratap.i...@gmail.com> wrote:





Hi,
I need to take out two square wave signals from the Virtex II Pro FPGA
board(XC2VP30, package ff896) with good signal shape and less jitter
value. The frequency of the two square wave signals are around 40MHz
and one is the delayed version of the other. I am trying to evaluate
the performance of a delay generator block inside the FPGA. Hence, the
shape and precision of the delays is of greater importance to me. I
have tried to take the signals through various pins on the board
including the high speed expansion connector. But I found that only
when the signals are routed out through the EXT_CLK_P(G15) and
EXT_CLK_N(F15) pins, the jitter performance is the best. But there is
a funny thing happening when I observe the two waveforms on a scope.
Below are the two cases. Looks like, when the signal levels of the two
signals are different, the signal with ZERO logic goes up to around
0.2*Vsupply and at the same time the signal with logic '1' goes down
by around 0.2Vsupply. Can anybody suggest how can I avoid such a
situation? I feel there is some sort of resistor coupling between
these two signals. But, can I  disable this coupling by changing some
setting in the ucf file? This is the entry in the ucf file
corresponding to the two pins mentioned above.

NET "clk_in_copy"  LOC = "G15" | IOSTANDARD = LVTTL  | SLEW = FAST |
DRIVE = 12 ;
#EXTERNAL_CLOCK_P=G15

NET "op_from_delay_chip_copy"  LOC = "F15" | IOSTANDARD = LVTTL | SLEW
= FAST | DRIVE = 12 ;
#EXTERNAL_CLOCK_N=F15

Please suggest a way to set these signals such that the coupling
between these two signals is nullified and I can use them as two true
single ended outputs.

Here is an illustration of the case.https://picasaweb.google.com/lh/webUpload?uname=pratap.iisc&aid=56081...

Waiting for some helpful answers.
Thanks and regards,
Pratap

Sorry...The link for the picture was wrogly pasted...Here is the
correct link.https://picasaweb.google.com/pratap.iisc/May182011?authkey=Gv1sRgCMjQ...- Hide quoted text -

- Show quoted text -

Based on the names these are intended to be a differential pair. This
means that they have been routed close together on the board and will
have intentional coupling/crosstalk between the two routed nets. In
addition there is likely a 100 ohm termination resistor between the
two nets that is generating the bump that you are seeing.

The resistor could be removed, you will need to check the schematics
for you board to determine which one it is.

The crosstalk however cannot be removed.

Ed McGettigan
--
Xilinx Inc.

 

[Pratap]

On May 19, 5:24 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On May 18, 11:14 am, Pratap <pratap.i...@gmail.com> wrote:



On May 18, 11:06 pm, Pratap <pratap.i...@gmail.com> wrote:

Hi,
I need to take out two square wave signals from the Virtex II Pro FPGA
board(XC2VP30, package ff896) with good signal shape and less jitter
value. The frequency of the two square wave signals are around 40MHz
and one is the delayed version of the other. I am trying to evaluate
the performance of a delay generator block inside the FPGA. Hence, the
shape and precision of the delays is of greater importance to me. I
have tried to take the signals through various pins on the board
including the high speed expansion connector. But I found that only
when the signals are routed out through the EXT_CLK_P(G15) and
EXT_CLK_N(F15) pins, the jitter performance is the best. But there is
a funny thing happening when I observe the two waveforms on a scope.
Below are the two cases. Looks like, when the signal levels of the two
signals are different, the signal with ZERO logic goes up to around
0.2*Vsupply and at the same time the signal with logic '1' goes down
by around 0.2Vsupply. Can anybody suggest how can I avoid such a
situation? I feel there is some sort of resistor coupling between
these two signals. But, can I  disable this coupling by changing some
setting in the ucf file? This is the entry in the ucf file
corresponding to the two pins mentioned above.

NET "clk_in_copy"  LOC = "G15" | IOSTANDARD = LVTTL  | SLEW = FAST |
DRIVE = 12 ;
#EXTERNAL_CLOCK_P=G15

NET "op_from_delay_chip_copy"  LOC = "F15" | IOSTANDARD = LVTTL | SLEW
= FAST | DRIVE = 12 ;
#EXTERNAL_CLOCK_N=F15

Please suggest a way to set these signals such that the coupling
between these two signals is nullified and I can use them as two true
single ended outputs.

Here is an illustration of the case.https://picasaweb.google.com/lh/webUpload?uname=pratap.iisc&aid=56081...

Waiting for some helpful answers.
Thanks and regards,
Pratap

Sorry...The link for the picture was wrogly pasted...Here is the
correct link.https://picasaweb.google.com/pratap.iisc/May182011?authkey=Gv1sRgCMjQ...Hide quoted text -

- Show quoted text -

Based on the names these are intended to be a differential pair.  This
means that they have been routed close together on the board and will
have intentional coupling/crosstalk between the two routed nets.  In
addition there is likely a 100 ohm termination resistor between the
two nets that is generating the bump that you are seeing.

The resistor could be removed, you will need to check the schematics
for you board to determine which one it is.

The crosstalk however cannot be removed.

Ed McGettigan
--
Xilinx Inc.

Thanks a lot McGettigan for the quick answer.
I checked the board again and found out that there was indeed an SMD
resistor soldered from the bottom side creating this impact. After
removing that resistor it looks nice. The crosstalk is not that much
as I am operating at around 40MHz. But one thing I am wandering is,
how only these two outputs are behaving so well where as none of the
other pins (even some pins taken from high speed expansion connector
J37) produce such clean and less jittery waveforms.

-Pratap

 

[Ed McGettigan]

On May 19, 9:26 am, Pratap <pratap.i...@gmail.com> wrote:

On May 19, 5:24 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On May 18, 11:14 am, Pratap <pratap.i...@gmail.com> wrote:

On May 18, 11:06 pm, Pratap <pratap.i...@gmail.com> wrote:

Hi,
I need to take out two square wave signals from the Virtex II Pro FPGA
board(XC2VP30, package ff896) with good signal shape and less jitter
value. The frequency of the two square wave signals are around 40MHz
and one is the delayed version of the other. I am trying to evaluate
the performance of a delay generator block inside the FPGA. Hence, the
shape and precision of the delays is of greater importance to me. I
have tried to take the signals through various pins on the board
including the high speed expansion connector. But I found that only
when the signals are routed out through the EXT_CLK_P(G15) and
EXT_CLK_N(F15) pins, the jitter performance is the best. But there is
a funny thing happening when I observe the two waveforms on a scope..
Below are the two cases. Looks like, when the signal levels of the two
signals are different, the signal with ZERO logic goes up to around
0.2*Vsupply and at the same time the signal with logic '1' goes down
by around 0.2Vsupply. Can anybody suggest how can I avoid such a
situation? I feel there is some sort of resistor coupling between
these two signals. But, can I  disable this coupling by changing some
setting in the ucf file? This is the entry in the ucf file
corresponding to the two pins mentioned above.

NET "clk_in_copy"  LOC = "G15" | IOSTANDARD = LVTTL  | SLEW = FAST |
DRIVE = 12 ;
#EXTERNAL_CLOCK_P=G15

NET "op_from_delay_chip_copy"  LOC = "F15" | IOSTANDARD = LVTTL | SLEW
= FAST | DRIVE = 12 ;
#EXTERNAL_CLOCK_N=F15

Please suggest a way to set these signals such that the coupling
between these two signals is nullified and I can use them as two true
single ended outputs.

Here is an illustration of the case.https://picasaweb.google.com/lh/webUpload?uname=pratap.iisc&aid=56081...

Waiting for some helpful answers.
Thanks and regards,
Pratap

Sorry...The link for the picture was wrogly pasted...Here is the
correct link.https://picasaweb.google.com/pratap.iisc/May182011?authkey=Gv1sRgCMjQ...quoted text -

- Show quoted text -

Based on the names these are intended to be a differential pair.  This
means that they have been routed close together on the board and will
have intentional coupling/crosstalk between the two routed nets.  In
addition there is likely a 100 ohm termination resistor between the
two nets that is generating the bump that you are seeing.

The resistor could be removed, you will need to check the schematics
for you board to determine which one it is.

The crosstalk however cannot be removed.

Ed McGettigan
--
Xilinx Inc.

Thanks a lot McGettigan for the quick answer.
I checked the board again and found out that there was indeed an SMD
resistor soldered from the bottom side creating this impact. After
removing that resistor it looks nice. The crosstalk is not that much
as I am operating at around 40MHz. But one thing I am wandering is,
how only these two outputs are behaving so well where as none of the
other pins (even some pins taken from high speed expansion connector
J37) produce such clean and less jittery waveforms.

-Pratap- Hide quoted text -

- Show quoted text -

The most likely answer is that you are getting a good connection for
the scope probe and a bad one trying to connect to the other
connector.

Ed McGettigan
--
Xilinx Inc.

 

[Mike Treseler]

On 6/2/2011 10:45 AM, Wojciech M. Zabolotny wrote:

When working with simulated soft CPUs to be implemented in FPGA,
I often needed a possibility to connect terminal emulator
(e.g. Minicom) or my own program to serial port of the simulated
IP core.

Finally I've found a solution, which seems to be good enough
to share it with others.

Thanks for the interesting and useful VPI example.

Of course the link to alt.usenet message should be:
http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba

Yes, that does the trick.

-- Mike Treseler

 

[wzab]

Of course the link to alt.usenet message should be:
http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba

 

[Aliaksei Chapyzhenka]

http://wavedrom.googlecode.com

WaveDrom is Free and Open Source online digital timing diagram editor that uses JavaScript?, HTML5 and SVG to render WaveJSON input text description into vector graphics.

The project is in progress. Any feedback appreciated.