The only tricky part here is the "once it syncs up" bit.John Larkin wrote:
On Wed, 01 Jun 2005 00:44:18 GMT, Joerg
notthisjoergsch@removethispacbell.net> wrote:
Hello John,
Skolnik's "Radar Handbook" has some I/Q error budgeting in chapter 3 but
I don't think it'll suffice here. I have never seen a book that goes
this far into practical matters on Hilbert (except for the analog
version), maybe too small a market for publishers. If there is anything
out there it'll be most likely for Doppler applications.
Artech House may have some good stuff and you could check them. Most
books about transforms come with a CD full of helpful routines but often
they will be plain C code:
http://www.artechhouse.com/default.asp?Frame=Book.asp&Book=C5P10&Country=&Continent=ME&State=
Possibly you could start at one of the math simulator vendors, like here:
http://www.mathworks.com/access/helpdesk/help/toolbox/signal/filterd9.html
Simulators are almost a must when doing this kind of stuff. My turf is
med imaging and there usually every company invents the wheel again,
simulates until smoke comes out of the PC and then it all becomes a
trade secret. They rarely publish.
What do you want to do? Does it have to be poured into the FPGA?
Suppose I have an AC power system, and I can digitize a pair of
voltage and current waveforms. I want to report everything: trms
volts/amps, true power, reactive power, phase angle. The line
frequency could vary from maybe 20 to 80 Hz for a stationary
generator, or 200-800 for an aircraft system (including startup and
weird situations.) I'll digitize to 16 bits, at maybe 20K
samples/second or something. I'm considering doing all the signal
processing in an FPGA, crunching maybe 8 voltage+current pairs.
For the rms volts/amps, we could just square the samples, filter, and
allow my pokey uP to occasionally pick up that and square root.
True power is just the product of the e*i samples, lowpass filtered.
Easy.
What's tricky is the reactive power/phase angle thing. The ideal thing
would be to delay the voltage samples 90 degrees and then multiply by
the current samples, then filter to get the signed reactive power. The
trick is to delay the voltage sample data stream 90 degrees. A
discrete (fir) Hilbert would give me the phase-shifted voltage signal
(actually 135 deg, not 90, so I'd have to delay the current samples,
too, but that's OK.) I just need to quantify how good a given
implementation might be.
The other way to do it would be to use a fifo clocked at a multiple of
the waveform frequency, delaying the voltage or current samples by 90
degrees. That would take a digital PLL to track the voltage waveform
frequency and generate a 128x or something tracking clock. Maybe a
dds/nco clock gen with some fancy digital phase detector? That's
complex, too, but has the advantage of acquiring the waveform
frequency essentially for free. I could have a range bit the user sets
for the 60 vs 400 Hz situations, so I'd only need about a 4:1 tracking
range on the clock.
Either way, it sounds like I'm in for some simulation. PowerBasic!
John
why not a synchronous demodulator (or lock-in amp
if you have 3 phases, its trivial. measure all 3 phases, and do a 3-2
phase transform to create an equivalent rotating vector a + jb. for a
single-phase system, build a 90 degree phase shifter so you have
Vpeak*sin(theta) + j*Vpeak*cos(theta).
then multiply by exp(-jtheta) (decompose into real & imaginary calcs)
You will then get 2 outputs, call them Vd and Vq. If you have a pure
sinusoidal system, and theta = integral(w_line.dt) is the correct phase,
one of these will be zero. Use this as the feedback to a PI controller,
whose reference is zero. PI output has ideal line frequency added to it
(if you want, not necessary) and is then integrated to produce theta.
once it syncs up, you have your real & imaginary V,I components in the
stationary reference frame, IOW they are DC quantities. easy to figure
out reactive power etc.
Cheers
Terry
Yes, it works. I have made scramblers that way (in VHDL). It should
Are you trying to understand how it works or looking for a
Isn't that clock for clock? My understanding was that they had to make
Either that, or Intel employed more of the cheap workforce, relied heavily
Interesting - is that DIV 2 in the IO area, or in the DCM itself - in
What jitter spec, would the DCM give ?Division ( even combined multiply/divide) with numbers up to 32 is no
problem. You can multiply 500 MHz by 7 and divide by 27 (if those are
your numbers). The virtual 3.5 GHz are not really being generated, it's
all mathematical trickery.
-jg
In the DCM. Turns out the IOB is pretty good at receiving signals: V2
For simple divide by 10, the jitter will be entirely from the tapDivision ( even combined multiply/divide) with numbers up to 32 is no
problem. You can multiply 500 MHz by 7 and divide by 27 (if those are
your numbers). The virtual 3.5 GHz are not really being generated, it's
all mathematical trickery.
What jitter spec, would the DCM give ?
assume sub 100MHz out, and 1GHz sub ps jitter IP .
Silicon Labs have small uC that can do 32 Channel ADC, in 12 bit or 8