EDK : FSL macros defined by Xilinx are wrong

preet schrieb:

I have written the code for my encoder below. It is synthesizable and has no errors.
This is good, but does not prove too much.

What i want to do is after programming the FPGA(Spartan3 starter kit), I want to check the results from the harware.

Means using LEDs for 3 bit output and switch for the input.
This might be a nice test (or better call it play around), but a
simulation is much better and does show much more. So your "test" isn't
a real test, it has no practical relevance.

My code also contains the clock signal.

IF i lock one switch to Clock and then toggle it's not working and i think it won't.
You can't use a normal switch to supply a clock to a digital circuit,
especially not a modern FPGA. The switch WILL bounce and produce
multiple pulses. A debouncing is necessary, either by hardware
(RC-filter + schmitt trigger) or software (logic inside the FPGA)

I want to test this code on hardware.

Some one suggested Using Picoblaze, RS232,UART connection.

I really have no clue of how to do it.
Looks like you just starting to get into the digital/FPGA business.
Start small. Get a simpler circuit thant a Viterby decoder. Get a
feeling for simulation and testing in hardware, understand the
difference and the idea behind the different ways of testing.
For instance, build a simple 4 bit counter. Do a clean simulation.
Implement it in hardware. Test it in hardware (use a switch debouncer).
Then go on to the Viterby.

Where to get picoblaze, how to program it to take input from RS232,
where to get UART models. And how will i be writing the text in
hyperterminal
to send the data through this port.Will i be actually toggling the
switch which i have locked for input.
Picoblaze can be found on the Xilinx website, look for xapp213.

I badly need help on this.
I think you need to understand some basic concepts first.

Regards
Falk
 
Angelos <aamanat@ee.duth.gr> wrote:
Hi all,

I would like to ask if anyone has implemented a physical usb interface in a
development board of altera that has not mounted a usb inf.

The core for usb1.1 and 2.0 are available but do i need certain physical
layer to implement usb?

I heared that for low speed i dont need to implement anythin just drive the
wires into the fpga but for high speed i need to implement the phy intf.
For USB1 1.5 Mbps it can be done with a mcu-PIC, 12 Mbps can proberbly also be
accomplished fairly easily. USB2 480 Mbps is another ballgame.. but with
enough MHz it maybe will work .. ;)
 
I agree with Clark, thats why the IP cores are for. The only matter is the
physical connection cause the high frequencies of the wires you have to
drive inside the fpga need to be shielded from noise.

chech existing phy inteegrated chips.

"Anonymous" <someone@microsoft.com> wrote in message
news:zraXf.56091$915.5917@southeast.rr.com...
Dumb question: Since USB is just a two wire serial interface and all the
USB
solutions I've seen are simple, though speedy, microcontrollers why can't
the USB be inside the fpga? Seems like you can instantiate a small micro
running at 50 mhz or so with code in a couple block rams to do what the
fx2,
for example, does. Apparently, doesn't exist so there must be some reason?

-Clark

"Mike Harrison" <mike@whitewing.co.uk> wrote in message
news:37no22duhjkjtns5mh9kvock01039l4tum@4ax.com...
On 30 Mar 2006 09:56:49 -0800, "johnp" <johnp3+nospam@probo.com> wrote:

I've used the Cypress FX2 in the past. It has a flexible
interface that can support byte or word interfaces. They
used to have sample driver code, I believe they now supply
only a pre-built driver, you may want to check.

It's a very flexible part, but with the flexiblity comes the need
for additional design work.

You might look at ?QuickUSB? that has a canned design with
the FX2, but I'm sure if it can handle full data rates sustained.

John Providenza

I used quickusb recently - removes the need to get involved in any of the
low-level USB stuff at the
PC end, and supports various IO models - 8/16 bit, internal/external
addressing, with various fifo
modes and UARTs plus a FPGA bitstream programming mode. Absolute minimum
pin count would be 8 data +
2 control + clock, but you'd probably need at least one extra for
framing/handshaking.
http://www.quickusb.com
 
"johnp" <johnp3+nospam@probo.com> wrote in message
news:1143913431.274974.10660@j33g2000cwa.googlegroups.com...
The OP wanted a "time efficient" approach for adding USB support.

I suspect trying to embed USB IP inside a FPGA does not meet
this requirement. Yes, you could add a USB core and a PHY and
an embedded processor and write and debug a bunch of code....

Or you could leverage parts like the Cypress FX2 that provides several
easy approaches to doing this.

Which is more "time efficient"?

John Providenza
What's more time efficient then going to your EDK and just adding an OPB_USB
peripheral? I was just asking why such a thing doesn't appear to exist. But,
yes, I agree I strayed off topic.

-Clark
 
oen_no_spam@yahoo.com.br wrote:
I have some doubts about the SPT3E Phase Shifter.

First:
Data sheet V3.0, pg. 54, fig. 44: CLK180 is wrong. I must start as
high! (easy to see)
To quote the immortal Homer Simpson, "Doh!" I'll see that this is
fixed!
Data sheet V3.0, pg. 57, eq. 6: MAX_STEPS =
+/-[integer(20*(TCLKIN-3ns))]
For example a 20MHz clock, TCLKIN=50ns
MAX_STEPS = +/-[integer(20*47n)] = +/-[integer(940*10E-9)] = +/- 0

Only seeing the "Answer Record: 22414" I understood.
How about changing it to: MAX_STEPS =
+/-[integer(20*10E9*(TCLKIN-3ns))] ?
Is the confusion with the "ns" term in the equation? It was added
only to emphasize that the equation is operating in time, not
frequency.

Now my doubts.
What happens when we overflow the Phase Shifter?
For the same 20MHz clock, MAX_STEPS = +/-940.
And if I shift 941 times (same direction form zero) ?
The output will be phase shifted by 940 steps. The DCM outputs no
longer shift when incremented, but will decrement.

From the data sheet, PSCLK_FREQ (phase shift frequency input) ranges
from 1MHz to 167MHz.
For 1MHz: MAX_STEPS = +/-19940
There must be at least 19940 internal delay taps (for each side)!
So I can go past 940 (the shifter doesn't know the frequency of the
clock, I think).
The phase shift limit is frequency dependent. The equation uses the
clock period, which is inversely proportional to the clock frquency.

The phase shifting range depends on the CLKIN input, not the PSCLK.
The minimum CLKIN frequency is 5 Mz, which equates to +/-3,940 steps.
Each step, called DCM_DELAY_STEP, is between 20 to 40 ps. The VARIABLE
phase shfit mode provide a phase shift range of between +/- (3,940 * 20
ps) to +/- (3,940 * 40 ps) or between +/- 78.8 ns to 157.6 ns.

The confusing difference between the Virtex-II/Spartan-3 variable phase
shifter and the Spartan-3E variable phase shifter is that
Virtex-II/Spartan-3 shifts by fraction of a period, the Spartan-3E
variable phase shift always shifts by time.

The FIXED phase shift mode for Virtex-II, Spartan-3, and Spartan-3E are
always measured in fraction of a clock period.

Again the 20MHz clock.
As MAX_STEPS = +/-940, the phase shift ranges from 940*20ps=18.8ns to
940*40ps=37.6ns, both below 50ns (TCLKIN).
If 940 is the limit, how can the phase shifter, in the fixed mode,
cover all the range from 0 to 2*pi (or 360 degrees, if you prefer)?
In FIXED phase shift mode, the Spartan-3E phase shifter works over the
range -180 degress to +180 degrees. For software compatibility, this
range is mapped to the Virtex-II/Spartan-3 range of -360 to +360
degrees.

I want to know if there is a way of changing the phase continuously,
crossing the borders of +/-2*N*pi smoothly (from 2*pi back to zero).
I have a clarifying question on your question. Are you using VARIABLE
phase shift mode to shift beyond -360 or +360 degrees and asking what
happens when you exceed a full period?

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
Tel: (408) 626-7447
E-mail: steve.knapp@xilinx.com
---------------------------------
The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
 
Chris,
without losing any words during the switching), but would it be possible
to
just multiplex the serial data?
The problem is that no you can't just multiplex the serial data at 1Gbs even
though fundamentally that is all you're trying to do. FPGAs circa 2006 do
not do any logic from external sources at that speed. All you can do is
deserialize then multiplex and re-serialize.

KJ
 
I guess if you cannot answer or help than its much better not to say
anything. I think you need some help in this area :)
 
I suppose Duane is wondering how such a naive ( impossible to answer)
and poorly worded question comes from somebody working in such a
sophisticated company..."interesting"
We all want to be helpful, but I will also point out that posters
should do a little bit of thinking and googling before they embarrass
themselves.
We learned recently that we must be tolerant of "creative spelling"...
Peter Alfke
 
Hi Steven,

"Is the confusion with the "ns" term in the equation? It was added
only to emphasize that the equation is operating in time, not
frequency."
No, TCLKIN is period, it must be given in seconds, no confusion here.
But n (nano) is a number (0.0000000001), so, the equation is wrong. For
the 20M[Hz], the TCLKIN=50n=50000p=0.05u (same number).
Use your calculator or your computer to evaluate the equation, using
TCLKIN=1/FCLKIN (frequency) and you'll see what I mean.

"I have a clarifying question on your question. Are you using VARIABLE

phase shift mode to shift beyond -360 or +360 degrees and asking what
happens when you exceed a full period?"
Yes, I would like to shift beyond +/-2pi (360 degrees). If you look at
"Stratum4E holdover" topic, you'll see what I want to do.
I could use 2 DCMs, and whenever the active DCM reaches the +/-2pi,
switch to the other one (locked at 0 radians). Or, maybe, just reset
the DCM. But it looks like the Spartan3E Frequency-Shifter in the
VARIABLE phase shift mode, can't reach the +/-2pi shifts. Is thet true?

Thanks,

Luiz Carlos
 
I have seen this behaviour. In my case it was enough to set "erase before
programming" check mark in the Impact GUI. Generally speaking, Impact is
full of small bugs, which sometimes make it crash and sometimes it just
wouldn't behave properly. In many cases it is enough to reset the cable and
re-initialize the chain, in other cases you need to restart the program...

/Mikhail


"mughat" <mughat@gmail.com> wrote in message
news:e0ralq$42v$1@news.net.uni-c.dk...
I have installed a XCF08P EEPROM in my fpga board.
The first time i wrote a program to it, it worked fine. But I can not
erase
the EEPROM.
When i write to it now verify fails, I suspect i have to erase it before
writing a new program.

Using: Impact 8.1.03i
JTAG programmer: JTAG 3 i belive (Parallel port), came with a digilent
starter board.

Thanks
Andreas Beier
 
"Fizzy" <fpgalearner@gmail.com> wrote in message
news:1144077660.439014.287360@v46g2000cwv.googlegroups.com...
Well,

I agree with you on that and i think he should put some thought in it
but Interestingly NOT ALL WORKING IN A sophisticated company may be
engineers :) is that right ? and who knows if this person is NOT an
engineer So we all should be tolerent and should be careful in
answering because this is a public forum not a personal area. Plus if
you think its naive and impossible to answer than do not answer .....
Thank you for taking on the job as forum moderator.

Many of us appreciate the time and effort of those who are ready and willing
to contribute to the policing of posts in an effort to make people look
silly.

Again, your time and attention is appreciated.

- John Handwork
 
I'll look into 6.1E. Is it free?

I have been working with the Workspace and Objects windows. Not sure what
Workspace means although I need to click on parts of this for certain
signals to appear in the Objects list. The Workspace has names of my
processes and sometimes line__numbers indicating an immediate assignment.
Too bad I can't see what assignment is made on those lines without double
clicking the line number and bringing up a source window. Perhpas I can
assign labels to these somehow?

"Hans" <hans64@ht-lab.com> wrote in message
news:bDqXf.294$Rm1.182@newsfe6-gui.ntli.net...
I believe that is the sim tab in your workspace. If you change versions I
would go for 6.1e since 6.0 has some annoying GUI bugs (like not
remembering your window layout).

Hans
www.ht-lab.com

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:122qto1lb19mrb8@corp.supernews.com...
In ModelSim 5.7 I would drag or right click items from a pane called
Structure and drag them or add them to the Wave. Where is this or what
is the new procedure for 6.0?

Brad Smallridge
Ai Vision
 
mughat wrote:
I have installed a XCF08P EEPROM in my fpga board.
The first time i wrote a program to it, it worked fine. But I can not erase
the EEPROM.
When i write to it now verify fails, I suspect i have to erase it before
writing a new program.

Using: Impact 8.1.03i
JTAG programmer: JTAG 3 i belive (Parallel port), came with a digilent
starter board.

Thanks
Andreas Beier
I had a similar problem with IMPACT refusing to go past 51% when
programming my XCF02S in the JTAG chain.

A simple upgrade from 8.1 ISE to SP1 fixed it (strangely). I did recall
it working perfectly with the ISE 7.
 
Anyone know if there is an alternative to Impact? that can erase and write
mcs files?
 
"John_H" <johnhandwork@mail.com> wrote in message
news:vIbYf.4674$kg.343@news02.roc.ny...
The newest version (3.0) of the Spartan3E complete data sheet came out a
week or two ago. I just wanted to give my Kudos to the Xilinx folks for
adding the DESIGN NOTE boxes complete with bright yellow attention symbol
to address the design issues that wouldn't be apparent to the casual data
sheet reader.

I've noted before that designers would appreciate full attention to detail
in the data sheet as opposed to relying on the answer records or help line
calls. The notes don't appear to detract from the technical "confidence"
in the devices at all, at least for this engineer. It's fantastic to see
the full disclosure.

Once the device tables specify "logic cells" as opposed to "equivalent
logic cells" I won't have anything to complain about!

- John_H
I second the kudos. I've seen up close the process of creating datasheets
and humongous hardware and software reference manuals for a couple of large
ASICs projects I've worked on. I've also designed the reference
design/development kit boards that were sold to customers. The process was
painful, and a real eye-opener for me. It is extremely difficult to do this
stuff well, especially when you're fabless and work with a foundry, which
means the detailed characteristics for I/O, PLLs, and other major blocks
come from the foundry and/or from IP vendors. At the same time, being
through this taught me to not assume that data sheets and app notes are
always correct. Never forget that human beings write these things, and not
always the super-savvy human beings that some may assume.

Rob
 
Hi Joseph,

Thanks again for your help. Alas, I'm still not having consistent results
with my setup. Sometimes place-and-route will give me a system that passes
the producer-consumer tests, and sometimes it won't. Tiny tweaks in the UCF
file seem to have a large impact success or fail in the final result. (i.e.
if I overconstrain a 100MHz clock to 9.9ns versus 10ns)

Anyway, I'm curious about the solution you found for your system. You
recommended running the BRAMDSOCMCLK input to the dsbram_if_cntlr at 1-4x
the processor clock, right? Where in the data sheet for the controller does
it say this is required? Maybe I've got an older version with EDK 7.1
because I can't find it. You're correct, though, that this clock signal is
passed directly through the controller module and becomes the clock input to
the BRAM (either BRAM_CLK_A or _B).

As far as I can find, the whole point of setting the clock ratio in the
C_DSCNTLVALUE parameter in the dscom module is to allow a *slower* BRAM
clock than PowerPC clock, not a *faster* clock. On the VIIPro, you can go up
to a ratio of 4:1. This is from the PowerPC block reference guide in the
table that shows the ratio of CPMC405CLOCK : BRAMDSOCMCLK.

I guess the problem with clocking the BRAM : PowerPC at a 1:1 ratio is that
it's impossible for me to do. I run my PowerPC's at 300Mhz, and there's no
way I can clock the rest of the controller logic and the 4 BRAMs at that
speed. (The mapper tells me it's impossible even given perfect routing). I'm
actually suprised you were able to route the BRAM successfully at 200MHz, as
the best I can get is maybe 125 MHz given the rest of the contraints of the
design. Good work!

Thanks,

Jeff


"Joseph" <joeylrios@gmail.com> wrote in message
news:1141335040.252179.271460@t39g2000cwt.googlegroups.com...
Not sure if this is relevant to your problem anymore, but I found the
problem with my design (briefly described above). There is only one
signal that can be assigned in the dsbram_if_cntlr, that is
BRAMDSOCMCLK. We were running our PPCs at 200MHz and our PLB bus at
100MHz using proc_clk_s and sys_clk_s, respectively. It was such a
habit to assign all non-processor clks to sys_clk_s, that we did so for
BRAMDSOCMCLK. After reading the data sheet for dsbram_if_cntlr, we
found that the BRAMDSOCMCLK signal needed to be 1-4X the processor clk.
The slow clock we gave to the BRAM caused our unpredictable behavior.
If anything, I have learned to read those data sheets a little better.
This may or may not be the same as your problem, Jeff, but thought I
would follow up with the fix we came up with for our system. We are
running a prodcuer/consumer type system as well and haven't had any
problem with inconsistencies. The shared BRAM is a circular FIFO in
our system. I could provide details on its operation if you still have
trouble with your system.
 
This avnet PCIe board was supposed to be using S3e and it had target
date june 2005.

looks like it is finally ready! there are WAU 8 boards made!
maybe Avnet can make some more til june 2006 so the delay would be only
1 year.

Antti
 
Hi,
At the seminar it was claimed that 1000+ boards were in production so we
will see when it is released.

REGARDS


"Antti" <Antti.Lukats@xilant.com> wrote in message
news:1144138241.151500.56140@i40g2000cwc.googlegroups.com...
This avnet PCIe board was supposed to be using S3e and it had target
date june 2005.

looks like it is finally ready! there are WAU 8 boards made!
maybe Avnet can make some more til june 2006 so the delay would be only
1 year.

Antti
 

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