EDK : FSL macros defined by Xilinx are wrong

[Paul Leventis]

Anandtech ran an article which does quite a good job in explaining the 2
and 3 GB barriers.http://www.anandtech.com/gadgets/showdoc.aspx?i=3034

As mentioned in the Anandtech article, there are stability issues with
running in 3GB mode. We have seen these stability issues with Quartus
on WinXP w/3GB mode. If you need more 2GB of memory for your Quartus
executable, your best bet is to run 32-bit Quartus on (a) 32-bit or 64-
bit Linux or (b) 64-bit Windows.

Regards,

Paul Leventis
Altera Corp.

 

[MM]

"Wei Wang" <camwwang@gmail.com> wrote in message
news:1186135446.310054.313850@g4g2000hsf.googlegroups.com...

What I found was very interesting, it was taking me 12 hours to run
the MAP process before, but yesterday it only took me ~3 hours to run
MAP, and PAR only too took ~40 mins as well.

I was trying to figure out the reasons, then found in *.map *.mrp
files that there was always a map phase which took such a long time as
~10+ hours, and that phrase was always very memory hungry. I was using
Linux64 with 2GB real memory and 4GB swap memory, as I just found that
the real 2GB memory was much smaller than the required peak memory
10.6GB. Yesterday, I was running ISE9.1i for XC5VLX330 on another
Linux64 machine with 11G real memory and 8G swap memory, the there
wasn't any MAP phrase which took a ridiculous ~10+ hours.

Can Xilinx guys shed some more light on the runtime of MAP and PAR,
wrt different memory sizes and CPU cores?

Yes, that indeed would be great!

With my current design I found that timing-driven MAP either crashes or
takes very long time to complete (relative to PAR). Even more interesting is
that I get much better timing and much faster run times by actually
disabling timing-driven mapping and use of RLOC constraints in MAP...

/Mikhail

 

Hello,

Regardless, I got this error while synthesizing a Verilog project. The
problem was that I adopted a project from ISE 7.1.04. After starting a
fresh project on ISE 9.2, handpicking the HDL files and UCFs (and so
on) the synthesis went smoothly.

Maybe this will do the trick for you too.

Eli

 

[Andreas Schwarz]

On 23 Aug., 18:22, eli.billa...@gmail.com wrote:

Regardless, I got this error while synthesizing a Verilog project. The
problem was that I adopted a project from ISE 7.1.04. After starting a
fresh project on ISE 9.2, handpicking the HDL files and UCFs (and so
on) the synthesis went smoothly.

I had the problem with a fresh 9.2 VHDL-only project. Which version of
fixed_pkg did you use? The Xilinx-adapted from http://www.eda-stds.org/fphdl/vhdl.html,
or the original package from the VHDL200x website?

Thanks,
Andreas

 

Is there a text version?

I've never understood the logic of listening to someone drone on in a
thick foreign accent when the same person could just publish the text
or write a web article that we can all read much faster.

Don't engineers read any more?

Lattice is holding a webcast this Wednesday, August 29th, "Tips to
Avoid Simultaneous Switching Output (SSO) Noise Problems." The
presenters will be Troy Scott, from our software marketing group and
Bertrand Leigh, from our applications engineering group.

If you're interested, the event takes place live at 11am Pacific,
18:00 GMT. In addition, you will be able to view this webcast archive
on-demand, at your convenience, within 24 hours after the live event
takes place.

You can register by clicking:
http://www.latticesemi.com/corporate/webcasts/tipstoavoidsimultaneoussw/index.cfm

Bart Borosky, Lattice

 

[Symon]

"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1188263507.145095.110420@q3g2000prf.googlegroups.com...

It has two mutually exclusive signal groups: signals E0, E1 and E2 are
mutually exclusive. So are signals E3, E4 and E5.

The implementation benefits with FPGA are huge !!!

For example:

OutBus has 64-bit width.

OutBusA : process(RESET, CLK)
begin
if(RESET = '1') then
OutBus <= (others=>'0');
elsif(CLK'event and CLK = '1') then
If(E0 = '1') then
OutBus <= Data0;
orif(E1 = '1') then
OutBus <= Data1;
orif(E2 = '1') then
OutBus <= Data2;
orif(E3 = '1') then
OutBus <= Data3;
orif(E4 = '1') then
OutBus <= Data4;
orif(E5 = '1') then
OutBus <= Data5;
end if;
end if
end process;

Hi,

I don't want to get involved in a language crusade, and I don't like to
crosspost so you'll need to read this on CAF, but why not just do something
like this? :-

OutBusA : process(RESET, CLK)
begin
if(RESET = '1') then
OutBus <= (others=>'0');
OutBus1 <= (others=>'0');
OutBus2 <= (others=>'0');
OutBus3 <= (others=>'0');
OutBus4 <= (others=>'0');
OutBus5 <= (others=>'0');
elsif rising_edge(CLK) then
if (E1 = '1') then OutBus1 <= Data1; else OutBus1 <= (others=>'0'); end
if;
if (E2 = '1') then OutBus2 <= Data2; else OutBus2 <= (others=>'0'); end
if;
if (E3 = '1') then OutBus3 <= Data3; else OutBus3 <= (others=>'0'); end
if;
if (E4 = '1') then OutBus4 <= Data4; else OutBus4 <= (others=>'0'); end
if;
if (E5 = '1') then OutBus5 <= Data5; else OutBus5 <= (others=>'0'); end
if;
OutBus <= OutBus1 or OutBus2 or OutBus3 or OutBus4 or OutBus5;
end if
end process;

Google comp.arch.fpga for a thread subject :-

Multidimensional Register in Modul Port List

and read Mr. Bromley's posts.
HTH., Syms.

 

[Gabor]

On Aug 27, 6:25 pm, MikeShepherd...@btinternet.com wrote:

Is there a text version?

I've never understood the logic of listening to someone drone on in a
thick foreign accent when the same person could just publish the text
or write a web article that we can all read much faster.

Definitely with you on this one! I don't even have speakers
connectd to my soundcard. Webcasts to me usually look like a
_VERY_ slowly moving powerpoint slide set, possibly with a
talking head in the corner of the screen.

Where there have been text downloads, they are usually a direct
transcript of the talking head, complete with umms, errrs, etc.

Once again I think the point of webcasts is to force registration
to see who is listening, while avoiding the extra pain of making
a readable informative document. (See recent thread "Annoying").

Just my 2 cents

Gabor

Don't engineers read any more?

Lattice is holding a webcast this Wednesday, August 29th, "Tips to
Avoid Simultaneous Switching Output (SSO) Noise Problems." The
presenters will be Troy Scott, from our software marketing group and
Bertrand Leigh, from our applications engineering group.

If you're interested, the event takes place live at 11am Pacific,
18:00 GMT. In addition, you will be able to view this webcast archive
on-demand, at your convenience, within 24 hours after the live event
takes place.

You can register by clicking:
http://www.latticesemi.com/corporate/webcasts/tipstoavoidsimultaneous...

Bart Borosky, Lattice

 

[Andreas Schwarz]

I installed the ISE service pack 2, and the error message became more
specific:
ERROR:Xst:2744 - "C:/Dokumente und Einstellungen/A/Eigene Dateien/FPGA/
fixpt-test/vhdl200x/fixed_pkg_c.vhdl" line 1026: alias of a function
is not supported.
ERROR:Xst:2683 - Unexpected error found while building hierarchy.

So I commented out the function aliases cleaned up the project files
(otherwise I would get "ERROR:HDLParsers:333 - Binary file "xst/
ieee_proposed/sub00/vhpl02" is corrupted. Recompile unit
fixed_pkg.fixed_pkg."), and everything compiles just fine.

Only division does not work:
ERROR:Xst:769 - "C:/Dokumente und Einstellungen/A/Eigene Dateien/FPGA/
fixpt-test/vhdl200x/fixed_pkg_c.vhdl" line 2599: Operator <INVALID
OPERATOR> must have constant operands or first operand must be power
of 2

Andreas

 

[Weng Tianxiang]

On Aug 28, 3:59 am, "Symon" <symon_bre...@hotmail.com> wrote:

"Weng Tianxiang" <wtx...@gmail.com> wrote in message

news:1188263507.145095.110420@q3g2000prf.googlegroups.com...



It has two mutually exclusive signal groups: signals E0, E1 and E2 are
mutually exclusive. So are signals E3, E4 and E5.

The implementation benefits with FPGA are huge !!!

For example:

OutBus has 64-bit width.

OutBusA : process(RESET, CLK)
begin
if(RESET = '1') then
OutBus <= (others=>'0');
elsif(CLK'event and CLK = '1') then
If(E0 = '1') then
OutBus <= Data0;
orif(E1 = '1') then
OutBus <= Data1;
orif(E2 = '1') then
OutBus <= Data2;
orif(E3 = '1') then
OutBus <= Data3;
orif(E4 = '1') then
OutBus <= Data4;
orif(E5 = '1') then
OutBus <= Data5;
end if;
end if
end process;

Hi,

I don't want to get involved in a language crusade, and I don't like to
crosspost so you'll need to read this on CAF, but why not just do something
like this? :-

OutBusA : process(RESET, CLK)
begin
if(RESET = '1') then
OutBus <= (others=>'0');
OutBus1 <= (others=>'0');
OutBus2 <= (others=>'0');
OutBus3 <= (others=>'0');
OutBus4 <= (others=>'0');
OutBus5 <= (others=>'0');
elsif rising_edge(CLK) then
if (E1 = '1') then OutBus1 <= Data1; else OutBus1 <= (others=>'0'); end
if;
if (E2 = '1') then OutBus2 <= Data2; else OutBus2 <= (others=>'0'); end
if;
if (E3 = '1') then OutBus3 <= Data3; else OutBus3 <= (others=>'0'); end
if;
if (E4 = '1') then OutBus4 <= Data4; else OutBus4 <= (others=>'0'); end
if;
if (E5 = '1') then OutBus5 <= Data5; else OutBus5 <= (others=>'0'); end
if;
OutBus <= OutBus1 or OutBus2 or OutBus3 or OutBus4 or OutBus5;
end if
end process;

Google comp.arch.fpga for a thread subject :-

Multidimensional Register in Modul Port List

and read Mr. Bromley's posts.
HTH., Syms.- Hide quoted text -

- Show quoted text -

Hi Syms,
Your code timing is fundamantally inferior to my code timing.

In your code, you specify 6 groups of data registers, then each bit of
its output registers gets a combinational bit output.

In my code, all 5 groups of signals are combinational signals and
through a carry chain structure in FPGA, the output registers get the
fastest clock-to-output timing result.

Weng

 

[Symon]

Hi Syms,
Your code timing is fundamantally inferior to my code timing.

In your code, you specify 6 groups of data registers, then each bit of
its output registers gets a combinational bit output.

In my code, all 5 groups of signals are combinational signals and
through a carry chain structure in FPGA, the output registers get the
fastest clock-to-output timing result.

Weng

I knew this would happen...

Is this 'fundamentally inferior'?

OutBus1 <= Data1 when (E1 = '1') else OutBus1 <= (others=>'0');
OutBus2 <= Data2 when (E1 = '1') else OutBus2 <= (others=>'0');
OutBus3 <= Data3 when (E1 = '1') else OutBus3 <= (others=>'0');
OutBus4 <= Data4 when (E1 = '1') else OutBus4 <= (others=>'0');
OutBus5 <= Data5 when (E1 = '1') else OutBus5 <= (others=>'0');

OutBus : process(RESET, CLK)
begin
if(RESET = '1') then
OutBus <= (others=>'0');
elsif rising_edge(CLK) then
OutBus <= OutBus1 or OutBus2 or OutBus3 or OutBus4 or OutBus5;
end if
end process;

I think Mike's comment sums it up...

HTH., Syms.

 

[Weng Tianxiang]

On Aug 28, 10:17 am, "Symon" <symon_bre...@hotmail.com> wrote:

Hi Syms,
Your code timing is fundamantally inferior to my code timing.

In your code, you specify 6 groups of data registers, then each bit of
its output registers gets a combinational bit output.

In my code, all 5 groups of signals are combinational signals and
through a carry chain structure in FPGA, the output registers get the
fastest clock-to-output timing result.

Weng

I knew this would happen...

Is this 'fundamentally inferior'?

OutBus1 <= Data1 when (E1 = '1') else OutBus1 <= (others=>'0');
OutBus2 <= Data2 when (E1 = '1') else OutBus2 <= (others=>'0');
OutBus3 <= Data3 when (E1 = '1') else OutBus3 <= (others=>'0');
OutBus4 <= Data4 when (E1 = '1') else OutBus4 <= (others=>'0');
OutBus5 <= Data5 when (E1 = '1') else OutBus5 <= (others=>'0');

OutBus : process(RESET, CLK)
begin
if(RESET = '1') then
OutBus <= (others=>'0');
elsif rising_edge(CLK) then
OutBus <= OutBus1 or OutBus2 or OutBus3 or OutBus4 or OutBus5;
end if
end process;

I think Mike's comment sums it up...

HTH., Syms.

Hi Syms,
1. Are you sure that Xilinx FPGA compiler will generate a carry chain
structure to meet your design requirements? You must pray they would
do so, but with new keyword 'orif' Xilinx FPGA compiler will be
mandated to map 'orif' structure into a carry chain structure without
doubt.

That will be the benefit everyone would enjoy.

Letting a special VHDL language structure refer to a carry chain
implementation in FPGA is a wonderful thing.

2. Which writing pattern between ours is better, more concise and more
impressive with the price of a new keyword 'orif' introduction?

I know that anything can be written in one way or the other in VHDL,
but mutually exclusiveness is an ubiquitous phenomenon and it should
be reflected in VHDL language structure. Its referring to carry chain
in FPGA is really a God's gift, why don't we accept it?

Weng

 

[Jonathan Bromley]

Weng,

I was almost starting to agree with you, until you said this...

with new keyword 'orif' Xilinx FPGA compiler will be
mandated to map 'orif' structure into a carry chain structure without
doubt.
...
Letting a special VHDL language structure refer to a carry chain
implementation in FPGA is a wonderful thing.

This is the purest madness. If you want a language structure
that specifies a particular implementation, you have it already:
it's called a "primitive instance". I agree that a conditional
that is mutually-exclusive by design can readily be mapped to
specific hardware such as MUXCY or a tree of ORs, but the
precise mapping is NOT something we want in the language,
thanks very much. Tools must have the freedom to optimize
as they think best, and must compete (and succeed or fail)
on how effectively they do it.

Language constructs that have built-in assertions for
things that are otherwise hard to describe, such as
mutual exclusivity, are something that is well worth
exploring. Especially now that we have the partially-
successful SystemVerilog example to study, it should be
possible to come up with some interesting ideas. But
please don't blast a hole in your own argument by
demanding that the language construct should have a
one-to-one mapping to some specific piece of technology.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

Hi,

I have a really exciting R&D role with a Media/Broadcast organisation
in the Oxford area.

If you have a solid background of VHDL digital design knowledge and
fancy a move into a busy and exciting industry in Motion Capture then
drop me your CV & contact details........

Salary range is Ł33-38K + excellent benefits and a great working
environment.

My email is kh@waconsultants.com or 01392 666060

Kind regards

Kevin Homeyard
WA

 

[Andrew FPGA]

27 is far too little. I reckon its more like a billion state machines,
or perhaps a bit more these days. Asics and FPGAS(?) can have more
than a billion transistors. A transistor can have at least 2 states
(on or off), so I suppose you can say a transistor is a state machine.

http://www.intel.com/technology/mooreslaw/

 

[Tobias Weingartner]

Weng Tianxiang wrote:

[snip]

Any more question?

What are you smoking? Care to share?

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Jim Granville]

Weng Tianxiang wrote:

I cannot guess the largest number of state machines you have written
for a design, but I know clearly the number of state machines you may
have written in a design is less than 100k. Any question?

More questions? you still have not answered older ones !?

Here is my question again :

So are you talking about a Silicon Ceiling, or a Software Ceiling ?

Since a single FF_CE can be considered a state machine, the silicon
limit will vary with FPGA, and be higher than any
practical requirement.

If there is some lower SW ceiling (that will clearly be SW release
dependant) then that only matters, if it is below someone's real design
needs.

-jg

 

[Jeff Cunningham]

Weng Tianxiang wrote:

No, a single FF_CE is not included in the count. Otherwise my post for
a guessing doesn't make sense.

Weng, it still doesn't make sense! But I hope you continue to post. You
are very entertaining!
-Jeff

 

[Ray Andraka]

Jonathan Bromley wrote:

On Fri, 25 Jan 2008 06:44:10 -0800 (PST),
Ann <thakkar.anuja@gmail.com> wrote:


I just found out that I need random number generator just for
simulation. I do not need to synthesize it. Some feedback on this
would be helpful. I am having a look at some of the links posted here.


OK, that's easy. The math_real package contains an excellent
random number generator that you can adapt for your own purposes.

use ieee.math_real.all;
...
process
variable R: real;
variable S1, S2: positive := 42;
--- seed variables, change initialization to
--- get a different random number stream
begin
...
uniform(S1, S2, R);
...

That's great for testbenching, but it isn't helpful for implementation

in an FPGA.

 

[Symon]

"Rich Grise" <rich@example.net> wrote in message
news:jw6Yi.4461$3j7.554@trnddc02...

On Tue, 06 Nov 2007 13:01:51 -0800, BobW wrote:
...
turbofans. I'll take the extra supplies as the lesser-of-two evils.

If Satan and Lucifer showed up at the inn, and the proprietor rented
them each a room, would he be the lessor of two evils? ;-)

Cheers!
Rich

Rich, maybe he'd be the landlord of the flies?

I'll get my coat...

http://en.wikipedia.org/wiki/Beelzebub#Religious_meaning

 

[Jim Granville]

Symon wrote:

"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message
news:4730b9f2@clear.net.nz...

Also, unlike uC design teams who are very 'analog aware', FPGA development
is rather cocooned in the digital world - Linear stuff !?.

-jg


Hi Jim,

I think that because FPGAs are on the latest and greatest geometry, building
SMPS onto the dice is not a practical proposition. The FPGA manufacturers
(and their customers) want faster, smaller, better. Think of all the LUTs a
4A pfet would replace. Also, I'd trust Linear Tech. to do a much better job
of a SMPS than an FPGA manufacturer.

It's not the area of the 4A PFET, so much as the power flux pouring out
of the thing.
I don't know any uC device that uses a SMPS (well, almost none, there
are a couple that have a niche step-up SMPS, from a single cell, but
that's a differnt target )

So we can all agree regulators are unlikely on the top-end FPGAs,
but they are there on CPLDs, (and uC) where Thermally allowed, and
perhaps they will appear on low power/small package FPGAs ?

eg Will the MAX III have a regulator, for single supply use ?

On the general subject, what FPGA vendors COULD include, is (more?)
Decoupling Caps in the BGA packages, a la Intel processors.

Cheers, Syms.

p.s. I think that John's use of a diode drop for Vccaux is just fine. Simple
and robust. I wonder if the temperature sensing diode that exists in some
FPGAs could be used for this. ;-) (Is that repulsive enough?)

Maybe John can see if both ends of that puppy are floating, and try it !
??

-jg