EDK : FSL macros defined by Xilinx are wrong

[Duth]

On Mar 19, 6:59 am, "Homuncilus" <Sha.Cr...@gmail.com> wrote:

On Mar 19, 11:00 am, "John McGrath" <tail...@gmail.com> wrote:



On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote:

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:

reg signed [15:0] table [0:255];
reg signed [23:0] sum;

integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end

Correct me if I'm wrong, but I believe that this is not valid verilog
- you cannot use an array as a term in the always() sensitivity list,
and the always* implies that the array is in the sensitivity list. I
know that the ncverilogsimulatorwarns about this (but does work). It
states that this is non-portable verilog. Synopsys DC does indeed
synthesize this correctly, but it's not a good idea to use non-
standard verilog statements.ISEseems to err on the side of adhering
to the strict rules of the verilog language. I could be wrong about
this, but from the warning given by ncverilog, I believe this to be
the case. Maybe try a verilog linting tool? formality/conformal should
set you straight, if you have them.
Cheers
John

I think the wrong isn't due to the sensitivity list. Do you sure the
error inISEis caused by that?

Hi,

This is something that was supposed to be supported in ISE XST in
9.1i, although the change did not make it in time.

Thanks
Duth

 

[Andrew Dupont]

Figured it out on my own... EDK doesn't happily mix languages.. remade the top peripheral wrapper in VHDL instead of verilog and it worked right away... GREAT TOOLS!!!

 

[Symon]

"Jim Lewis" <jim@synthworks.com> wrote in message
news:130it10cdc7ocbf@corp.supernews.com...

Mr Tianxiang,
Mr. Jim,

I wonder, should it be Mr. Weng? Perhaps, given his manifest interest in
languages, the Mr. OP can instruct us on the correct etiquette?
Cheers, Mr. Syms.
http://en.wikipedia.org/wiki/Chinese_name

 

[sovan]

On Apr 14, 1:23 pm, "Pedro" <pete.dud...@comcast.net> wrote:

Hello

Has anyone figured out how to program and configure from the Platform Flash on the ML506. I have spent a lot of quality time with the ML505/ML506 Getting Started Tutorial (ug348.pdf) without luck.

There is a dip switch (SW3), the Impact settings and a pair of XCF32P flashes.

I just want to configure from one of the flashes on power up.

If anyone can tell me the exact settings that make the flashes usable I would be very grateful.

Pete

I am using ML505 and I configure the fpga from PROM in Parallel mode.
SW3 Setting is following

1 Off
2 Off
3 Off
4 On
5 Off
6 Off
7 Off
8 Off

ML505 Evaluation Platform User Guide (ug347) Explains the DIP settings
required for different modes of configuration.

-Sovan.

 

[Jim Granville]

[Removed all language groups]

Anson.Stuggart@gmail.com wrote:

I'm designing a debounce filter using Finite State Machine. The FSM
behavior is it follows the inital input bit and thinks that's real
output until it receives 3 consecutive same bits and it changes output
to that 3 consecutive bit until next 3 consecutive bits are received.
A reset will set the FSM to output 1s until it receives the correct
input and ouput.

That's an unusual brief - is this homework ?

This is the test sequence with input and correct output.

1 0 0 1 0 1 0 0 0 1 0 1 1 1 (input)
1 1 1 1 1 1 1 1 0 0 0 0 0 1 (output)

No, it is a partial test sequence. The spec mentions reset, but
the test does not.

The state diagram I came up has 6 states and it's named SEE1, SEE11,
SEE111, SEE0, SEE00, SEE000. I am getting stuck at 11th bit, a 0 in
the input. Because it just came from SEE1 and before SEE1, it came
from SEE000, so at SEE1 it can not change ouput to 1 which is what I
have specified that state's ouput to be.

Anyone knows how to solve this problem? Or maybe there's other better
ways to design the state diagram?

There is probably a better way to specify the state operation

Normally, digital debounce is done with something like a saturating
counter and a toggle or JK result stage.

-jg

 

[ZHI]

The checkram is generated by the IP core generator. Actually it has no
problem in the inital simulation. When I run by step the simulation,
It got the error information.
Newman wrote:

On May 1, 8:41 am, ZHI <threeinchn...@gmail.com> wrote:
Hi,
I want to learn using textio. Here I use Read data from scr.txt to IP
core RAM and Write them to the text1.txt. I wrote the codes here but
it doesn't work. Any suggestions about this is very appreciated.
One more thing, when i use Modelsim to Run by step. It alway gives the
error information and cannot finish the simulation. I don't what it
means.
******************************************************
Trace back: Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6
# while executing
# "error $winName"
# (procedure "view" line 82)
# invoked from within
# "view source"
# (procedure "vsimcmd::viewProcessSource" line 2)
# invoked from within
# "vsimcmd::viewProcessSource /check/uut/u0/select_outputb"
# ("after" script)
# 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6}
# 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6}
**************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity check is
end check;

architecture serial of check is

component checkram
port (
addra: IN std_logic_VECTOR(2 downto 0);
addrb: IN std_logic_VECTOR(2 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0);
wea: IN std_logic);
end component;

signal addra: std_logic_vector(2 downto 0):=(others=>'0');
signal addrb: std_logic_vector(2 downto 0):=(others=>'0');
signal dina: std_logic_vector(7 downto 0) :=(others=>'0');
signal doutb: std_logic_vector(7 downto 0) :=(others=>'0');
signal wea: std_logic :='1';
signal wrd: std_logic :='0';
signal clk : std_logic :='0';
signal reset: std_logic :='1';
file from_file:text open READ_MODE is "src.txt";
file to_text:text open WRITE_MODE is " text1.txt";
begin
UUT:checkram port map
(
addra => addra,
addrb => addrb,
clka => clk,
clkb => clk,
dina => dina,
doutb => doutb,
wea =>wea
);

clock_process: PROCESS
BEGIN
clk <= NOT (clk);
WAIT FOR 5 ns;
END PROCESS clock_process;

reset <= '0' after 1 ns;

ramRd: process (clk,reset)
variable buf_out,buf_in:line;
variable num: std_logic_vector(7 downto 0):=(others=>'0');
variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
begin
if reset='1' then
iptaddr :=(others=>'0');
elsif clk'event and clk='1' then
while not (endfile(from_file))loop

READLINE(from_file,buf_out);
READ(buf_out,num);
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);
wea <='1';
addra<=iptaddr;
dina<= num;
iptaddr:=iptaddr+"1";
end loop;
end if;
end process;
---------------------------------------
addPro: process (addra,reset)
begin
if reset='1' then
wea<='1';
wrd<='0';
elsif addra = "111" then
wea<='0';
wrd <='1';
end if;
end process;
----------------------------------------
output: process(clk,wrd,reset)
variable buf_in:line;
variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
begin
if reset='1' then
addrb <=(others=>'0');

elsif clk'event and clk ='1' then
if wrd <= '1' then
addrb <= addrb+"001";
end if;
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);

end if;
end process;
end serial;

ZHI,
Below is what I got. The src.txt was referenced to my current
modelsim directory. When I created the file, that error went away.
I think the error you got was from the component checkram whose code
you did not post.

Newman

---------------------------------------------------------------------
# //
# Loading C:\eda\Modeltech_6.2c\win32pe/../std.standard
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_1164(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_arith(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_signed(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../std.textio(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_textio(body)
# Loading work.check(serial)
# ** Error: (vsim-7) Failed to open VHDL file "src.txt" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
vhdl_tb/fileio.vhd
# ** Warning: (vsim-3473) Component instance "uut : checkram" is not
bound.
# Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
vhdl_tb/fileio.vhd

 

[austin]

Weng,

If you need spice models for devices, contact your local semiconductor
fabrication house (Chartered, UMC, TSMC, etc..) and request the models
for the technology node you are interested in.

Choices are typically: low power, or high performance (high Vt, low Vt);
130nm, 90nm (the min gate length), and so on.

Generally speaking, these models (which are used by IC designers) are
kept under very strict non-disclosure for new technology nodes.

Depending on how advanced the models are, BSIM 4, or BSIM 4.5 spice
models are the "best" right now, and many are good to use in RF analog
circuits, and have proximity effects, NBTI, and other real world
behaviors modeled, too.

Austin

Weng Tianxiang wrote:

Hi,
Please help.

Where can I find the pass transistor's working curve under 1.2V that
is widely used in IC design preferebly in any articles, instead of in
books?

Thank you.

Weng

 

[Petter Gustad]

Andy <jonesandy@comcast.net> writes:

Unless you are prototyping an ASIC (and want portability of the code
to ASIC tools), I would not recommend Synopsys for FPGA synthesis.

Which tool are you talking about? DC, FPGA Compiler, FPGA Compiler II,
or DC-FPGA? The latest Synopsys tool in the FPGA-camp was DC-FPGA, but
they terminated the product long time ago. A bit pity I think because
it was great to have an ASIC flow acompatible FPGA synthesis tool.


Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[ZHI]

Yeah, I guess it is the problem of the IP core RAM. I wander if the ip
core RAM can be simulated in ModelSim.
When I removed the IP core RAM part, and just using textio read and
write, that will be no problem.
cpope wrote:

"Newman" <newman5382@yahoo.com> wrote in message
news:1178032912.349257.47850@e65g2000hsc.googlegroups.com...
On May 1, 10:50 am, "cpope" <cep...@nc.rr.com> wrote:
I have a new board where I switched from the xcf08p to the xcf32p serial
prom devices. The 32p programs fine and when I cycle power the current
jumps
up and my test led lights which should mean that the fpga is configured.
However, the PPC in the v4fx12 device is dead or not running. Running
XMD
returns all zeros for the processor ID and I get no output from my
bootloader code.

Downloading the fpga manually works fine.

One other difference is that I'm using the revision select lines on the
32p
where I didn't on the 08p but the lines are both set correctly and it
does
appear that the fpga loads but then freezes. Any ideas what might cause
this?

Thanks,
Clark


Clark,
Don't understand the relationship to this thread but I found
something on the Xilinx website that may or may not be related to what
you are seeing. I did not read the errata.

--------------------------------------------------------------------------
---------------------
XCF08P, XCF16P, & XCF32P Errata and Deviations from the Data Sheet
Intermittent Power Ramp Fa


A test escape has been discovered with the devices named above which
for some applications results in device failure during "Power on Reset
Activation." Devices that have a VCCint ramp during "Power on Reset
Activation" that takes longer than 1ms to reach 1.6V may see failures.

Associated Products: Configuration PROMs
--------------------------------------------------------------------------
----------------------

Newman


Thanks, but I get the same result whether I run from Impact or whether I
power cycle the board. When I'm using Impact the board power supplies should
be well settled so I don't think it's anything to do with transients at
power up. -Clark

 

[Newman]

On May 1, 2:08 pm, ZHI <threeinchn...@gmail.com> wrote:

The checkram is generated by the IP core generator. Actually it has no
problem in the inital simulation. When I run by step the simulation,
It got the error information.



Newman wrote:
On May 1, 8:41 am, ZHI <threeinchn...@gmail.com> wrote:
Hi,
I want to learn using textio. Here I use Read data from scr.txt to IP
core RAM and Write them to the text1.txt. I wrote the codes here but
it doesn't work. Any suggestions about this is very appreciated.
One more thing, when i use Modelsim to Run by step. It alway gives the
error information and cannot finish the simulation. I don't what it
means.
******************************************************
Trace back: Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6
# while executing
# "error $winName"
# (procedure "view" line 82)
# invoked from within
# "view source"
# (procedure "vsimcmd::viewProcessSource" line 2)
# invoked from within
# "vsimcmd::viewProcessSource /check/uut/u0/select_outputb"
# ("after" script)
# 2: ::tkerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6}
# 1: ::bgerror {Error opening C:/Documents and Settings/zq500/Local
Settings/Temp/xil_1700_6}
**************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity check is
end check;

architecture serial of check is

component checkram
port (
addra: IN std_logic_VECTOR(2 downto 0);
addrb: IN std_logic_VECTOR(2 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0);
wea: IN std_logic);
end component;

signal addra: std_logic_vector(2 downto 0):=(others=>'0');
signal addrb: std_logic_vector(2 downto 0):=(others=>'0');
signal dina: std_logic_vector(7 downto 0) :=(others=>'0');
signal doutb: std_logic_vector(7 downto 0) :=(others=>'0');
signal wea: std_logic :='1';
signal wrd: std_logic :='0';
signal clk : std_logic :='0';
signal reset: std_logic :='1';
file from_file:text open READ_MODE is "src.txt";
file to_text:text open WRITE_MODE is " text1.txt";
begin
UUT:checkram port map
(
addra => addra,
addrb => addrb,
clka => clk,
clkb => clk,
dina => dina,
doutb => doutb,
wea =>wea
);

clock_process: PROCESS
BEGIN
clk <= NOT (clk);
WAIT FOR 5 ns;
END PROCESS clock_process;

reset <= '0' after 1 ns;

ramRd: process (clk,reset)
variable buf_out,buf_in:line;
variable num: std_logic_vector(7 downto 0):=(others=>'0');
variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
begin
if reset='1' then
iptaddr :=(others=>'0');
elsif clk'event and clk='1' then
while not (endfile(from_file))loop

READLINE(from_file,buf_out);
READ(buf_out,num);
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);
wea <='1';
addra<=iptaddr;
dina<= num;
iptaddr:=iptaddr+"1";
end loop;
end if;
end process;
---------------------------------------
addPro: process (addra,reset)
begin
if reset='1' then
wea<='1';
wrd<='0';
elsif addra = "111" then
wea<='0';
wrd <='1';
end if;
end process;
----------------------------------------
output: process(clk,wrd,reset)
variable buf_in:line;
variable iptaddr: std_logic_vector(2 downto 0):=(others=>'0');
begin
if reset='1' then
addrb <=(others=>'0');

elsif clk'event and clk ='1' then
if wrd <= '1' then
addrb <= addrb+"001";
end if;
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);

end if;
end process;
end serial;

ZHI,
Below is what I got. The src.txt was referenced to my current
modelsim directory. When I created the file, that error went away.
I think the error you got was from the component checkram whose code
you did not post.

Newman

---------------------------------------------------------------------
# //
# Loading C:\eda\Modeltech_6.2c\win32pe/../std.standard
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_1164(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_arith(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_signed(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../std.textio(body)
# Loading C:\eda\Modeltech_6.2c\win32pe/../ieee.std_logic_textio(body)
# Loading work.check(serial)
# ** Error: (vsim-7) Failed to open VHDL file "src.txt" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
vhdl_tb/fileio.vhd
# ** Warning: (vsim-3473) Component instance "uut : checkram" is not
bound.
# Time: 0 ps Iteration: 0 Region: /check File: C:/work/Projects/
vhdl_tb/fileio.vhd- Hide quoted text -

- Show quoted text -

--------------------------------------------------------------------------------------------------
# invoked from within
# "vsimcmd::viewProcessSource /check/uut/u0/
select_outputb" <<===
# ("after" script)
# 2: ::tkerror {Error opening C:/Documents and Settings/zq500/
Local
Settings/Temp/xil_1700_6}

I believe the <<=== points to something in the checkram uut
component. My initial thought was that embedded spaces in the path
might be causing some problem (Documents and Settings)... some tools
have problems with this. Can't remember if Modelsim does.

Since I cannot duplicate the problem, I am at a loss to help you.

Newman

 

[Andy]

On May 1, 1:33 pm, Petter Gustad <newsmailco...@gustad.com> wrote:

Andy <jonesa...@comcast.net> writes:
Unless you are prototyping an ASIC (and want portability of the code
to ASIC tools), I would not recommend Synopsys for FPGA synthesis.

Which tool are you talking about? DC, FPGA Compiler, FPGA Compiler II,
or DC-FPGA? The latest Synopsys tool in the FPGA-camp was DC-FPGA, but
they terminated the product long time ago. A bit pity I think because
it was great to have an ASIC flow acompatible FPGA synthesis tool.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

The last time I tried (i.e. was told) to use it was a couple of years
ago (dc-fpga). Good riddance, as far as I'm concerned.

Thanks,

Andy

 

[Weng Tianxiang]

On May 1, 11:16 am, austin <aus...@xilinx.com> wrote:

Weng,

If you need spice models for devices, contact your local semiconductor
fabrication house (Chartered, UMC, TSMC, etc..) and request the models
for the technology node you are interested in.

Choices are typically: low power, or high performance (high Vt, low Vt);
130nm, 90nm (the min gate length), and so on.

Generally speaking, these models (which are used by IC designers) are
kept under very strict non-disclosure for new technology nodes.

Depending on how advanced the models are, BSIM 4, or BSIM 4.5 spice
models are the "best" right now, and many are good to use in RF analog
circuits, and have proximity effects, NBTI, and other real world
behaviors modeled, too.

Austin



Weng Tianxiang wrote:
Hi,
Please help.

Where can I find the pass transistor's working curve under 1.2V that
is widely used in IC design preferebly in any articles, instead of in
books?

Thank you.

Weng- Hide quoted text -

- Show quoted text -

Hi Austin,
Actually what I need is not a precise latest pass transistor working
curve. I thought it were available somewhere such that I has requested
the latest version. What I really need is a typical V-I or V-V working
curve of any typical pass transistor to learn some basic, not
sophisticated characteristics.

I think it should be availble somewhere and not a commercial secret.
Because I think pass transistors are one of the most basic elements in
IC industry and it should be included in any IC textbooks. I don't
know which textbook contains the latest information about it.

Thank you.

Weng

 

[austin]

Weng,

Any mosfet model should be adequate for what you need.

There is no difference between a "pass transistor" model, and any other
kind of spice mosfet model.

Austin

 

[Weng Tianxiang]

On May 1, 6:32 pm, austin <aus...@xilinx.com> wrote:

Weng,

Any mosfet model should be adequate for what you need.

There is no difference between a "pass transistor" model, and any other
kind of spice mosfet model.

Austin

Hi Austin,
Do you have any idea where I can get a graph of it? I just want the
graph showing the relationship between input and output.

Thank you.

Weng

 

[Jonathan Bromley]

On 1 May 2007 18:50:32 -0700,
Weng Tianxiang <wtxwtx@gmail.com> wrote:

Do you have any idea where I can get a graph of it? I just want the
graph showing the relationship between input and output.

Why not simulate one in any of the free versions of SPICE?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Weng Tianxiang]

On May 2, 12:41 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On 1 May 2007 18:50:32 -0700,

Weng Tianxiang <wtx...@gmail.com> wrote:
Do you have any idea where I can get a graph of it? I just want the
graph showing the relationship between input and output.

Why not simulate one in any of the free versions of SPICE?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan,
What I need is a graph of pass transistor's working curving that must
be available in some books or articles. I have no Spice experiences
and even don't know what proper parameters should be.

Weng

 

[Jonathan Bromley]

On 2 May 2007 03:54:52 -0700,
Weng Tianxiang <wtxwtx@gmail.com> wrote:

What I need is a graph of pass transistor's working curving that must
be available in some books or articles.

Weng,

sorry, it's been a while since I looked in detail at this
kind of stuff. There is some nice information on the use
of pass switches for digital applications in the technical
notes for QuickSwitch devices:

http://www.idt.com/products/files/7591/quickswitch_basics.pdf
http://www.idt.com/products/files/7528/TN_07.pdf

I'm sure this is not everything you need, but perhaps it will put
you on the right track. Of course, the exact behaviour will depend
strongly on the details of the pass transistor itself - gate
threshold, etc.

Note that QuickSwitch devices use single NMOS pass transistors.
For basic information on CMOS pass structures, try

http://www.fairchildsemi.com/ds/CD/CD4066BC.pdf

although that part is fairly ancient history now.

I have no Spice experiences
and even don't know what proper parameters should be.

If you are concerned about the detailed analog behaviour
of pass transistors, I suggest you *should* get some
SPICE experience, double-quick!

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[austin]

Weng,

1. Learn spice
2. Use spice.

Austin

Weng Tianxiang wrote:

On May 2, 12:41 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com
wrote:
On 1 May 2007 18:50:32 -0700,

Weng Tianxiang <wtx...@gmail.com> wrote:
Do you have any idea where I can get a graph of it? I just want the
graph showing the relationship between input and output.
Why not simulate one in any of the free versions of SPICE?
--
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Hi Jonathan,
What I need is a graph of pass transistor's working curving that must
be available in some books or articles. I have no Spice experiences
and even don't know what proper parameters should be.

Weng

 

[cpope]

Turns out I had to change the bitgen option to drive the done pin. Must have
been marginal or the pull up strength is different between the xcf08p and
xcf32p proms. Mystery solved. -Clark

"cpope" <cepope@nc.rr.com> wrote in message news:...

I have a new board where I switched from the xcf08p to the xcf32p serial
prom devices. The 32p programs fine and when I cycle power the current
jumps
up and my test led lights which should mean that the fpga is configured.
However, the PPC in the v4fx12 device is dead or not running. Running XMD
returns all zeros for the processor ID and I get no output from my
bootloader code.

Downloading the fpga manually works fine.

One other difference is that I'm using the revision select lines on the
32p
where I didn't on the 08p but the lines are both set correctly and it does
appear that the fpga loads but then freezes. Any ideas what might cause
this?

Thanks,
Clark

 

[Joseph H Allen]

In article <1178200419.714442.227530@l77g2000hsb.googlegroups.com>,
romi <weberrm@gmail.com> wrote:

On May 2, 9:11 am, jhal...@TheWorld.com (Joseph H Allen) wrote:
// Concise priority arbiter
input [26:0] req; // Bit zero is highest priority
wire [26:0] gnt = req & -req; // Isolate least significant set bit

reg [26:0] prev; // Previous winner (saved from last cycle)
wire [26:0] req1 = req & ~((prev - 1) | prev); // Mask off previous winners
wire [26:0] gnt1 = req1 & -req1; // Select new winner
wire [26:0] winner = |gnt1 ? gnt1 : gnt; // Start from bit zero if none

// Save previous winner
always @(posedge clk) if (winner) prev <= winner;

Since gnt1 implies that there was a req1, wouldn't it be better
(faster) to use req1 in the winner selection?

wire [26:0] winner = |req1 ? gnt1 : gnt; // Start from bit zero if
none

Yes. Cool.

Here are some other variations:

If the carry chain is really fast, get rid of the mux:

wire [53:0] req1 = { req, req & ~((prev - 1) | prev) };
wire [53:0] gnt1 = req1 & -req1;
wire [26:0] winner = gnt1[53:27] | gnt1[26:0];

Or use wrap-around carry, if you don't mind the combinatorial loop:

// Rotate previous winner one bit to the left. If no previous winner,
// pretend it was prev[26].
wire [26:0] prev1 = |prev ? { prev[25:0], prev[26] } : 27'd1;

// Wrap-around two's complement where the add 1 is just to the left of the
// previous winner instead of at bit 0.
wire [27:0] tmp = { 1'b0, ~req } + ({ 1'b0, prev1 } | { 27'b0, tmp[27] });

wire winner = req & tmp[26:0];

This is probably the fastest, but you need a synthesis tool which allows
combinatorial loops.

--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}