EDK : FSL macros defined by Xilinx are wrong

[fjh-mailbox-38@galois.com]

Eric Smith writes:

Problem 3.

The average software designer couldn't describe
two gates and flip flop in C (or any other programming language), but
would instead describe something that synthesizes to a large
collection of gates and flip-flops.

Solution 3:

Several steps are required:

(a) Provide source-level hardware resource profiling, so that
developers using high-level languages for hardware design
can determine how much each part of their source code contributes
to the overall resource costs.

(b) Provide documentation of recommended HLL idioms for generating
efficient hardware.

(c) Ensure that the high-level language used for hardware design has a
way of expressing constructs that will map directly down to the
each of the available hardware resources, such as LUTs and
flip-flops,
so that programmers can if necessary manually transform their
code
to optimize it at a fairly low level without having to switch to
a different
programming language.

(d) Implement compiler optimizations to perform as many as possible of
these transformations automatically, or by means of pragmas or
compilation
options, rather than requiring the programmer to perform the
transformations
manually.

--
Fergus J. Henderson "I have always known that the pursuit
Galois Connections, Inc. of excellence is a lethal habit"
Phone: +1 503 626 6616 -- the last words of T. S. Garp.

 

[Bob Perlman]

On 14 Nov 2005 14:49:49 -0800, "fjh-mailbox-38@galois.com"
<fjh-mailbox-38@galois.com> wrote:

Mike Treseler writes:

Problem 1.

There are ten times as many software designers
as digital hardware designers.

Solution 1:

Develop high-level languages for hardware design. Make these similar
enough to existing software development practices that developers only
need a general understanding of hardware optimization techniques (e.g.
pipelining, resource sharing, etc.), available hardware resources (e.g.
LUTs
and BlockRAMs), and how high-level language constructs map onto those
hardware resources. Then one hardware engineer can easily train up 10
software engineers to the level of hardware knowledge that they need in
order
to be able to productively develop efficient hardware using a
high-level language.

Would it be possible to do just the opposite, and create a high-level
language that lets a digital designer write efficient,
high-performance software the same way he'd design hardware? Because
I'd like to become an expert programmer without expending much effort.

Bob Perlman
Cambrian Design Works

 

[derek]

Hi,
You may also want to look at the GNAT design which was featured in the following
Xilinx Xcell Journal.
http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm

This design uses the JTAG port of the FPGA as a communication channel from a PC to
the logic in your design. You can use it as an interface to the PicoBlaze.

The GNAT design is available for download for free from here.
http://www.s3group.com/system_ic/gnat/

Derek



Dhivya wrote:

hi..
i am tryin to interface the pico blaze from SPRATAN III to a computer
and hvin some trouble..can ny 1 guide me/??

 

[derek]

Hi,
You can use the JTAG port of the FPGA to read back the contents
of any BRAM. However you will need to build some custom logic into
your design to enable this. Firstly you will need logic to talk to the
JTAG port of the FPGA and secondly you will need logic to read the appropriate
BRAM and pass the contents to the JTAG port.
Furthermore you will need software on your PC to capture the data read back through the
JTAG port.

The following Xcell article describes the GNAT design which illustrates how
you can use the JTAG port of a Xilinx FPGA to communicate with the internals
of your design.
http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm

The GNAT example design is available for download free from
http://www.s3group.com/system_ic/gnat/

Derek


giohdl@netscape.net wrote:

Hi all.
I'm using a Virtex2 fpga which uses a lot of BRAMs.
The design modifies the content of these BRAMs during elaboration.
Is it possible to dynamically readback the BRAMs contents in a text
file using JTAG?
I've read the Xilinx documentation (impact) but I can't find a simple
and fast solution.
Can anybody help me?
Thanks.

 

[backhus]

PiyushG schrieb:

Hi all
I have problem in designing a circuit which is recursive

Suppose i am designing a schematic of BRLSHIFTER and suppose i want
assign all outputs to inputs then what changes should I made in ".vhf"
file?

Thanking you

Hi Piyush,

first of all...why do you want to manipulate your *.vhf file?
if you are designing a schematic, you can use your schematic editor,
which creates a *.sch file. The *.vhf file is generated from the
schematic file, and might be overwritten by the IDE.

Now, if you already have designed your barrelshiftersave it, go back to
the ide and generate a symbol out of the schematic (Look under design
entry tools). Open a new schematic and place the barrel schifter symbol
there. Well, now you are free to connect the outputs to the inputs with
a bus or wires, if it makes any sense.
Maybe you should think about a multiplexer, to feed in your initial data
and then switch to the feedback, and a register would be nice to prevent
a combinatorial loop, if your barrel shifter doesn't already have it.



At last please tell me what you mean by "recursive"? Recursion is not
equal to feeding data back into a function (block), which can be seen as
looping. In software it only works, because you have lots of RAM and
your function can allocate new workspaces (for variables etc.) until the
problem deepth is reached and the results can be accumulated somehow on
the way back to the first calling function, or...until your ram limit is
reached. (Without thinking about the stack)
This is a virtual behavior. Workspaces are created as needed.
How should that happen in hardware? Function blocks do not virtually pop
out of nowhere.
It is surely possible to create a hardware that behaves to a certain
limit like a recursive algorithm, but then, only a very limited number
of algorithms need real recursion. In software mostly everything can be
expressed different, though not even as elegant.

have a nice synthesis
Eilert

 

[Brian Davis]

john wrote:

with my version of ISE, I can not put the IOB attribute on a signal

I rebuilt that example 6.3 project I'd posted a link to, using 7.1SP4

The IOB attribute worked just fine (note 1); the tristate controls are
properly replicated and all registers show up in the IOBs.

I get the error
ERROR:HDLParsers:1202 - "/home/XXX/XXX/XXX.vhd" Line 210. Redeclaration of symbol tristate_enable_reg. --

That message sounds like the synthesizer is choking on a coding

problem. Do you have duplicate (identical) names for both a process
and a signal, or something similar ?

Brian

Note 1:
There is a 7.1iSP4 bug with assigning IOSTANDARDs and LOCS
using HDL attributes. Unused LOC'd inputs drop their IOSTANDARD
definitions and default back to LVCMOS25, causing banking errors.
To make that example project compile, make the following change to
<ram_test.vhd> to avoid any unused inputs:

-- seg_dp <= '1';
seg_dp <= sw(5) OR sw(4) OR sw(3) OR sw(2) OR sw(1) OR sw(0)
OR pb(1) OR pb(0);

 

[Krzysztof Przednowek]

Hi,
Thanks for answers.

1) does the board worj when you use Avnet ref design image ?

There was no reference design for PCI included. But I believe board

works. Everything else works fine. Currently I'm workin on some kind of
PCI monitor, to see what is going on.

2) the 24ma would not help, you have some problem with your core that
is the reason for the freeze

I think that is something with my core, too. I was asking about

current, to be sure that electrical part of design is good.

and I suggest you start testing and analyzing some existing and
working PCI design before trying your own, and for your
own core make sure it works in testbench

I've try to test my core with Altera'a testbench from their
evaluation version of PCI compiler... But they set clk and data and
everything
else in the same time. How it could posible to sample data on rising
clk, when data are set up in the same time? And they use adresses (in
config read/write) with oldest bit set, why?

Best regards
Krzysztof Przednowek

 

[PeteS]

Much depends on the drive that can be provided by the FPGA, so I would
need to know the specific device.

The effective output resistance depends on the driver characteristics.

Note that at those frequencies, terminating the lines is not optional
with a distributed bus, and impedance controlled address / data /
control would be an exceedingly good idea.

Cheers

PeteS

 

[Eric Smith]

Adrian Knoth wrote:

BTW: backticks are deprecated, use $() instead

Deprecated? Why bother? It's not like they can remove the backtick
feature from the shell without breaking a bazillion existing scripts.

They can have my backtick when they pry it out of my cold, dead shell
scripts.

 

[fad]

Hi,
I can suggest a user group hosted by cadence, spetraquest.com. You can
post your queries out there regarding EMI issues and can get the
answers from experts.
Regards,
Fahad

 

[Gabor]

adnan.aziz@gmail.com wrote:

i everyone,

i'm teaching a vlsi design class, and we're covering datapath this
week.

we use weste and harris' new edition of "cmos vlsi design". it's a
great book; however, it doesn't discuss actual delays/area costs for
adders, multipliers, dividers, etc., and the other sources i've looked
at tend to be focused on asymptotics (O(log N) type analyses).

does anyone know off the top of their heads what the actual delay/area
numbers are like on a modern FGPA for the following:

- addition, multiplication, division

- 16/32/64 bit

- number of pipeline stages for these implementations.

i'd also be interested in knowing correspondnig values for floating
point arithmetic,

suggestions for survey articles would be welcome

thanks in advance,

adnan

Area in a "modern FPGA" for arithmetic varies widely, due to the recent
addition of dedicated blocks for multiply/accumulate functions. If
you're only
interested in functions using the FPGA fabric, your best bet is to use
COREgen (or some other vendor's equivalent IP generator) to make the
functions you want. The Xilinx version allows you to see the resulting
coverage if you check the "Display Core Footprint" box in the dialog
for the core. Most cores allow you to check off whether to use
dedicated
hardware if the FPGA family has it, the alternative being to generate
the function using only the fabric (LUTs and flip-flops).

The nice thing about the core generator is that you don't actually need
to build the project to see the resource requirements. If you don't
have
ISE with COREgen, you can get some representative usage values from
the IP function datasheets, mostly available at the Xilinx IP center.

 

[ALuPin@web.de]

I have no tristate enable signal available to define something like
IIC_SCL_2V <= '1' WHEN Tristate_enable='1' ELSE 'Z';
IIC_SCL_2V_HELP <= IIC_SCL_2V;

 

[Austin Lesea]

Nichael,

There are many books on E&M theory that detail the basis for calculating
cross-talk, but I am not sure that is going to help you at all.

Of more interest is calculating quickly the cross-talk coupling that you
actually have in your system?

To do that, it is a question of which tools to use.

A few simplistic formulas from a textbook will give you the theory, but
they will not be useful in finding what the actual cross-talk is.

A complete and accurate solution to any E&M problem can be found by
packages such as Ansoft's field solvers. Next on my list would be
Sigrity's modeling software. Cadence and Mentor both have signal
integrity packages which will extract parameters from your printed
circuit board, and report the cross-talk. One of my favorites is
Mentor's Hyperlynx which is a lower cost (and lower featured) version of
the more powerful (and capable) signal integrity tool suites -- and is
very easy to use.

Of course, spice has the W, T, and U transmission line models, and each
model is useful for different reasons. Not all model types are
supported by all versions of spice ('hspice' has them all).

For theory, I use Ramo, Whinnery, and Van Duzer "Fields and Waves in
Communications Electronics" only because I took the course from Whinnery
~30 years ago.

Austin

Michael Chan wrote:

I'm looking for a good book that goes deeply into theory about transmission
lines and crosstalk in high speed communications systems. If anyone has any
good references, please let me know.

I have the book High-Speed Digital Design by Howard Johnson, which has some
good stuff in it, but I'm looking for another reference which gives detailed
attention to crosstalk. In particular, how crosstalk is modelled, and
methods for mitigating crosstalk.

Thanks in advance,

Michael.

 

[Nicolas Matringe]

ALuPin a écrit:

I have no tristate enable signal available to define something like
IIC_SCL_2V <= '1' WHEN Tristate_enable='1' ELSE 'Z';
IIC_SCL_2V_HELP <= IIC_SCL_2V;

Open-drain are outputs, not inputs (an I˛C interface should have bidir
pins, though, but that's another problem). High-impedance has nothing
to do with inputs.
The usual way is to have an internal signal (called scl_out for
example) that drives the pin's output enable:

scl <= '0' when scl_out = '0' else 'Z';

Nicolas

 

[calaf]

I think that CLK0 and CLK90 has the same frequency as the input clk.
Regards

 

[Mike Treseler]

adnan.aziz@gmail.com wrote:

i'm teaching a vlsi design class, and we're covering datapath this
week.
does anyone know off the top of their heads what the actual delay/area
numbers are like on a modern FGPA for the following:

That might have to be a different class.
It seems to me that custom cmos design and
fpga design have very little in common
in terms of primitive elements.

-- Mike Treseler

 

[Andrew Lohbihler]

<brassaro@iro.umontreal.ca> wrote in message
news:1132178625.633742.197620@o13g2000cwo.googlegroups.com...

Forgot to mention that i am using EDK 6.3i.

Check the synthesis report for details, if you have not already done so.
Sometimes errors don't appear inthe dialog but in the report for which there
are various in ISE. Also, check to see if your connections are complete,
perhaps none are recognized. If all fails try opening a web support issue
with Xilinx. This can take time but the response often hits the heart ofthe
problem.

-Andrew

 

[Andrew Lohbihler]

"sjulhes" <t@aol.fr> wrote in message
news:437b395e$0$10968$626a14ce@news.free.fr...

Hi !

I installed ISE and EDK 6.2i with SP3, and ISE as a stange behavior.
When I go through steps synthesis, P&R and .bit generation every thing is
ok.
If I launch impact or if I swap to another windows application and back to
ISE, all green marks go back to ? and ISE launches the wholel flow !!!!
It is a big waste of time !

Does anyone has a clue ?

Just one point, there was a ISE 6.3 install on this computer which was not
removed correctly.

Thank you.

Stéphane.

Try using the "Run All" option after right-clicking in iMPACT and see what
happens. Could be that you have a corrupted version of ISE 6.2 for which
later modules (i.e. ISE 6.3) are in your setup. I would uninstall everything
from the Xilinx folder and reinstall from scratch, but saving your projects
using the archive option. Also make sure you are using Win XP or 2K pro.
-Andrew

 

[brassaro@iro.umontreal.ca]

I checked the reports, and no other info except the one I posted is
given. What bothers me also is that synthesis works on altera tools,
like Quartus II. Could it be an error that Quartus does not find in the
design, or is it a bug in Xilinx tools?

 

[Bob Perlman]

On Thu, 17 Nov 2005 17:19:17 +1000, "Michael Chan"
<mchan@itee.uq.edu.au> wrote:

I'm looking for a good book that goes deeply into theory about transmission
lines and crosstalk in high speed communications systems. If anyone has any
good references, please let me know.

I have the book High-Speed Digital Design by Howard Johnson, which has some
good stuff in it, but I'm looking for another reference which gives detailed
attention to crosstalk. In particular, how crosstalk is modelled, and
methods for mitigating crosstalk.

Thanks in advance,

Michael.

I strongly recommend "Signal Integrity Simplified" by Eric Bogatin.
It's well-written, and manages to go into a lot of detail without
overwhelming the SI newcomer. And there's a 68-page chapter on
crosstalk.

Bob Perlman
Cambrian Design Works