EDK : FSL macros defined by Xilinx are wrong

[Ray Andraka]

Tobias Weingartner wrote:

In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:


as example VQ100 is really nice package very thin, so largest LUTs you get
in VQ100 is S3e. etc..



I realize that there are people out there that need the 1000+ pin packages
that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
would come in VQ100/144 packages. Personally, I'd love to have the capacity,
but I really dont need (or want) the complexity and raw bandwidth of having
to deal with several hundred (or a thousand) pins...



Unfortunately, the size of the cavity in those small packages is far too

small to fit the die for the high density parts, and even if it did fit,
you may have power dissipation issues as well.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Antti Lukats]

"Vanheesbeke Stefaan" <svhb@pandora.be> schrieb im Newsbeitrag
news:xb2cf.42389$vo1.2039857@phobos.telenet-ops.be...

Hello,

What tools do I need for changing an outsourced dising from a 3020A to a
3030A Xilinx device (the 3020A is obsolete).

I only have a XNF netlist available.

Thanks

I just checked that I can compile an 'Logic Assembler' source file until
..BIT using Foundation 1.5i for the P&R

I guess that you can run Foundation implementation on the XNF as well.

The 'ISE Classics' that are available from Xilinx website do not support
3030A

Antti

 

[Jecel]

Thanks Jim and Antti for clearing that up.

-- Jecel

 

[Gabor]

aydin3w@gmail.com wrote:

Is it possible to drive global clock routing networks with an internal
signal on a Virtex-E FPGA?

I am trying to develop data/strobe enoding on an Virtex-E FGPA. It is
required that data and strobe signals are XORed to obtain a clock
signal. Then this clock signal will be fed to other logic in the FPGA.
Therefore I need to use the XORed signal to use as a clock signal.

Thanks for your replies.

Virtex-E is similar to other Xilinx devices and has internal global
clock buffers (BUFG) that can be driven by logic such as an XOR
gate as well as an external pin. In fact routing to the global buffer
is not even restriced to the global clock input pins, but for external
clock sources the input delay is significantly less on these global
pins.

If your signals to be XOR'd are external, you don't gain this advantage
by using the global clock inputs as the routing must first go to a LUT
using non-global resources. In this case it is better to use
non-global
I/O pins to feed your XOR gate.

It is also possible to run logic signals to a DLL in ther Virtex-E
parts. You
may need to set the XIL_MAP_ALLOW_ANY_DLL_INPUT environment
variable for this. Also this only works for free-running clocks that
meet
the minimum/maximum frequency limits of the DLL. So if your XOR clock
doesn't form a constant clock of fixed period you can't take advantage
of
the DLL.

Good luck,
Gabor

 

Ray Andraka wrote:

Tobias Weingartner wrote:

In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:


as example VQ100 is really nice package very thin, so largest LUTs you get
in VQ100 is S3e. etc..



I realize that there are people out there that need the 1000+ pin packages
that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
would come in VQ100/144 packages. Personally, I'd love to have the capacity,
but I really dont need (or want) the complexity and raw bandwidth of having
to deal with several hundred (or a thousand) pins...



Unfortunately, the size of the cavity in those small packages is far too
small to fit the die for the high density parts, and even if it did fit,
you may have power dissipation issues as well.

--
--Ray Andraka, P.E.

any idea how big the dies are?, what will fit in a vq100, the only
thing I could find on the web was something like 3x3mm sounds small
for a 10x10 package?

-Lasse

 

[Bevan Weiss]

langwadt@ieee.org wrote:

Ray Andraka wrote:
Tobias Weingartner wrote:

In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:


as example VQ100 is really nice package very thin, so largest LUTs you get
in VQ100 is S3e. etc..


I realize that there are people out there that need the 1000+ pin packages
that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
would come in VQ100/144 packages. Personally, I'd love to have the capacity,
but I really dont need (or want) the complexity and raw bandwidth of having
to deal with several hundred (or a thousand) pins...



Unfortunately, the size of the cavity in those small packages is far too
small to fit the die for the high density parts, and even if it did fit,
you may have power dissipation issues as well.

--
--Ray Andraka, P.E.

any idea how big the dies are?, what will fit in a vq100, the only
thing I could find on the web was something like 3x3mm sounds small
for a 10x10 package?

-Lasse

That sounds about right to me.
You've got to remember there's a tolerance on the die placement, so the
interior die 'room' needs to be larger, then you've got the anchor space
for the pins themselves and then the added space for the wirebonds.

BGAs can accommodate much larger dies given equivalent sizing to QFP etc
etc. They don't require any room for wirebonds in almost all cases.

 

[mughat]

What does this "Intellectual Property" actually mean. is it like copyright?
Is it the oposite of opencores ?

<allanherriman@hotmail.com> wrote in message
news:1131431142.314073.177710@o13g2000cwo.googlegroups.com...

mughat wrote:


Intellectual Property.

http://www.acronymfinder.com/af-query.asp?String=exact&Acronym=ip&Find=Find

Regards,
Allan

 

[Bevan Weiss]

mughat wrote:

What does this "Intellectual Property" actually mean. is it like copyright?
Is it the oposite of opencores ?

It means some implementation of an idea that is not actual property (ie
not physical) but is being represented or sold as a physical quantity.

ie you can buy an IP core from someone, but that doesn't entitle you to
any rights other than the usage of this core and possible redistribution
based on royalties etc. You can't disclose the contents of the core, or
attempt to reverse engineer it, much like a standard product.

 

[Adam Megacz]

"IP Core" is often [mis]used even when the writer does not mean to
exclude public domain or open source works. For this reason, the term
"gateware" is preferred unless you intend to deliberately exclude
noncommercial creations.

http://en.wikipedia.org/wiki/Gateware

- a


"mughat" <mughat@gmail.com> writes:

What does this "Intellectual Property" actually mean. is it like copyright?
Is it the oposite of opencores ?

allanherriman@hotmail.com> wrote in message
news:1131431142.314073.177710@o13g2000cwo.googlegroups.com...
mughat wrote:


Intellectual Property.

http://www.acronymfinder.com/af-query.asp?String=exact&Acronym=ip&Find=Find

Regards,
Allan

--
PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380

Q: "Won't the pendulum swing back?"
A: "It has never been a pendulum. Think tectonic plates instead."
-- from patrick.net

 

[Athena]

Hi all,

I mean that how to use the registers and fifo when I am creating my own IP core. How to transfer data with my ip core.

Thank you.

Athena

 

[Philip Freidin]

On Tue, 08 Nov 2005 13:59:57 GMT, "Vanheesbeke Stefaan" <svhb@pandora.be> wrote:

Hello,

What tools do I need for changing an outsourced dising from a 3020A to a
3030A Xilinx device (the 3020A is obsolete).

Are you changing the design, or just migrating from one device size to
another? I would have thought that if the 3020A was unavailable, the
3030A would also be unavailable

http://www.fpga-faq.org/FAQ_Pages/0009_Xilinx_sw_versions.htm

I only have a XNF netlist available.

If you are not changing the design, then this is a simple edit
of this file where the part number is specified. Look for a line
like this:

PART, 3020APC84-100

and change it to

PART, 3030APC84-100

then re-run place and route and bitstream generate.

If you are changing the design as well, then this will make a very
difficult project, extremely difficult. As this is all you have,
you will have to edit this netlist, which can be done, but it was
never designed for.

Thanks

While this may not be what you want to hear, you may be better off
figuring out your desired function, and starting a new design with
current products. This is not easy either, as you probably have
existing boards, and everything runs at 5V . There are no current
products that will fit into the old footprint of the 3020A, and
almost none of the current products tolerate 5V.

Good luck,

Philip

 

[Anthony Ellis]

Hi Kevin,

I can't figure your explanation. Even if you wnated to step (in clock cycles) the IO enable could still be in the IOB! Using an internal FF, with defined placement and routing, gives control of scew within the same cycle - if you wanted it!

Anthony.

 

[Simon Peacock]

its important to note that IF you ever user a reset on a shift register, the
a SRL16 CAN'T be inferred as it doesn't have a reset!

"Ray Andraka" <ray@andraka.com> wrote in message
news7Jbf.2$Mi5.0@dukeread07...

Antti Lukats wrote:

AGREE 100%

SRL16 is way useful but I do not see it nearly possible that they will be
used the best
way with regular synthesis. so the customer should be at least aware of
what
is needed
to get the SRL16 being used (automatically) or then use them directly.

Antti



Current synthesis pretty much only instantiates the SRL16 as a fixed
length shift register, and then only if the designer didn't put resets
on the registers. There is supposedly a magic incantation in Synplicity
that will infer a dynamic shift, but for th elife of me I have not been
able to get it to infer that consistently, and the words to the
incantation seem to change with each revision of the software. I find
it to require less effort just to instantiate the SRL16, especially if
you are actually using the dynamic capability. Also, a common mistake
with inferred fixed length shift registers is the synthesis often does
not infer a flip-flop at the SRL16 outputs, which kills clock
performance. Synplify will put a flip-flop at the output of a delay,
but if you have a register deeper than 17 clocks, it strings together
SLR16's with no flip-flops between, which again kills the performance.
(This may have been fixed in later versions, I haven't checked).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Simon Peacock]

Now including the core generator in webpack would defiantly be a plus

Simon

"Eric Smith" <eric@brouhaha.com> wrote in message
news:qh8xw082b2.fsf@ruckus.brouhaha.com...

I just found this article by accident, and haven't seen this information
widely publicized:

http://www.esp2000.ro/articol.php?id_ar=2850

Summary:

There won't be a BaseX version of 8.1i. However, BaseX customers still
in-warranty will be offered an upgrade to full ISE Foundation for
$1495.
Alternatively, they can transition to WebPack 8.1i with no loss of
functionality.

WebPack 8.1i will still be available at no charge, and will have all
the
features that BaseX had. In particular, it will support all the
devices formerly supported by BaseX, and will also now include the
FPGA Editor, ISE Simulator Lite, and CORE Generator.

Disclaimer: that's just what I found in the article, and I have no idea
how accurate the information is.

Eric

 

[Bob Perlman]

Peter -

On 9 Nov 2005 11:30:24 -0800, "Peter Alfke" <peter@xilinx.com> wrote:

I think I wrote that article in XCell.
If you follow the reasoning, you will agree that it has to apply to all
CMOS manufacturing. It is not even Xilinx-specific.
Assuming the best-case (min) delay to be a quarter of the worst case
(max) delay still seems to be a conservatively realistic assumption.

My real question is:
Why do you care? What are you gambling on?
Min delays do not matter in a synchronous design.

Sure, they do. You need them to calculate hold margins. Even if the
receiving device's hold time is zero (and sometimes it isn't), you
need to ensure that clock skew doesn't exceed minimum path delay.

I'm not just trying to be picky here--this is important.

Bob Perlman
Cambrian Design Works

 

[Jim Granville]

Peter Alfke wrote:

I think I wrote that article in XCell.
If you follow the reasoning, you will agree that it has to apply to all
CMOS manufacturing. It is not even Xilinx-specific.
Assuming the best-case (min) delay to be a quarter of the worst case
(max) delay still seems to be a conservatively realistic assumption.

My real question is:
Why do you care? What are you gambling on?
Min delays do not matter in a synchronous design.

On the same die, probably not, in absolute number terms, but
some min delay is necessary.

However, move across die and process, and it can become
important if some devices HOLD times have finite
post-edge windows.

-jg

 

[Peter Alfke]

Yes, I agree.
Inside the chip, we make sure that the delay tolerances on a global
clock are less than the min delay clock-to-Q, and we can guarantee
that, since delays track inside the chip.
Between chips, the min delay is important since the clock delay
differences are determined by the pc-board, and the transmitting device
may also have nothing in common with the receiving device (neither
temperature nor processing, although probably voltage).

That's why source-synchronous design is now popular (sending the clock
together with the data) and IDELAY in Virtex-4 gives you the ability to
delay clock or data by a precise amount, so that you can achieve
near-optimal relative timing.
Peter Alfke

 

[Jon Elson]

Vanheesbeke Stefaan wrote:

"Philip Freidin" <philip@fliptronics.com> wrote in message
news:kjp2n1hrhl6jvmldnbapl8mjcd3hs0v202@4ax.com...


While this may not be what you want to hear, you may be better off
figuring out your desired function, and starting a new design with
current products. This is not easy either, as you probably have
existing boards, and everything runs at 5V . There are no current
products that will fit into the old footprint of the 3020A, and
almost none of the current products tolerate 5V.




The bad thing is that we need a last production batch of 500 pieces for
spare parts, the project is dead already for some time ...





If you only need 500 parts, one last time, and never again, have you checked

all the "obsolete parts specialists"? There are outfits that have huge
stocks
of old Xilinx parts. I don't use parts this old, but still use some 5 V
original
Spartan chips, and these outfits have been quite helpful. Highmont in
Australia was the last outfit I used.

Jon

 

[Jon Elson]

JASH wrote:

Hi...
I am having a quite similar issue...
I am using FPGA board Gigilent XS10... with xilinx spartan
FPGA.XCS10...
I used FS 1.5e and FS2.1E... But then I downloaded web pack 6.xx.
Surpeise was that this version didnot supported Spartan XCS10, not even
Spartan -II.... I wish Xilinx Management should think on that, although
they have made the components obsolete, but poor people like us are
still learning on the same...
Well then... what to do next... What i did was a little nasty....
Webpack 6.xx supported Vertex - II... And so did previous version FS
3.3 (which a good man donated me). I made my design in 6.xx on device
V-II, opened the project in FS 3.3 and then changed the device to
Spartan XCS10-PC84..... It worked... Just remenber that keep the gate
count under final target device.... and configure the pinouts in each
implementation repeatedly.....
If u have XNF file it should work... but can you send me little more
detail on versions... I am a little shaky in understanding your
requirements.


Wow! This is an amazing discovery! I've been using a 1997 or so version of

ISE so I can keep support of the old 5V parts.

Jon

 

[Peter Alfke]

You can also try
syracusesemiconductors.com
or call them at
603-897 1280
and ask for Joe. Very helpful guy.
Peter Alfke