EDK : FSL macros defined by Xilinx are wrong

[Jim Granville]

Bob Perlman wrote:

On 9 Oct 2006 11:57:12 -0700, "KJ" <Kevin.Jennings@Unisys.com> wrote:

In any case, nobody has articulated yet the application that really
does require specified reset behaviour PRIOR to the clock starting thus
requiring use of the async reset (with the exception of the reset
signal synchronizer flip flop itself).

Uh, I did. Took me 20 minutes to type it up, too. I'm not exactly
sure what the disagreement is: if you have FFs controlling TriState
enables, you should initialize them asynchronously. Whether that's
done by an end-of-config reset or some other reset signal doesn't
really matter--you need the asynchronous reset.

And I didn't even get to the open-the-bomb-bay-doors and
throw-the-countermeasures-out-the-back-of-the-plane and
start-radiating-the-patient signals. Proper design etiquette demands
that they be initialized immediately, too. (Yes, those signals go
through other interlocks, but as soon as you rely on redundancy, it
ceases to exist.)

Correct, and you also need Async control, in such paths as Watchdog.
If the wdog fires due to clock failure, and your reset is only Sync,
guess what happens next ?
Maybe the FPGA core does not care, but the system design certainly does,
and if the FPGA cannot handle this, then downstream, logic must be added.

-jg

 

[Ray Andraka]

Peter Alfke wrote:

That's why (as I posted earlier) all Xilinx FPGA asynchronously
initiate all flip-flops as part of the initiating and configuration
process, and also keep the outputs 3-stated until configuration is
finished.
Nothing new for you, Bob, but somebody else may have forgotten.
Peter Alfke
====================
Bob Perlman wrote:

On Mon, 09 Oct 2006 00:04:37 GMT, "KJ" <kkjennings@sbcglobal.net
wrote:


"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message
news:1160349835.918930.124340@i42g2000cwa.googlegroups.com...

If you take a step back and realize that you probably shouldn't expect
anything useful out of a part that is not receiving the proper inputs yet
(perhaps by design, after all it could be a power saving measure) then
the
outputs that do not actually reset themselves until the clock does start
up
is not really an issue.

Ok but what if those FPGA outputs can cause problems for other parts of
the system, say if the FPGA is on a bus. Maybe there are some bus
protocols out there where the bus clock can stop, and the peripheral
needs to be able to be reset by the bus master??

Like I said, I don't discount that there may be these cases...but have yet
to hear anyone actually name a specific case where the clock isn't running
but a specific reset condition is required.

Can anyone actually provide one? Hard to believe that such a case doesn't
exist, but also hard to believe that one hasn't been articulated
either....oh well.

How about TriState contention? If I'm controlling TriState buffers
with FFs that aren't initialized until the clock comes along, I run
the risk of turning on more than one set of TriStates on a signal or
bus. And when you're using high-current drivers, this can cause
smoke; I've seen it.

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com

Yup, that's what I do for those cases that need an async reset. The PGM
pin on the FPGA works fine as a reset, as it instantly drives all but a
few pins to hi-Z. FPGAs are not really designed for Async reset; the
tools do not support it very well (timing analysis issues). If it were
up to me, I'd remove the async resets from the internal logic and reap
the increased performance that would result.

 

[Mike Harrison]

An FPGA based camera platform would seem to be entirely on-topic and of potential interest for this
NG. I certainly don't have a problem with people posting info on _relevant_ new products.

 

JeffM wrote:
http://groups.google.com/group/sci.electronics/msg/13651a897337a7a9?q=Charters+misc.industry.electronics.marketplace+Discussions+Advertisement+only-advertise+sci.electronics.design-Electronic-circuit-design

"How NOT to Advertise on Usenet" by Joel K. Furr
http://66.102.9.104/search?q=cache:CMU1z-5ywJ4J:shopsite.com/help/4.1/sc/lte/usenet.html+rude.to.advertise.*.*+*-*-*-*-*-*-the-word-forsale-or-marketplace-in-their-names+preserve.*.culture.of.open.discussion+reads-an-advertisement+*.most.pervasive.form.*.*.*.*-*+How-*-to-Advertise-on-Usenet+biz+hated+rude+lose-*-account

That's all good and gret but we have a number of vendors in the C.A.F
forum regularly spamming by the comon definition, from Xilinx to
various vendors like John Adair's frequent posts for Enterpoint. The
cross posting is mostly likely the offense people care about.

 

[alessandro basili]

Could you please give me a reference for those?

thanks a lot

Al

This isn't different from the "normal" async reset, however, where the
reset signal isn'f filtered. The solution usually used is an external
reset circuit (they come packed in nice tiny ICs these days) that
provides a clean reset signal of 200 ms (or whatever you set it to)
whenever there's a problem with the supplies, and as a byproduct, when
the power is going up.

Eli

 

[Symon]

"Elmo Fuchs" <maerchenprinz@arcor.de> wrote in message
news:4545fdf6$0$5712$9b4e6d93@newsspool3.arcor-online.net...

Because of the restricted amount of available pins on the device I
selected
(Virtex-4 FX40 with 352 user I/Os) I would like to use just one clock
input
on each side of the FPGA, thereby saving clock multiplexer inputs which I
can use as normal GPIOs, and use an external clock multiplexer instead for
my 3 clocks.
Has anyone made experience with such or similar solution? Has anyone used
an
external clock multiplexer device for frequencies up to 500 MHz, yet? Is
there any recommendation which chip I could use for this application in
terms of jitter, etc.? And by the way... is my approach advisable, at all?

Any comments are appreciated.

Regards Elmo

Hi Elmo,

Firstly, I recommend you appreciate Andy's comments. I detect a voice of
experience in his good advice! Then, when you decide to carry on with your
original plan regardless, Google this:-

"Runt Pulse Eliminator" site:micrel.com

HTH, Syms.

 

[Mark McDougall]

Paul Uiterlinden wrote:

Have a look in the ModelSim User's Manual, in chapter 'Compiling
Verilog Files'. There is a paragraph "Handling sub-modules with
common names". It mentions the special meaning of the vsim option
-L work:

Thanks, I'll check it out...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Subroto Datta]

Hi Mark,

The vho file cannot contain both VHDL and Verilog. If it does it is a
bug. Can you email me the vho file that is causing the problem?

Subroto Datta,
Altera Corp.

On Nov 6, 9:46 pm, Mark McDougall <m...@vl.com.au> wrote:

I'm having problems getting a simulation running. Here's the recipe...

Quartus output VHO file - contains VHDL & Verilog components.
Testbench components - VHDL & Verilog components.

Note (and I *think* this is part of the problem) the VHO file contains a
certain verilog modle, whilst the testbench also contains an instance of
the same module, albeit with *different* parameter values.

Attempting to start the simulation under ModelSim ('vsim') loads a bunch
of structures from the library, and then halts with an error that just
does *not* make any sense at all!

The error is "irda_peripheral.v(155) The width (1) of VHDL port
'addr_cnt_out_2' does not match the width (5) of its Verilog connection
(3rd connection)".

This error occurs in the file that contains a 2nd instance of the
verilog module, and the 3rd connection is indeed a vector whose width is
specified with a parameter - which incidently differs from the value for
the instance inside the VHO file.

However:

* addr_cnt_out is internal to the VHO and not connected to the instance
in this file at all.
* neither of the parameters specify a width of '1' for the vector.

I suspect Modelsim is getting confused between the instance in the VHO
file and the instance in irda_peripheral.v and is having trouble wiring
up the ports?!?

Anyone else had a similar experience?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Trevor Coolidge]

They can't back off on the religon - as you note - they think we are dumb.
It is very hard to get ASIC companies to provide a guaranteed delay element,
let alone FPGA companies. There are many applications that need fixed delay
elements. I even remember when a delay element was the standard way for
DRAM timing to be generated.

One way to add an unoptomized buffer is to allocate 2 input pins of the
FPGA. For goodness sakes we have 8-billion pins these days. Externally
pull one high and one low. Then just AND or OR your logic as needed with
these input pins. Since they are static their routing delays are minimal
(and desired). In the end, if they aren't used, just call them "Spare FPGA
Inputs" and everyone will think you thought ahead!

Trevor

They should back off this religious devotion to fully synchronous
logic and give us a couple of dozen programmable true delay elements,
scattered about the chip. But they won't because it's not politically
correct, and because they figure that we're so dumb that we'd get into
trouble using them.


John

 

[mk]

On Sun, 19 Nov 2006 10:30:53 -0800, "Trevor Coolidge"
<tjc-sda@cox.com> wrote:

They can't back off on the religon - as you note - they think we are dumb.
It is very hard to get ASIC companies to provide a guaranteed delay element,
let alone FPGA companies. There are many applications that need fixed delay
elements. I even remember when a delay element was the standard way for
DRAM timing to be generated.

One way to add an unoptomized buffer is to allocate 2 input pins of the
FPGA. For goodness sakes we have 8-billion pins these days. Externally
pull one high and one low. Then just AND or OR your logic as needed with
these input pins. Since they are static their routing delays are minimal
(and desired). In the end, if they aren't used, just call them "Spare FPGA
Inputs" and everyone will think you thought ahead!

Trevor




They should back off this religious devotion to fully synchronous
logic and give us a couple of dozen programmable true delay elements,
scattered about the chip. But they won't because it's not politically
correct, and because they figure that we're so dumb that we'd get into
trouble using them.


John

What John is asking and what're asking are two different things. What
you're asking is not doable at all, at least at a cost you'd be
willing to pay. There are no "guaranteed delay elements" in ASICs. The
delay variation across the whole PVT range is around 4 to 6 times. You
may have programmable delay elements which need to be calibrated (and
recalibrated as temperature and voltage change). I don't think the
reason you don't get this off-the-shelf is political correctness but
self-preservation. If you change processes as often as X & A are
changing and you want the designs to run in the next chip, you have to
use fully synchronous implementations. Absolute delays, with our
without calibration, don't port to different processes too well.

 

[Jim Granville]

mk wrote:

On Sun, 19 Nov 2006 10:30:53 -0800, "Trevor Coolidge"
tjc-sda@cox.com> wrote:


They can't back off on the religon - as you note - they think we are dumb.
It is very hard to get ASIC companies to provide a guaranteed delay element,
let alone FPGA companies. There are many applications that need fixed delay
elements. I even remember when a delay element was the standard way for
DRAM timing to be generated.

One way to add an unoptomized buffer is to allocate 2 input pins of the
FPGA. For goodness sakes we have 8-billion pins these days. Externally
pull one high and one low. Then just AND or OR your logic as needed with
these input pins. Since they are static their routing delays are minimal
(and desired). In the end, if they aren't used, just call them "Spare FPGA
Inputs" and everyone will think you thought ahead!

Trevor





They should back off this religious devotion to fully synchronous
logic and give us a couple of dozen programmable true delay elements,
scattered about the chip. But they won't because it's not politically
correct, and because they figure that we're so dumb that we'd get into
trouble using them.


John



What John is asking and what're asking are two different things. What
you're asking is not doable at all, at least at a cost you'd be
willing to pay. There are no "guaranteed delay elements" in ASICs. The
delay variation across the whole PVT range is around 4 to 6 times. You
may have programmable delay elements which need to be calibrated (and
recalibrated as temperature and voltage change). I don't think the
reason you don't get this off-the-shelf is political correctness but
self-preservation. If you change processes as often as X & A are
changing and you want the designs to run in the next chip, you have to
use fully synchronous implementations. Absolute delays, with our
without calibration, don't port to different processes too well.

They do have delay elements, but they tend to be encapsulated.
There are pin delay elements, and the multi-phase DLLs use
calibrated delays (which is why they are granular).

As part of their operation, the DLLs have to lock and maintain
tracking of temp/process, and I've thought that one thing the
vendors could do, is allow user access to that
calibration/tap pointer register - but that is a niche market.

-jg

 

[Andreas Schallenberg]

Utku Özcan wrote:

...
Tell me from which university and departmant you are, and also your
name, then I can answer your question. Of course for free ;-)
...

The message contained:

Path:
uni-berlin.de!fu-berlin.de!news.maxwell.syr.edu!postnews.google.com!f16g2000cwb.googlegroups.com!not-for-mail

So you already know the university

Andreas

 

[PeteS]

Homer J Simpson wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:icjgm25adv16uhp51ahftmbqpl824dnafh@4ax.com...

Wrong again. Mine were all voluntary students, but the Army paid
the tab.

Actually, I quit teaching long ago since I found out that "Them that
can, do. Them that can't, teach."

Which is far from true. Some of us do it all.

I used to teach formally (and any of us not effectively teaching are
not doing the job right anyway), and my take is:

Those that can, teach.
Those that can't become managers

Cheers

PeteS

 

[Jim Thompson]

On 25 Nov 2006 12:08:01 -0800, "PeteS" <PeterSmith1954@googlemail.com>
wrote:

Homer J Simpson wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:icjgm25adv16uhp51ahftmbqpl824dnafh@4ax.com...

Wrong again. Mine were all voluntary students, but the Army paid
the tab.

Actually, I quit teaching long ago since I found out that "Them that
can, do. Them that can't, teach."

Which is far from true. Some of us do it all.

I used to teach formally (and any of us not effectively teaching are
not doing the job right anyway), and my take is:

Those that can, teach.
Those that can't become managers

Cheers

PeteS

You have it wrong, it's...

Those that can, do.

Those that can't, flip burgers.

Those that can't flip burgers, work check-out at Fry's Electronics.

Those that can't work check-out at Fry's Electronics, teach.

Those that can't teach, become managers.

Those that can't manage, they hang out on S.E.D hiding behind some
hideous nom de plume.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Homer J Simpson]

"PeteS" <PeterSmith1954@googlemail.com> wrote in message
news:1164485281.237408.305840@l12g2000cwl.googlegroups.com...

Which is far from true. Some of us do it all.

I used to teach formally (and any of us not effectively teaching are
not doing the job right anyway), and my take is:

Those that can, teach.
Those that can't become managers

Ain't that the truth!

 

[Homer J Simpson]

"Jim Thompson" <To-Email-Use-The-Envelope-Icon@My-Web-Site.com> wrote in
message news:nu9hm2p9iofkct7kjt6vuo0td93fu2bmb2@4ax.com...

Those that can't manage, they hang out on S.E.D hiding behind some
hideous nom de plume.

"Jim Thompson" isn't THAT hideous a nom de plume.

 

[PeteS]

Jim Thompson wrote:

On 25 Nov 2006 12:08:01 -0800, "PeteS" <PeterSmith1954@googlemail.com
wrote:

Homer J Simpson wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:icjgm25adv16uhp51ahftmbqpl824dnafh@4ax.com...

Wrong again. Mine were all voluntary students, but the Army paid
the tab.

Actually, I quit teaching long ago since I found out that "Them that
can, do. Them that can't, teach."

Which is far from true. Some of us do it all.

I used to teach formally (and any of us not effectively teaching are
not doing the job right anyway), and my take is:

Those that can, teach.
Those that can't become managers

Cheers

PeteS

You have it wrong, it's...

Those that can, do.

Those that can't, flip burgers.

Those that can't flip burgers, work check-out at Fry's Electronics.

Those that can't work check-out at Fry's Electronics, teach.

Those that can't teach, become managers.

Those that can't manage, they hang out on S.E.D hiding behind some
hideous nom de plume.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Amusing

I was actually being serious for a moment. Teachers (as opposed to
lecturers) must have a fire inside if they are actually _teachers_. The
best teachers _are_designers, for that reason. I was not always the
most popular, but I was always the most respected.

I happen to respect your abilities (not that I always say so) because I
know what design takes; indeed I am a designer, of boards not chips. Do
you know what it takes to _really_ teach? (that's not a rhetorical
question).

Cheers

PeteS

 

[Jim Thompson]

On 25 Nov 2006 15:05:26 -0800, "PeteS" <PeterSmith1954@googlemail.com>
wrote:

Jim Thompson wrote:

[snip]

You have it wrong, it's...

Those that can, do.

Those that can't, flip burgers.

Those that can't flip burgers, work check-out at Fry's Electronics.

Those that can't work check-out at Fry's Electronics, teach.

Those that can't teach, become managers.

Those that can't manage, they hang out on S.E.D hiding behind some
hideous nom de plume.

...Jim Thompson

Amusing

I was actually being serious for a moment. Teachers (as opposed to
lecturers) must have a fire inside if they are actually _teachers_. The
best teachers _are_designers, for that reason. I was not always the
most popular, but I was always the most respected.

I happen to respect your abilities (not that I always say so) because I
know what design takes; indeed I am a designer, of boards not chips. Do
you know what it takes to _really_ teach? (that's not a rhetorical
question).

Cheers

PeteS

I taught at a school for technicians from around 1964 until 1974.

And I've given numerous lectures and seminars (I wrote AND taught all
the ICE analog stuff years ago).

I even substituted for Barry Gilbert, when he took ill in 1986 (?,
yep, checked my old passport)), teaching a week-long seminar at the
Royal Melbourne Institute of Technology, teaching bipolar chip design
alongside Willy Sansen, who taught the CMOS stuff.

I offered to teach for free at Scottsdale Community College, but was
turned down... no "teacher's certificate" :-(

And I agree with you, teachers have the "fire". I am where I am now
because of teachers with "fire"... I particularly still fondly
remember Evelyn Truchovesky, my 8th grade Algebra teacher ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[rickman]

What the hell is wrong with you two??? Are you both just 8 years old?
Not only are you annoying everyone who used to read this thread, you
are pissing off all the gay engineers!!!

GROW UP!!!

BTW, I hear that you are both really gay lovers and are acting out your
lover's spat in this forum. :^P


John Fields wrote:

On Sun, 26 Nov 2006 17:53:57 GMT, "Homer J Simpson"
nobody@nowhere.com> wrote:


"John Fields" <jfields@austininstruments.com> wrote in message
news:tltim2t5j1h89hodv7sd9cneapb34uammg@4ax.com...

Or you're trying to dodge, more likely. What I said was that women
liked you (actually, "thought you were pretty" I think was the
phrase) because they considered you to be one of them. Kind of like
a "Will and Grace" arrangement, get it?

No. Never watched it. I've heard a lot of gays do.

---
Then you'd probably enjoy it.


--
JF

 

[Jim Thompson]

On 26 Nov 2006 13:59:35 -0800, "rickman" <gnuarm@gmail.com> wrote:

What the hell is wrong with you two??? Are you both just 8 years old?
Not only are you annoying everyone who used to read this thread, you
are pissing off all the gay engineers!!!

GROW UP!!!

BTW, I hear that you are both really gay lovers and are acting out your
lover's spat in this forum. :^P

Sno-o-o-o-ort! Almost lost my coffee over that one ;-)

John Fields wrote:
On Sun, 26 Nov 2006 17:53:57 GMT, "Homer J Simpson"
nobody@nowhere.com> wrote:


"John Fields" <jfields@austininstruments.com> wrote in message
news:tltim2t5j1h89hodv7sd9cneapb34uammg@4ax.com...

Or you're trying to dodge, more likely. What I said was that women
liked you (actually, "thought you were pretty" I think was the
phrase) because they considered you to be one of them. Kind of like
a "Will and Grace" arrangement, get it?

No. Never watched it. I've heard a lot of gays do.

---
Then you'd probably enjoy it.


--
JF

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.