don\\\'t read this unless you empathize with ...(arg)...

On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface.  As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA.  This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing.  It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data
selector logic. I once did the logic for a hot-spare system in a satcom
central station with a CD4067B.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com
 
On Thu, 5 Nov 2020 14:10:30 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface.  As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA.  This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing.  It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data
selector logic. I once did the logic for a hot-spare system in a satcom
central station with a CD4067B.

Cheers

Phil Hobbs

Is it legal to use an analog mux for logic?

An open-drain decoder makes a nice anything logic block.

I had a job interview where the guy presented me a logic puzzle and I
used a decoder. That annoyed him and he flunked me. Just as well, I
would have wound up living in Los Angeles.
 
On 11/5/2020 3:08 PM, John Larkin wrote:
On Thu, 5 Nov 2020 14:10:30 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface.  As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA.  This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing.  It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data
selector logic. I once did the logic for a hot-spare system in a satcom
central station with a CD4067B.

Cheers

Phil Hobbs

Is it legal to use an analog mux for logic?

An open-drain decoder makes a nice anything logic block.

I had a job interview where the guy presented me a logic puzzle and I
used a decoder. That annoyed him and he flunked me. Just as well, I
would have wound up living in Los Angeles.

There have been reports of coding interviews where the interviewee was
flunked for using a loop to sum the first 20 integers rather than using
n(n + 2)/2 to return the result directly.

They may be flunking people who don\'t know their sequences & series too
well, or who know that premature optimization is the root of all evil,
but whether they\'re flunking bad coders is anyone\'s guess.
 
On 11/5/2020 1:58 PM, Rickster C wrote:
On Thursday, November 5, 2020 at 11:45:55 AM UTC-5, Phil Hobbs wrote:
On 11/5/20 11:18 AM, jlarkin@highlandsniptechnology.com wrote:
On Wed, 4 Nov 2020 23:55:15 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

The server at nntp.olduse.net is serving up selected parts of Usenet
with a 30-year delay. This one from sci.electronics may have some
points of contact for our recent discussions about analogue engineering. ;)

Cheers

Phil Hobbs

On 11/2/90 12:05 PM, Scott T. Dupuie wrote:
In article <11242.2730bfd5@ecs.umass.edu> tohline@ecs.umass.edu
(Chris Tohline) writes:

as a college sophmore I felt very confident about my major, computer
systems engineering. Then, I took a BASIC circuit analysis class.
now, I am very frusterated. Am I lost because my teacher is poor, or
is this just a difficult subject to grasp? I refuse to live with a \'C\'
and am very frusterated. But I\'m sure someday it will click and I\'ll
be happy again.

Chris Tohline

tohline@ecs.umass.edu

Chris,

This has been one of my \"pet peeves\" since I began my education in EE
8 years ago. I am currently completing a M.S. degree in this field, and
have spent some time teaching and working in industry as well. As much as
the academics may object, I can tell you with some certainty that your
introductory circuit analysis course has very little to do with *real*
analog engineering. It seems that most universities like to use this course
as a vehicle for \"weeding out\" what they consider to be unsuitable
students. In addition to this, many of the faculty stuck teaching this
course know very little about the subject as it pertains to real life
design issues. They act as though they are being punished by being forced
to teach this class. This is unfortunate, since it tends to turn off many
young engineering students to the field of analog circuit design. I can\'t
tell you how many students I\'ve known through the years that switched to
digital design (no pun intended) because of the experience thay had in a
similar circuits course. Perhaps this is one of the reasons why there are
so few analog design engineers out there and why they are in such high
demand. I can\'t tell you what to do about your particular situation, but if
you stick it out, as I did, the rewards are many.

Scott T. Dupuie
The Ohio State University
Department of Electrical Engineering
dupuie@parts.eng.ohio-state.edu



I thought freshman chemistry was the classic weeder course.

I can see how a bad instructor handing out bad grades could turn kids
off from analog electronics. It should be fun.

I never took any digital design courses. They looked awfully abstract
to me. Does anyone actually use Karnaugh map minimization?

Once in a great while when I need some bit of glue logic in an
out-of-the-way spot and need good timing, or when I\'ve run out of MCU pins.

It only works up to 4 inputs, but it allows you to use visual pattern
matching, which is quicker and much more fun than Boolean logic
minimization.

There are flexible gate chips (lineal descendents of the classical,
horrible and-or-invert gate) that can do several K maps in one small
package. Typical examples are the SN74LVC1G57 / 58, which between them
can make any 2-input logic function and quite a lot of 3-input ones.

Karnaugh maps can be used with more than 4 inputs. You just need to be able to \"see\" them in 3d. But if you have more than 4 inputs it is highly likely that it can be broken into two, independent maps. The real issue is that hardly anyone ever uses gates on a board other than in PLDs. So a couple of gates in chips for the basic functions, then use a mux for bigger functions, then use a PLD.

This one does up to 6 variables from a truth table, automatically:

<http://www.32x8.com/index.html>

Boolean satisfiability is NP-complete, many more obscure computational
problems are proved to be NP-complete by reducing them to an equivalent
set of BSAT problems.
 
\"John Larkin\" <jlarkin@highland_atwork_technology.com> wrote in message
news:mmm8qf9eakjnpsste7aff3iulv8meg1106@4ax.com...
On Thu, 5 Nov 2020 14:10:30 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would
have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface. As he was
unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA. This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing. It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data
selector logic. I once did the logic for a hot-spare system in a satcom
central station with a CD4067B.

Cheers

Phil Hobbs

Is it legal to use an analog mux for logic?

An open-drain decoder makes a nice anything logic block.

I had a job interview where the guy presented me a logic puzzle and I
used a decoder. That annoyed him and he flunked me. Just as well, I
would have wound up living in Los Angeles.

I was once asked what a mixer does.
Me: \"It multiplies two signals together\".
Interviewer: \"No, what happens is that one signal varies the gain of the
other\".
 
On 11/5/2020 11:45 AM, Phil Hobbs wrote:
On 11/5/20 11:18 AM, jlarkin@highlandsniptechnology.com wrote:
On Wed, 4 Nov 2020 23:55:15 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

The server at nntp.olduse.net is serving up selected parts of Usenet
with a 30-year delay.  This one from sci.electronics may have some
points of contact for our recent discussions about analogue
engineering. ;)

Cheers

Phil Hobbs

On 11/2/90 12:05 PM, Scott T. Dupuie wrote:
In article <11242.2730bfd5@ecs.umass.edu> tohline@ecs.umass.edu
(Chris Tohline) writes:

as a college sophmore I felt very confident about my major, computer
systems engineering.  Then, I took a BASIC circuit analysis class.
now, I am very frusterated.  Am I lost because my teacher is poor, or
is this just a difficult subject to grasp?  I refuse to live with a
\'C\'
and am very frusterated.  But I\'m sure someday it will click and I\'ll
be happy again.

Chris Tohline

tohline@ecs.umass.edu

Chris,

This has been one of my \"pet peeves\" since I began my education in EE
8 years ago. I am currently completing a M.S. degree in this field, and
have spent some time teaching and working in industry as well. As
much as
the academics may object, I can tell you with some certainty that your
introductory circuit analysis course has very little to do with *real*
analog engineering. It seems that most universities like to use this
course
as a vehicle for \"weeding out\" what they consider to be unsuitable
students. In addition to this, many of the faculty stuck teaching this
course know very little about the subject as it pertains to real life
design issues. They act as though they are being punished by being
forced
to teach this class. This is unfortunate, since it tends to turn off
many
young engineering students to the field of analog circuit design. I
can\'t
tell you how many students I\'ve known through the years that
switched to
digital design (no pun intended) because of the experience thay had
in a
similar circuits course. Perhaps this is one of the reasons why
there are
so few analog design engineers out there and why they are in such high
demand. I can\'t tell you what to do about your particular situation,
but if
you stick it out, as I did, the rewards are many.

Scott T. Dupuie
The Ohio State University
Department of Electrical Engineering
dupuie@parts.eng.ohio-state.edu



I thought freshman chemistry was the classic weeder course.

I can see how a bad instructor handing out bad grades could turn kids
off from analog electronics. It should be fun.

I never took any digital design courses. They looked awfully abstract
to me. Does anyone actually use Karnaugh map minimization?

Once in a great while when I need some bit of glue logic in an
out-of-the-way spot and need good timing, or when I\'ve run out of MCU pins.

It only works up to 4 inputs, but it allows you to use visual pattern
matching, which is quicker and much more fun than Boolean logic
minimization.

There are flexible gate chips (lineal descendents of the classical,
horrible and-or-invert gate) that can do several K maps in one small
package.  Typical examples are the SN74LVC1G57 / 58, which between them
can make any 2-input logic function and quite a lot of 3-input ones.

Cheers

Phil Hobbs

The mechanized/computational version of K-mapping, Quine-McCluskey
algorithm, works for arbitrary number of boolean input variables, but
boolean satisfiability is NP-complete so it runs in exponential time.

Not sure exactly how many inputs taps it out on modern consumer hardware
but like the traveling salesman problem it\'s relatively low if one wants
an exact solution, for logic minimization with large numbers of input
variables one must resort to heuristics, genetic algorithms, that sort
of stuff.
 
On 11/5/2020 3:37 PM, bitrex wrote:
On 11/5/2020 11:45 AM, Phil Hobbs wrote:
On 11/5/20 11:18 AM, jlarkin@highlandsniptechnology.com wrote:
On Wed, 4 Nov 2020 23:55:15 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

The server at nntp.olduse.net is serving up selected parts of Usenet
with a 30-year delay.  This one from sci.electronics may have some
points of contact for our recent discussions about analogue
engineering. ;)

Cheers

Phil Hobbs

On 11/2/90 12:05 PM, Scott T. Dupuie wrote:
In article <11242.2730bfd5@ecs.umass.edu> tohline@ecs.umass.edu
(Chris Tohline) writes:

as a college sophmore I felt very confident about my major, computer
systems engineering.  Then, I took a BASIC circuit analysis class.
now, I am very frusterated.  Am I lost because my teacher is poor, or
is this just a difficult subject to grasp?  I refuse to live with
a \'C\'
and am very frusterated.  But I\'m sure someday it will click and I\'ll
be happy again.

Chris Tohline

tohline@ecs.umass.edu

Chris,

This has been one of my \"pet peeves\" since I began my education in EE
8 years ago. I am currently completing a M.S. degree in this field,
and
have spent some time teaching and working in industry as well. As
much as
the academics may object, I can tell you with some certainty that your
introductory circuit analysis course has very little to do with *real*
analog engineering. It seems that most universities like to use
this course
as a vehicle for \"weeding out\" what they consider to be unsuitable
students. In addition to this, many of the faculty stuck teaching this
course know very little about the subject as it pertains to real life
design issues. They act as though they are being punished by being
forced
to teach this class. This is unfortunate, since it tends to turn
off many
young engineering students to the field of analog circuit design. I
can\'t
tell you how many students I\'ve known through the years that
switched to
digital design (no pun intended) because of the experience thay had
in a
similar circuits course. Perhaps this is one of the reasons why
there are
so few analog design engineers out there and why they are in such high
demand. I can\'t tell you what to do about your particular
situation, but if
you stick it out, as I did, the rewards are many.

Scott T. Dupuie
The Ohio State University
Department of Electrical Engineering
dupuie@parts.eng.ohio-state.edu



I thought freshman chemistry was the classic weeder course.

I can see how a bad instructor handing out bad grades could turn kids
off from analog electronics. It should be fun.

I never took any digital design courses. They looked awfully abstract
to me. Does anyone actually use Karnaugh map minimization?

Once in a great while when I need some bit of glue logic in an
out-of-the-way spot and need good timing, or when I\'ve run out of MCU
pins.

It only works up to 4 inputs, but it allows you to use visual pattern
matching, which is quicker and much more fun than Boolean logic
minimization.

There are flexible gate chips (lineal descendents of the classical,
horrible and-or-invert gate) that can do several K maps in one small
package.  Typical examples are the SN74LVC1G57 / 58, which between
them can make any 2-input logic function and quite a lot of 3-input ones.

Cheers

Phil Hobbs



The mechanized/computational version of K-mapping, Quine-McCluskey
algorithm, works for arbitrary number of boolean input variables, but
boolean satisfiability is NP-complete so it runs in exponential time.

Not sure exactly how many inputs taps it out on modern consumer hardware
but like the traveling salesman problem it\'s relatively low if one wants
an exact solution, for logic minimization with large numbers of input
variables one must resort to heuristics, genetic algorithms, that sort
of stuff.

Random aside, the variant of the traveling salesman problem where the
goal is to visit all edges of a graph by the shortest path, rather than
all vertices, is called the Chinese postal-route inspection problem, or
the pen-plotter problem.

Interestingly that variant is not NP-complete, it can be solved in
polynomial time.
 
On 11/5/2020 12:10 PM, Phil Hobbs wrote:
On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface. As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA. This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing. It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most general
way he gave to implement a truth table directly was data selector logic. I
once did the logic for a hot-spare system in a satcom central station with a
CD4067B.

The problem lies with the handling of potential hazards as you can\'t be
guaranteed \"how\" the outputs vary as the inputs are varying; you can only
know where they will \"settle out\".

When I was designing CPUs, I used to rely heavily on using bipolar PROMS to
drive the control signals *inside* the processor. But, the design would
be 100% synchronous so all I had to do was guarantee the outputs would
settle before the next clock setup time -- never use the PROM to generate
\"clocks\".
 
On 11/5/2020 1:22 PM, bitrex wrote:
There have been reports of coding interviews where the interviewee was flunked
for using a loop to sum the first 20 integers rather than using
n(n + 2)/2 to return the result directly.

If they were being hired as a \"coder/programmer\", I\'d just say that this was
a testament to their lack of formal training (what happens when I want you
to sum a billion such values?)

OTOH, if hiring a software engineer, I\'d show them the door in a hearbeat;
coding is such a tiny part of software engineering. Sort of like knowing
how to use a soldering iron...

[This is why you want an interviewee who asks questions instead of just
picking up a pen and writing down the first (only?) solution that comes
to mind.]

They may be flunking people who don\'t know their sequences & series too well,
or who know that premature optimization is the root of all evil, but whether
they\'re flunking bad coders is anyone\'s guess.
 
On 11/5/20 3:08 PM, John Larkin wrote:
On Thu, 5 Nov 2020 14:10:30 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface.  As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA.  This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing.  It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data
selector logic. I once did the logic for a hot-spare system in a satcom
central station with a CD4067B.


Is it legal to use an analog mux for logic?

An open-drain decoder makes a nice anything logic block.

Yup. HC4017s make excellent sequencers in one-offs, too. I often make
quickish analog lockins by turning one switch on in states 0-4 and the
other in states 5-9, with the output integration switched on in 1-4 and
6-9. That way there are no slew artifacts to speak of. A regular
binary counter and a decoder would probably need fewer parts. (It does
change the harmonic sensitivity a bit--even harmonics are still ignored,
but a bit more of the odd harmonics make it in.)

One thing that makes people\'s heads explode when they try to read your
schematics: J-K flipflops. ;) You can do a lot of fun things with
J-Ks--I used them a fair amount back in my satcom days, because at that
point 74S112s were the fastest non-ECL flipflops on the planet.

I had a job interview where the guy presented me a logic puzzle and I
used a decoder. That annoyed him and he flunked me. Just as well, I
would have wound up living in Los Angeles.

And working for somebody with zero flexibility of mind. The guy I
worked for as a post-doc was like that.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com
 
On 11/5/20 3:34 PM, Edward Rawde wrote:
\"John Larkin\" <jlarkin@highland_atwork_technology.com> wrote in message
news:mmm8qf9eakjnpsste7aff3iulv8meg1106@4ax.com...
On Thu, 5 Nov 2020 14:10:30 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would
have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface. As he was
unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA. This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing. It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data
selector logic. I once did the logic for a hot-spare system in a satcom
central station with a CD4067B.

Cheers

Phil Hobbs

Is it legal to use an analog mux for logic?

An open-drain decoder makes a nice anything logic block.

I had a job interview where the guy presented me a logic puzzle and I
used a decoder. That annoyed him and he flunked me. Just as well, I
would have wound up living in Los Angeles.


I was once asked what a mixer does.
Me: \"It multiplies two signals together\".
Interviewer: \"No, what happens is that one signal varies the gain of the
other\".

That\'s why they needed a guy. ;)

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com
 
On 11/5/20 3:49 PM, Don Y wrote:
On 11/5/2020 12:10 PM, Phil Hobbs wrote:
On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would
have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface.  As he was
unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA.  This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing.  It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc.  The next
most general way he gave to implement a truth table directly was data
selector logic.  I once did the logic for a hot-spare system in a
satcom central station with a CD4067B.

The problem lies with the handling of potential hazards as you can\'t be
guaranteed \"how\" the outputs vary as the inputs are varying; you can only
know where they will \"settle out\".

It doesn\'t always matter. If it does, you just resynchronize. An
HC374 is like beer: \"Good for what ails ye, and if nothing ails ye, it\'s
good for that too.\" ;)

In the hot-spare system, the most rapidly-changing inputs were the
alarms from the upstream boards. These indicated stuff like a PLL
approaching the limits of its tuning range, and so were kilohertzy at
the fastest.

When I was designing CPUs, I used to rely heavily on using bipolar PROMS to
drive the control signals *inside* the processor.  But, the design would
be 100% synchronous so all I had to do was guarantee the outputs would
settle before the next clock setup time -- never use the PROM to generate
\"clocks\".

Sure thing. But as always it\'s horses for courses.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com
 
On 11/5/2020 3:54 PM, Don Y wrote:
On 11/5/2020 1:22 PM, bitrex wrote:
There have been reports of coding interviews where the interviewee was
flunked for using a loop to sum the first 20 integers rather than using
n(n + 2)/2 to return the result directly.

If they were being hired as a \"coder/programmer\", I\'d just say that this
was
a testament to their lack of formal training (what happens when I want you
to sum a billion such values?)

OTOH, if hiring a software engineer, I\'d show them the door in a hearbeat;
coding is such a tiny part of software engineering.  Sort of like knowing
how to use a soldering iron...

[This is why you want an interviewee who asks questions instead of just
picking up a pen and writing down the first (only?) solution that comes
to mind.]

If one\'s hiring software engineers it would seem logical to test them on
software engineering, not their knowledge of sequences & series. I\'ve
probably learned and forgot and re-learned n(n + 2)/2 a half-dozen times
over my life.
 
On 11/5/2020 3:54 PM, Don Y wrote:
On 11/5/2020 1:22 PM, bitrex wrote:
There have been reports of coding interviews where the interviewee was
flunked for using a loop to sum the first 20 integers rather than using
n(n + 2)/2 to return the result directly.

If they were being hired as a \"coder/programmer\", I\'d just say that this
was
a testament to their lack of formal training (what happens when I want you
to sum a billion such values?)

OTOH, if hiring a software engineer, I\'d show them the door in a hearbeat;
coding is such a tiny part of software engineering.  Sort of like knowing
how to use a soldering iron...

[This is why you want an interviewee who asks questions instead of just
picking up a pen and writing down the first (only?) solution that comes
to mind.]

A solution that well-satisfies the stated requirements of the problem
but doesn\'t satisfy some further unstated requirement that turns up
later is just the kind of client or employer you may not want to work
for and is something that is complained about with respect to questions
asked here all the time.
 
On Thu, 5 Nov 2020 13:49:16 -0700, Don Y <blockedofcourse@foo.invalid>
wrote:

On 11/5/2020 12:10 PM, Phil Hobbs wrote:
On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface. As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA. This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing. It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most general
way he gave to implement a truth table directly was data selector logic. I
once did the logic for a hot-spare system in a satcom central station with a
CD4067B.

The problem lies with the handling of potential hazards as you can\'t be
guaranteed \"how\" the outputs vary as the inputs are varying; you can only
know where they will \"settle out\".

When I was designing CPUs, I used to rely heavily on using bipolar PROMS to
drive the control signals *inside* the processor. But, the design would
be 100% synchronous so all I had to do was guarantee the outputs would
settle before the next clock setup time -- never use the PROM to generate
\"clocks\".

One rather large organization in Texas was designing an \"advanced
scientific computer\" and did not allow the presets or the clears of
any flops to be used, not even at powerup.

The project was a failure but did result in a superior way to shoot
rubber bands. Several marriages resulted.
 
On 11/5/20 1:58 PM, Rickster C wrote:
On Thursday, November 5, 2020 at 11:45:55 AM UTC-5, Phil Hobbs
wrote:
On 11/5/20 11:18 AM, jlarkin@highlandsniptechnology.com wrote:
On Wed, 4 Nov 2020 23:55:15 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

The server at nntp.olduse.net is serving up selected parts of
Usenet with a 30-year delay. This one from sci.electronics
may have some points of contact for our recent discussions
about analogue engineering. ;)

Cheers

Phil Hobbs

On 11/2/90 12:05 PM, Scott T. Dupuie wrote:
In article <11242.2730bfd5@ecs.umass.edu
tohline@ecs.umass.edu (Chris Tohline) writes:

as a college sophmore I felt very confident about my
major, computer systems engineering. Then, I took a BASIC
circuit analysis class. now, I am very frusterated. Am I
lost because my teacher is poor, or is this just a
difficult subject to grasp? I refuse to live with a \'C\'
and am very frusterated. But I\'m sure someday it will
click and I\'ll be happy again.

Chris Tohline

tohline@ecs.umass.edu

Chris,

This has been one of my \"pet peeves\" since I began my
education in EE 8 years ago. I am currently completing a
M.S. degree in this field, and have spent some time teaching
and working in industry as well. As much as the academics
may object, I can tell you with some certainty that your
introductory circuit analysis course has very little to do
with *real* analog engineering. It seems that most
universities like to use this course as a vehicle for
\"weeding out\" what they consider to be unsuitable students.
In addition to this, many of the faculty stuck teaching this
course know very little about the subject as it pertains to
real life design issues. They act as though they are being
punished by being forced to teach this class. This is
unfortunate, since it tends to turn off many young
engineering students to the field of analog circuit design.
I can\'t tell you how many students I\'ve known through the
years that switched to digital design (no pun intended)
because of the experience thay had in a similar circuits
course. Perhaps this is one of the reasons why there are so
few analog design engineers out there and why they are in
such high demand. I can\'t tell you what to do about your
particular situation, but if you stick it out, as I did, the
rewards are many.

Scott T. Dupuie The Ohio State University Department of
Electrical Engineering dupuie@parts.eng.ohio-state.edu



I thought freshman chemistry was the classic weeder course.

I can see how a bad instructor handing out bad grades could turn
kids off from analog electronics. It should be fun.

I never took any digital design courses. They looked awfully
abstract to me. Does anyone actually use Karnaugh map
minimization?

Once in a great while when I need some bit of glue logic in an
out-of-the-way spot and need good timing, or when I\'ve run out of
MCU pins.

It only works up to 4 inputs, but it allows you to use visual
pattern matching, which is quicker and much more fun than Boolean
logic minimization.

There are flexible gate chips (lineal descendents of the classical,
horrible and-or-invert gate) that can do several K maps in one
small package. Typical examples are the SN74LVC1G57 / 58, which
between them can make any 2-input logic function and quite a lot of
3-input ones.

Karnaugh maps can be used with more than 4 inputs. You just need to
be able to \"see\" them in 3d.

Well, of course you could draw a KM on a tesseract or other
higher-dimensional scribbler. I have some on order, but the lead time
is pretty long....

But if you have more than 4 inputs it is highly likely that it can be
broken into two, independent maps. The real issue is that hardly
anyone ever uses gates on a board other than in PLDs. So a couple of
gates in chips for the basic functions, then use a mux for bigger
functions, then use a PLD.

Depends on the speed, though, and they still sell a metric buttload (*)
of glue logic chips.

Cheers

Phil Hobbs

(*) or possibly a troy crap-ton. ;)

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com
 
On 11/5/2020 2:34 PM, bitrex wrote:
On 11/5/2020 3:54 PM, Don Y wrote:
[This is why you want an interviewee who asks questions instead of just
picking up a pen and writing down the first (only?) solution that comes
to mind.]

If one\'s hiring software engineers it would seem logical to test them on
software engineering, not their knowledge of sequences & series. I\'ve probably
learned and forgot and re-learned n(n + 2)/2 a half-dozen times over my life.

But you\'d likely remember that you KNEW such a thing and would strive to
recall it (or, rederive it). Employment exams are rarely very difficult;
this is intentional. The point is to draw out how the applicant approaches
the problem, not how well he happens to know the syntax of a particular
implementation language.

[Note that sum of 1..n is actually n(n+1)/2; you\'d have tested that, in
your head, before committing to it, on paper. If I saw you doing an
exercise like that, I\'d inquire as to what you were doing and why -- and
already have my \"answer\"... even if you ended up with the wrong expression
(cuz I know you\'d EVENTUALLY get it)]
 
On 11/5/2020 2:38 PM, bitrex wrote:
[This is why you want an interviewee who asks questions instead of just
picking up a pen and writing down the first (only?) solution that comes
to mind.]

A solution that well-satisfies the stated requirements of the problem but
doesn\'t satisfy some further unstated requirement that turns up later is just
the kind of client or employer you may not want to work for and is something
that is complained about with respect to questions asked here all the time.

If the potential employer changed the goal-posts during/after the problem
was posed, you can simply condition your answer based on that additional
information.

Telling an applicant to sort a list -- and, LATER, telling him that the
items in the list are 200 character strings -- can be used to force
the applicant to consider tweeks to his implementation when the cost
of \"moving\" an item is considerably increased. How he addresses this
shows that he understands the cost of copies, etc.
 
On 11/5/2020 2:20 PM, Phil Hobbs wrote:
On 11/5/20 3:49 PM, Don Y wrote:
On 11/5/2020 12:10 PM, Phil Hobbs wrote:
On 11/5/20 1:49 PM, Don Y wrote:
On 11/5/2020 11:22 AM, Edward Rawde wrote:
I\'ve seen people use expensive chips when a diode and resistor would have
been fine.

But then I was introduced to logic gates as diodes, resistors and the
occasional transistor if an inverter was needed.

A fellow I worked with designed a graphic LCD interface. As he was unsure
of the exact logic required to derive a few of the control signals, he
installed an *EPROM* to act as a crude PLA. This let him release the
board to manufacturing while he tinkered with the contents of the EPROM.

I looked at the functionality that it was effectively providing. It
(and the time to PROGRAM it!) could be replaced by a quad NAND and hex
inverter.

shakes head

Don L talks about doing that in the CMOS Cookbook, iirc. The next most
general way he gave to implement a truth table directly was data selector
logic. I once did the logic for a hot-spare system in a satcom central
station with a CD4067B.

The problem lies with the handling of potential hazards as you can\'t be
guaranteed \"how\" the outputs vary as the inputs are varying; you can only
know where they will \"settle out\".

It doesn\'t always matter. If it does, you just resynchronize. An HC374 is
like beer: \"Good for what ails ye, and if nothing ails ye, it\'s good for that
too.\" ;)

Yes, but it introduces another \"delay element\" -- important when you\'re
designing a processor and are concerned with the execution time (clocks)
of each opcode.

Amusingly, there are some cases where adding another delay element can let you
dramatically increase clock frequency so, even though you now require X+1
clocks to complete an operation, that operation can potentially take HALF
the actual time that it did, previously!

In the hot-spare system, the most rapidly-changing inputs were the alarms from
the upstream boards. These indicated stuff like a PLL approaching the limits
of its tuning range, and so were kilohertzy at the fastest.
 
On 11/5/2020 6:39 PM, Don Y wrote:
On 11/5/2020 2:34 PM, bitrex wrote:
On 11/5/2020 3:54 PM, Don Y wrote:
[This is why you want an interviewee who asks questions instead of just
picking up a pen and writing down the first (only?) solution that comes
to mind.]

If one\'s hiring software engineers it would seem logical to test them
on software engineering, not their knowledge of sequences & series.
I\'ve probably learned and forgot and re-learned n(n + 2)/2 a
half-dozen times over my life.

But you\'d likely remember that you KNEW such a thing and would strive to
recall it (or, rederive it).  Employment exams are rarely very difficult;
this is intentional.  The point is to draw out how the applicant approaches
the problem, not how well he happens to know the syntax of a particular
implementation language.

The question wasn\'t on what the interviewee did or didn\'t know about
closed forms of sums of series it was about writing a function to sum
the first 20 integers. Which they did adequately.

It was a simple solution for a simple problem, seems like a perfectly
valid approach to me. And a modern optimizing compiler may even be able
to optimize them both to the same code for small inputs.

[Note that sum of 1..n is actually n(n+1)/2; you\'d have tested that, in
your head, before committing to it, on paper.  If I saw you doing an
exercise like that, I\'d inquire as to what you were doing and why -- and
already have my \"answer\"... even if you ended up with the wrong expression
(cuz I know you\'d EVENTUALLY get it)]

See? Seven times. Thankfully I\'m not paid to remember or derive math
facts I sometime tend to forget but can look up.
 

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