Direct digital synthesis of square waves...

[Anthony William Sloman]

On Thursday, August 25, 2022 at 4:43:52 PM UTC+10, Ricky wrote:

On Thursday, August 25, 2022 at 12:50:47 AM UTC-4, bill....@ieee.org wrote:
On Thursday, August 25, 2022 at 1:24:55 PM UTC+10, Ricky wrote:
On Wednesday, August 24, 2022 at 10:30:13 PM UTC-4, bill....@ieee.org wrote:
On Thursday, August 25, 2022 at 6:30:11 AM UTC+10, Ricky wrote:
On Wednesday, August 24, 2022 at 10:14:05 AM UTC-4, Joe Gwinn wrote:
On Mon, 22 Aug 2022 21:53:03 -0700 (PDT), Clifford Heath <cliffor...@gmail.com> wrote:
On Tuesday, August 23, 2022 at 12:12:41 PM UTC+10, jla...@highlandsniptechnology.com wrote:
On Tue, 23 Aug 2022 11:21:00 +1000, Clifford Heath <no_...@please.net> wrote:
snip
That\'s all true in theory, but there are a lot of details to work out. How is this complexity, in any way superior to using a conventional DDS design in an FPGA with an external DAC and filter running over a 2:1 ratio, followed by an octave divider, all updatable from a single command, so completely synchronized, never producing a glitch pulse?

Of course, if you buy an Analog Devices DDS chip, the logic is all buried in the chip, so you don\'t have to buy or program the FPGA.

The reason that John Larkin isn\'t doing that does seem to be that the Analog Devices DDS chips are expensive, and an FPGA and a DAC to do the same job are cheaper (and harder to copy and look more like an original design). Once you\'ve got to that point, it may be worth thinking about using the same components in a slightly different way, which is what circuit designers do.

It also does not meet all his requirements, which is to produce pulses without glitches when retuned. By implementing the DDS in the FPGA, the DDS and the octave divider can be reprogrammed on the same clock cycle, making a glitchless transition.

Have you any idea how the Analog Devices chips work? Or what\'s being asked for? The Analog Devices part produce a continuous signal through a frequency transition so one transition is going to be in the wrong place in terms of either frequency regime, but that\'s inevitable, unless you make the transition on an output clock edge. which would take work.

There may be one issue to work out. The DDS will be running from the master clock. The octave divider will be running on the DDS output clock. So the octave threshold setting update will, by definition, not be perfectly synchronous with the DDS update. So this might need a bit of thought to make sure there are no glitches during a rate transition.

The trapezium ramp scheme wouldn\'t need an \"octave divider\" so it wouldn\'t have that problem.

The \"trapezium\" scheme has the problem that it isn\'t designed and may have other problems.

Of course it isn\'t designed. I\'m not going to put it into production, and John Larkin wouldn\'t pay me money to design it for him.

The detailed design phase is where you find and sort out a whole lot of - hopefully - minor problems. Back when I was getting paid to do that kind of work I was pretty good at it, but that\'s a long time ago. What I\'ve spelled out here strikes me as good beginning, but John Larkin may have some particularly rabid customer to satisfy, and he hasn\'t been all that forth-coming about the end application.

A lot of the point of having this kind of early stage design is to clarify what\'s going on and what needs to go on.

--
Bill Sloman, Sydney