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On Fri, 12 Aug 2022 07:10:56 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:
<snip>
Use a fast 8 bit down counter followed by a slow 40 bit down counter.
If the fast counter is run at 1 GHz (1 ns), the slow counter only
runs at 4 MHz. When the slow down counter reaches 0x0000000000, it can
start reloading the preset value. At that time the fast counter is at
0xFF and it takes 256 ns before reaching zero and doing the preset. At
that time the slow counter has already been reloaded and it can start
counting as soon as the preset fast counter reaches 0 the next time.
<snip>
Then do not use DDS directly for very low frequencies.
Reprogramming DDS = loading a new addend value into the DDS. After
that the phase accumulator increases more or less rapidly, so quite
hard to even detect in a short time.
If you have a DDS for periods shorter than 1 s, you could add a
divide-by-N for longer periods. Each time the divide-by-N reaches 0,
you could enable the DDS addend loading, thus the timing would be
quite clean, even for a time sweep. Of course, this will require
precalculating the DDS addend and the divide-by-N before the divider
expires, but a very primitive CPU could do it before a sweep or other
predictable sequence.
<jjlarkin@highlandtechnology.com> wrote:
On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:
On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
<snip>
If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?
Most of our customers expect to set an internal trigger frequency.
There are times when setting it to high resolution is valuable.
Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.
I can\'t do that in an FPGA. And resolution is mediocre around 10 MHz.
Use a fast 8 bit down counter followed by a slow 40 bit down counter.
If the fast counter is run at 1 GHz (1 ns), the slow counter only
runs at 4 MHz. When the slow down counter reaches 0x0000000000, it can
start reloading the preset value. At that time the fast counter is at
0xFF and it takes 256 ns before reaching zero and doing the preset. At
that time the slow counter has already been reloaded and it can start
counting as soon as the preset fast counter reaches 0 the next time.
<snip>
But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?
A straightforward DDS will have tons of period jitter at low
frequencies, which is ugly.
Then do not use DDS directly for very low frequencies.
And some customers whine if we stop
triggering while we reprogram a DDS (or a synth chip) and a divisor.
Reprogramming DDS = loading a new addend value into the DDS. After
that the phase accumulator increases more or less rapidly, so quite
hard to even detect in a short time.
Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.
If you have a DDS for periods shorter than 1 s, you could add a
divide-by-N for longer periods. Each time the divide-by-N reaches 0,
you could enable the DDS addend loading, thus the timing would be
quite clean, even for a time sweep. Of course, this will require
precalculating the DDS addend and the divide-by-N before the divider
expires, but a very primitive CPU could do it before a sweep or other
predictable sequence.