DDS questions...

[John Larkin]

On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I\'ve read, if he is looking for minimum jitter, there\'s nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave from the NCO and skipping the filter, that\'s fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
you want to turn that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
so 1uV tresh hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.



--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Glen Walpert]

On Thu, 11 Aug 2022 15:08:28 -0700, John Larkin wrote:

On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk
wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4,
upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin
wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd
whi...@gmail.com> wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin
wrote:

My question was, why make a sine wave if the final result
is a digital clock?

Do you want the digital clock edges to be synchronous with
an existing source, or asynchronous? Mathematically, the
creation of an asynchronous clock is not gonna happen in
clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse
generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for
arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the
dac is incremented infrequently and the filter doesn\'t do
much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the
wide noise power is close to the LSB size, do you need
additional dithering?. At low frequencies, there is also the 1/f
noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB
bits are buried in noise.

If you need better dither control, some DDS chips have phase
and/or amplitude modulators built in, so the PM/AM inputs can be
used to control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input
to the DAC. I believe he is talking about much higher sample rates
than what you can get in audio DACs. He wants to program clock
rates over a very wide range. Otherwise, none of this is a
problem. It\'s also not a problem if multiple filters are switched
depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock.
He is trying to view the problem from a very different perspective
to see if he can gain some insight rather than using the standard,
well defined approach. From what I\'ve read, if he is looking for
minimum jitter, there\'s nothing better than optimizing the length
of the phase counter, then using any of various means for
generating a sine waveform with high resolution, then rounding to
the data width of your DAC. If the clipping/rounding is done at
the phase word, it introduces close in spurs that can not be
effectively filtered out. The spurs introduced by rounding or
truncation of the sine data, tend to be harmonically related to
the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it
is now more of a cookbook matter, other than the details of
implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine
values, but it might have some utility in this case. I think the
best solution, though, and certainly more likely to produce a good
result, is to implement different low pass filters for the
different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS
output, so the issues is if you have, say just as an example, 1mV of
noise on where there comparator switches. The slow slewrate of a
sinewave going through that 1mV can cause more just jitter on the
resulting squarewave than just hammering through that 1mV window
with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave
from the NCO and skipping the filter, that\'s fine. He will get a
jitter of one clock period. Adding a filter will do little to clean up
jitter in the square wave and will slow the edge rate to create the
noise sensitivity problem again. If the requirements allow this much
jitter, then there was no need for all the fuss in the first place. If
he needs low ps level jitter, then he has to mitigate the close in
spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase
truncation, but maybe they only appear when running that through the
sine wave generator. If you skip the sine generation, perhaps that
doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter
combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn
that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV
just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh
hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes
628V/s, the DAC can\'t make 200V so we\'ll chop the peaks off since we are
only interested in the zero crossing so 1uV tresh hold variation is now
only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will
change about every millisecond. And theoretically one step parks at zero
volts. So jitter is bad. Gain doesn\'t improve things.

So if I have this right the DDS has lowest jitter at high frequencies and
a digital clock will have lowest jitter at low frequencies, where you can
calculate the optimal crossover frequency between the two for lowest
jitter across a wide range, and you want to use the phase accumulator? of
the DDS as your digital clock at lower frequencies, allowing for fast
synchronized transition between the two? Been a long time since I used a
DDS, not at all clear on the details, but is this basically what you are
trying to do?

Glen

 

[whit3rd]

On Thursday, August 11, 2022 at 3:08:46 PM UTC-7, John Larkin wrote:

On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.

Oh, if your goal is to clock logic, gain certainly DOES improve things; you want
the fast rise. And, \'one step\' is exactly what the filter doesn\'t pass; your DAC is clocked
at sub-microsecond intervals complete with some dither, and the microsecond-steps are
filtered away. You\'re using the oversampling wrong if you have a millisecond duration zero
volt output.

 

[John Larkin]

On Thu, 11 Aug 2022 22:53:41 GMT, Glen Walpert <nospam@null.void>
wrote:

On Thu, 11 Aug 2022 15:08:28 -0700, John Larkin wrote:

On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk
wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4,
upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin
wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd
whi...@gmail.com> wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin
wrote:

My question was, why make a sine wave if the final result
is a digital clock?

Do you want the digital clock edges to be synchronous with
an existing source, or asynchronous? Mathematically, the
creation of an asynchronous clock is not gonna happen in
clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse
generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for
arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the
dac is incremented infrequently and the filter doesn\'t do
much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the
wide noise power is close to the LSB size, do you need
additional dithering?. At low frequencies, there is also the 1/f
noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB
bits are buried in noise.

If you need better dither control, some DDS chips have phase
and/or amplitude modulators built in, so the PM/AM inputs can be
used to control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input
to the DAC. I believe he is talking about much higher sample rates
than what you can get in audio DACs. He wants to program clock
rates over a very wide range. Otherwise, none of this is a
problem. It\'s also not a problem if multiple filters are switched
depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock.
He is trying to view the problem from a very different perspective
to see if he can gain some insight rather than using the standard,
well defined approach. From what I\'ve read, if he is looking for
minimum jitter, there\'s nothing better than optimizing the length
of the phase counter, then using any of various means for
generating a sine waveform with high resolution, then rounding to
the data width of your DAC. If the clipping/rounding is done at
the phase word, it introduces close in spurs that can not be
effectively filtered out. The spurs introduced by rounding or
truncation of the sine data, tend to be harmonically related to
the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it
is now more of a cookbook matter, other than the details of
implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine
values, but it might have some utility in this case. I think the
best solution, though, and certainly more likely to produce a good
result, is to implement different low pass filters for the
different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS
output, so the issues is if you have, say just as an example, 1mV of
noise on where there comparator switches. The slow slewrate of a
sinewave going through that 1mV can cause more just jitter on the
resulting squarewave than just hammering through that 1mV window
with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave
from the NCO and skipping the filter, that\'s fine. He will get a
jitter of one clock period. Adding a filter will do little to clean up
jitter in the square wave and will slow the edge rate to create the
noise sensitivity problem again. If the requirements allow this much
jitter, then there was no need for all the fuss in the first place. If
he needs low ps level jitter, then he has to mitigate the close in
spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase
truncation, but maybe they only appear when running that through the
sine wave generator. If you skip the sine generation, perhaps that
doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter
combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn
that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV
just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh
hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes
628V/s, the DAC can\'t make 200V so we\'ll chop the peaks off since we are
only interested in the zero crossing so 1uV tresh hold variation is now
only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will
change about every millisecond. And theoretically one step parks at zero
volts. So jitter is bad. Gain doesn\'t improve things.

So if I have this right the DDS has lowest jitter at high frequencies and
a digital clock will have lowest jitter at low frequencies, where you can
calculate the optimal crossover frequency between the two for lowest
jitter across a wide range, and you want to use the phase accumulator? of
the DDS as your digital clock at lower frequencies, allowing for fast
synchronized transition between the two? Been a long time since I used a
DDS, not at all clear on the details, but is this basically what you are
trying to do?

Glen

That\'s about right. At high frequencies, synthesize a waveform
(usually a sine) and lowpass filter it into a comparator. At low
frequencies, just use the MSB of the phase accumulator as the clock. I
think a glitchless transition can be made between those two modes.

And next step, do something trickier between the phase accumulator and
the DAC, trapezoid maybe at a high DAC clock rate where the filter
still helps.





--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Thu, 11 Aug 2022 16:02:42 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

On Thursday, August 11, 2022 at 3:08:46 PM UTC-7, John Larkin wrote:
On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.

Oh, if your goal is to clock logic, gain certainly DOES improve things; you want
the fast rise. And, \'one step\' is exactly what the filter doesn\'t pass; your DAC is clocked
at sub-microsecond intervals complete with some dither, and the microsecond-steps are
filtered away. You\'re using the oversampling wrong if you have a millisecond duration zero
volt output.

A comparator makes a fast rise. The problem is at the DAC output.

Dithering sounds like a jitter generator. I\'d rather put some clever
waveform into the DAC.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Thu, 11 Aug 2022 19:00:28 -0000 (UTC), Mike Monett <spamme@not.com>
wrote:

whit3rd <whit3rd@gmail.com> wrote:

On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote:
On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:

A precision clock, high frequency low jitter

Feeding into the FPGA with say 64bit counter, adding delay line for sub
clock cycle accuracy

Compare and lookup on that counter, coupled to the delay line also

Like standard PWM done in microcontroller timer

Programming is cycle to cycle, changing just the compare capture word

That architecture works in theory, and the math isn\'t bad to do
on-the-fly in an FPGA. One practical difficulty is building an
instantly-programmable glitch-free delay line.

Or, just fine-tune a cavity oscillator by moving a wall, trombone-style.
You get continuous frequency control, but it does need a moving part.
Next step up from that, is a YIG system tuned with magnetic field.

Yig\'s are great, but you have to stabilize the current.

It sounds messy to get extreme mag field stability. And a yig won\'t go
down to 1 Hz.
--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Anthony William Sloman]

On Friday, August 12, 2022 at 9:40:02 AM UTC+10, John Larkin wrote:

On Thu, 11 Aug 2022 19:00:28 -0000 (UTC), Mike Monett <spa...@not.com
wrote:
whit3rd <whi...@gmail.com> wrote:

On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote:
On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund
klau...@hotmail.com> wrote:

A precision clock, high frequency low jitter

Feeding into the FPGA with say 64bit counter, adding delay line for sub
clock cycle accuracy

Compare and lookup on that counter, coupled to the delay line also

Like standard PWM done in microcontroller timer

Programming is cycle to cycle, changing just the compare capture word

That architecture works in theory, and the math isn\'t bad to do
on-the-fly in an FPGA. One practical difficulty is building an
instantly-programmable glitch-free delay line.

Or, just fine-tune a cavity oscillator by moving a wall, trombone-style.
You get continuous frequency control, but it does need a moving part.
Next step up from that, is a YIG system tuned with magnetic field.

Yig\'s are great, but you have to stabilize the current.
It sounds messy to get extreme mag field stability. And a yig won\'t go
down to 1 Hz.

It doesn\'t have to. If you can tune the YIG oscillator over a continuous 2:1 range , a binary divider can get you almost literally any lower frequency - a thirty stage divider get you close to 1Hz. And the YIG oscillation frequency is a pretty accurate guide to the magnetic field - monitor that for feedback control of the magnetic field.

--
Bill Sloman, Sydney

 

[Martin Brown]

On 11/08/2022 23:08, John Larkin wrote:

On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I\'ve read, if he is looking for minimum jitter, there\'s nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave from the NCO and skipping the filter, that\'s fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
you want to turn that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
so 1uV tresh hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.

Although that is true if you set your zero crossing high/low by half a
least significant bit (or half the smallest step in the sine wave table)
then you can trade lower jitter for a small asymmetry in the waveform.

Then divide by two in the digital domain and you are done.

The other option is to integrate the output of the DAC so that you get a
join the dots piecewise linear waveform much more amenable to comparator
thresholding and interpolation in the time domain.

But then you have new problems - drift/offsets in the integrator,
variable gain and delay offset as the frequency changes.

There is no free lunch!

--
Regards,
Martin Brown

 

[server]

On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
<gnuarm.deletethisbit@gmail.com> wrote:

On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.

larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?

Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?

Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.

 

[John Larkin]

On Fri, 12 Aug 2022 08:20:50 +0100, Martin Brown
<\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 11/08/2022 23:08, John Larkin wrote:
On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I\'ve read, if he is looking for minimum jitter, there\'s nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave from the NCO and skipping the filter, that\'s fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
you want to turn that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
so 1uV tresh hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.

Although that is true if you set your zero crossing high/low by half a
least significant bit (or half the smallest step in the sine wave table)
then you can trade lower jitter for a small asymmetry in the waveform.

The DAC still increments once a millisecond.

Then divide by two in the digital domain and you are done.

The other option is to integrate the output of the DAC so that you get a
join the dots piecewise linear waveform much more amenable to comparator
thresholding and interpolation in the time domain.

But then you have new problems - drift/offsets in the integrator,
variable gain and delay offset as the frequency changes.

There is no free lunch!

The option is to do digital tricks in the FPGA. Almost free lunch.

I\'m thinking that it\'s (barely) possible to simulate the DDS in LT
Spice. The tricky part would then be measuring period jitter.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[John Larkin]

On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:

On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
gnuarm.deletethisbit@gmail.com> wrote:

On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.

larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?

Most of our customers expect to set an internal trigger frequency.
There are times when setting it to high resolution is valuable.

Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

I can\'t do that in an FPGA. And resolution is mediocre around 10 MHz.

It might be interesting to program a 1 GHz SERDES channel (which we
can do) DDS-sorta waveform that we can filter into a comparator.
That\'s hard to think about, which I can delegate.

But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?

A straightforward DDS will have tons of period jitter at low
frequencies, which is ugly. And some customers whine if we stop
triggering while we reprogram a DDS (or a synth chip) and a divisor.

Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.

I\'ll ping the boys about the SERDES idea. That could be cool.

--

John Larkin Highland Technology, Inc trk

The cork popped merrily, and Lord Peter rose to his feet.
\"Bunter\", he said, \"I give you a toast. The triumph of Instinct over Reason\"

 

[Anthony William Sloman]

On Saturday, August 13, 2022 at 12:11:15 AM UTC+10, John Larkin wrote:

On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote:
On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

<snip>

Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

I can\'t do that in an FPGA. And resolution is mediocre around 10 MHz.

Peter Alfke probably could have. Sadly, he is dead.

https://www.eetimes.com/peter-alfke-remembered-1931-2011/

There are quite a lot of different sorts of FPGA\'s around, some of them quite quick

It might be interesting to program a 1 GHz SERDES channel (which we
can do) DDS-sorta waveform that we can filter into a comparator.
That\'s hard to think about, which I can delegate.

But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale?

A straightforward DDS will have tons of period jitter at low frequencies, which is ugly.

So don\'t use a \"straightforward DDS\".

> And some customers whine if we stop triggering while we reprogram a DDS (or a synth chip) and a divisor.

So ping-pong between two.

Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.

I\'ll ping the boys about the SERDES idea. That could be cool.

The last serial data link that I played with was the Taxichip back in 1988. It used an 8-bit to 10-bit recoding scheme to avoid sending troublesome bit patterns.

Working out what you were actually sending might be a bit tedious.

--
Bill Sloman, Sydney

 

[Mike Monett]

upsidedown@downunder.com wrote:

[...]

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?

Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?

Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.

The Stanford Research Systems group has introduced a new method of
frequency generation described below:

SG380 Series RF Signal Generators

Introducing the new SG380 Series RF Signal Generators—finally, high
performance, affordable RF sources.

The SG380 Series RF Signal Generators use a unique, innovative architecture
(Rational Approximation Frequency Synthesis) to deliver ultra-high
frequency resolution (1 µHz), excellent phase noise, and versatile
modulation capabilities (AM, FM, ØM, pulse modulation and sweeps) at a
fraction of the cost of competing designs.

The standard models produce sine waves from DC to 2.025 GHz (SG382), 4.05
GHz (SG384) and 6.075 GHz (SG386).

A New Frequency Synthesis Technique

The SG380 Series Signal Generators are based on a new frequency synthesis
technique called Rational Approximation Frequency Synthesis (RAFS). RAFS
uses small integer divisors in a conventional phase-locked loop (PLL) to
synthesize a frequency that would be close to the desired frequency
(typically within ±100 ppm) using the nominal PLL reference frequency. The
PLL reference frequency, which is sourced by a voltage control crystal
oscillator that is phase locked to a dithered direct digital synthesizer,
is adjusted so that the PLL generates the exact frequency. Doing so
provides a high phase comparison frequency (typically 25 MHz) yielding low
phase noise while moving the PLL reference spurs far from the carrier where
they can be easily removed. The end result is an agile RF source with low
phase noise, essentially infinite frequency resolution, without the spurs
of fractional-N synthesis or the cost of a YIG oscillator.

https://www.thinksrs.com/products/sg380.html

The manual is at

https://www.thinksrs.com/downloads/pdfs/manuals/SG380m.pdf

The description of Rational Approximation Synthesis starts on page 151. A
block diagram is on page 156.





--
MRM

 

[Ricky]

On Friday, August 12, 2022 at 10:11:15 AM UTC-4, John Larkin wrote:

On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote:

On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:

On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.

larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?
Most of our customers expect to set an internal trigger frequency.
There are times when setting it to high resolution is valuable.

Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.
I can\'t do that in an FPGA. And resolution is mediocre around 10 MHz.

It might be interesting to program a 1 GHz SERDES channel (which we
can do) DDS-sorta waveform that we can filter into a comparator.
That\'s hard to think about, which I can delegate.

But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?
A straightforward DDS will have tons of period jitter at low
frequencies, which is ugly. And some customers whine if we stop
triggering while we reprogram a DDS (or a synth chip) and a divisor.

Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.
I\'ll ping the boys about the SERDES idea. That could be cool.

Cool, but it puts you right back at dealing with all the jitter issues of outputting the timing signal directly from the FPGA.

--

Rick C.

+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209

 

[Phil Hobbs]

John Larkin wrote:

On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I\'ve read, if he is looking for minimum jitter, there\'s nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave from the NCO and skipping the filter, that\'s fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
you want to turn that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
so 1uV tresh hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.

Numerical gain ahead of the DAC does help, though, as somebody pointed
out upthread.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Ricky]

On Friday, August 12, 2022 at 1:03:24 PM UTC-4, Phil Hobbs wrote:

John Larkin wrote:
On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.
larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I\'ve read, if he is looking for minimum jitter, there\'s nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to filter.

The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

I\'ve never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for the different ranges of clock output rates.

Don\'t you agree?
afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
And your point is?

If larkin is talking about producing a square or \"trapezoidal\" wave from the NCO and skipping the filter, that\'s fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO truncation.

Maybe I shouldn\'t say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn\'t produce the unfilterable spurs. I\'m not betting on it.


you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
you want to turn that into a square wave so you stick it into a comparator.

The comparator isn\'t perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
so 1uV tresh hold variation turns into a ~16us timing variation

ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can\'t make 200V so we\'ll chop
the peaks off since we are only interested in the zero crossing
so 1uV tresh hold variation is now only a ~160ns timing variation

Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
will change about every millisecond. And theoretically one step parks
at zero volts. So jitter is bad. Gain doesn\'t improve things.
Numerical gain ahead of the DAC does help, though, as somebody pointed
out upthread.

It\'s hard to do good work with a 10 bit DAC. A 16 bit DAC would improve the time step to about 16 us.

https://www.ti.com/data-converters/dac-circuit/high-speed/products.html#p84=16;16&sort=p1130;asc

This time step does not define the jitter. That\'s why the sine wave is filtered, to smooth the threshold point to a proper sine function. Different filters are needed for different frequency ranges. That would seem to be pretty obvious.

--

Rick C.

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

 

[Clifford Heath]

On 12/8/22 17:20, Martin Brown wrote:

Although that is true if you set your zero crossing high/low by half a
least significant bit (or half the smallest step in the sine wave table)
then you can trade lower jitter for a small asymmetry in the waveform.

Wouldn\'t it be just as good (and symmetrical) to introduce a one-bit
hysteresis? And not need to divide?

The other option is to integrate the output of the DAC so that you get a
join the dots piecewise linear waveform much more amenable to comparator
thresholding and interpolation in the time domain.

So, a first-order filter? What do you reckon a normal DDS filter is doing?

Clifford Heath

 

[Clifford Heath]

On 12/8/22 23:54, upsidedown@downunder.com wrote:

On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
gnuarm.deletethisbit@gmail.com> wrote:

On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.

larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?

Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?

Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
might be justified to get 1 ps timing steps. But for longer times,
say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
after the DDS ? Combining the DDS and divide-by-N programming, quite
strange periods can be obtained.

You just described a one-bit DDS. It doesn\'t need a lookup table, of course.

CH

 

[Clifford Heath]

On 13/8/22 00:10, John Larkin wrote:

On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:

On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
gnuarm.deletethisbit@gmail.com> wrote:

On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.

larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?

Most of our customers expect to set an internal trigger frequency.
There are times when setting it to high resolution is valuable.


Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

I can\'t do that in an FPGA. And resolution is mediocre around 10 MHz.

It might be interesting to program a 1 GHz SERDES channel (which we
can do) DDS-sorta waveform that we can filter into a comparator.
That\'s hard to think about, which I can delegate.


But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?

A straightforward DDS will have tons of period jitter at low
frequencies, which is ugly. And some customers whine if we stop
triggering while we reprogram a DDS (or a synth chip) and a divisor.

So use the top bit of the DDS accumulator, but take the next few bits to
drive a digital delay generator to add 0..1ns of extra delay (or
0.5..1.5ns, etc). You\'re good with design of picosecond digital delay
generators, I understand?

Clifford Heath.

 

[Lasse Langwadt Christensen]

lørdag den 13. august 2022 kl. 02.17.58 UTC+2 skrev Clifford Heath:

On 13/8/22 00:10, John Larkin wrote:
On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote:

On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:

On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder..com wrote:
On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

My question was, why make a sine wave if the final result is a digital
clock?

Do you want the digital clock edges to be synchronous with an existing source, or
asynchronous? Mathematically, the creation of an asynchronous clock is
not gonna happen in clocked logic circuitry, it has to have an analog component.
Of course. The analog components are dac, filter, comparator.

I want a programmable internal trigger rate for a pulse generator.

A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
up to Nyquist. But it gets messy at low frequencies where the dac is
incremented infrequently and the filter doesn\'t do much.

Sounds like an application for dithering.

Do you even need explicit dithering ?

The DAC output has some wide band (thermal) white noise. If the wide
noise power is close to the LSB size, do you need additional
dithering?. At low frequencies, there is also the 1/f noise.

For audio frequencies \"24 bit\" 192 kHz DACs are available, which
accepts 24 bit sample values, but in practice the last few LSB bits
are buried in noise.

If you need better dither control, some DDS chips have phase and/or
amplitude modulators built in, so the PM/AM inputs can be used to
control the high frequency dither more precisely.

larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is a problem. It\'s also not a problem if multiple filters are switched depending on the frequency of the output clock.

He\'s already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

If the purpose is to create a variable _timing_ generator (not just
frequency generator), why mess with the DDS principle at all ?

Most of our customers expect to set an internal trigger frequency.
There are times when setting it to high resolution is valuable.


Using a divide-by-N counter clocked at say, 1 GHz, you can timing
intervals in 1 ns steps. With a 48 bit synchronous down counter, you
can get timing intervals of several days with 1 ns timing steps. Some
trickery is needed to avoid running all 48 stages at full ECL speed.

I can\'t do that in an FPGA. And resolution is mediocre around 10 MHz.

It might be interesting to program a 1 GHz SERDES channel (which we
can do) DDS-sorta waveform that we can filter into a comparator.
That\'s hard to think about, which I can delegate.


But the real question is, do you really need nanosecond step size in
minutes, hours or day time scale ?

A straightforward DDS will have tons of period jitter at low
frequencies, which is ugly. And some customers whine if we stop
triggering while we reprogram a DDS (or a synth chip) and a divisor.
So use the top bit of the DDS accumulator, but take the next few bits to
drive a digital delay generator to add 0..1ns of extra delay (or
0.5..1.5ns, etc).

make a square wave with the DAC, into integrator (filter)
vary the amplitude