A
Andrew Beckett
Guest
Erik,
In which case, why not get the simulator to do it? Having another process in
there to process the netlist:
a) wouldn't help the case where subckt instances have m factors
b) would have to include a complete spectre parser (which spectre already
has...)
c) would not help with the mapping of original components in the schematic to
the netlist (in fact would make it worse, unless perhaps it update the map
information in the netlist dir).
Regards,
Andrew.
On 1 Aug 2003 20:21:15 -0700, erikwanta@starband.net (Erik Wanta) wrote:
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
In which case, why not get the simulator to do it? Having another process in
there to process the netlist:
a) wouldn't help the case where subckt instances have m factors
b) would have to include a complete spectre parser (which spectre already
has...)
c) would not help with the mapping of original components in the schematic to
the netlist (in fact would make it worse, unless perhaps it update the map
information in the netlist dir).
Regards,
Andrew.
On 1 Aug 2003 20:21:15 -0700, erikwanta@starband.net (Erik Wanta) wrote:
--Andrew:
How about postprocessing the netlist to convert all the devices with a
specified mfactor (m, np, M, _M, ...) to iterated instance notation
(M0_0, M0_1...)? I suppose you could have the case of iterated
instances and m>2.
---
Erik
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<837hiv00p9esmlk837o5g5dctnjgvuoa8o@4ax.com>...
Hi Erik,
It's possible, but wouldn't then handle custom netlist procedures (each
custom netlist procedure would have to implement this); nor would it handle
m factor on subckt instances; nor would it help people working from netlists.
So I think the simulator is probably the right place to do it.
Regards,
Andrew.
On 30 Jul 2003 19:52:46 -0700, erikwanta@starband.net (Erik Wanta) wrote:
Andrew:
Instead of splitting the devices up inside spectre, how about a
netlist option that prints out the devices that use the mfactor in the
iterated instances format?
---
Erik
erikwanta@starband.net (Erik Wanta) wrote in message news:<84018314.0307300939.206fd778@posting.google.com>...
Andrew:
I like the idea of the option to split the devices up that are using
mfactor inside spectre for dcmatch and monte carlo.
We try to discourage the use of iterated instances and use the mfactor
and layoutXL generate multiple instances. The only problem we have
are layout designers who refuse to use layoutXL.
---
Erik
Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<ccgfiv0n3sn18nf3c773mo5asfcdht4q4n@4ax.com>...
Frederic,
Fairly recently I did propose the opposite:
PCR: 419311
Title: montecarlo and dcmatch need to allow mismatch with m factor
Where I outlined:
Commonly instances have the "m" parameter on them to indicate multiple
devices. This is generally used to indicate that a device will be laid
out using m devices in parallel.
However, the problem with doing this is that for mismatch type analyses
(i.e. montecarlo and presumably the new IC50 dcmatch), all the
separate parallel instances are going to end up being 100% correlated,
because the m-factor is being taken account within the device equations.
We need to come up with some way of handling this. One possibility would
be to split the devices up (inside spectre) into really separate parallel
devices. Of course, the downside is that this would slow the simulation
down and increase the memory usage significantly.
The user can workaround this by using instance names such as M1<0:8
in composer (i.e. an iterated instance), but this means that you pay
the penalty for there being parallel devices in normal simulations.
Potentially the other way around could be done (at least in simple cases).
The problem is where do you stop? I think you'd want to do it both before
the hierarchy was flattened (so that subckts in parallel get m-factor'd up),
and then after flattening (to catch any others which happened to end
up in parallel after flattening - although in this case you'd probably be
restricted to single primitives in parallel). Doing this reduction could take
a reasonable amount of time (it can do in a verification tool), so it
would have to be an option.
Then you'd have the issue of relating the simulated results back to the
original netlist. For example, what if you'd asked to save the current
in _one_ of the devices that got paralleled up? Or what if you wanted to
look at the operating point data for one of these devices. It could get quite
confusing (or hard to handle).
An interesting idea though. I'm not sure how often people use the iterated
instance approach though - in other words, would it really be worth the effort
of implementing this (which I suspect could end up being a can of worms...)
when the "right" thing to do is to use the m-factor (with the proviso of PCR
419311 above).
Any thoughts?
Regards,
Andrew.
On Tue, 29 Jul 2003 12:53:54 +0200, eda support guy
cad_support_at_catena_dot_the_netherlands> wrote:
Andrew,
You mentioned here something that always puzzled me. Putting 2
identical devices, in parallel in a netlist does increase the simulation
cpu-time compared to putting one device with m=2. This is true with
spectre, and also with any spice-like simulator that I know of.
Now, would it not be easy for spectre programmers to do a little
"network preprocessing" in spectre and replace identical devices in
parallel by devices with an M>1 ? This, of course applies not only to
device models or devices modelled as subcircuits, but to any identical
subcircuit, or any identical "subparts" in a circuit.
Those two identical parts should have their nodes virtually shorted,
thereby easily reducing the admittance (or tableau, etc ...) matrix size.
I admit this can bring it share of problems, for instance in
implementing DCmatch or other sensitivity analysis, but the simulation
speedup would outweight the trouble, wouldn t it ?
Now, this would be too easy, and it is not done in spectre or *spice, so
I m probably overseeing stg. Anyone please tell me what ?
--
Frederic
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd