cell libraries and place and route

[Andrew Beckett]

FYI,

File->Export->Stream has an option "Output Rectangle as BOX" (off by default)
and File->Import->Stream has an option "Ignore BOX record" (off by default) to
handle this variability in the comprehension of box records by various other
tools.

Regards,

Andrew.

 

[Andrew Beckett]

On 26 May 2005 01:20:58 -0700, wjcndyd@yahoo.com wrote:

Thank you, Andrew!

After played around it for a while, I think I'm getting close there.
Here is another question.

Regardless how I change the values in the CDF form of the blocks, the
values actually never change. I have to go into the source file to edit
them. Could this be a bug?

Also, where's the default location for the log file? Is input.dat under
netlist/ the correct result file?

Many thanks!!!

Why are you changing values on the CDF form? (I assume you mean the
Tools->CDF->Edit CDF form) - this is primarily set up to reflect the
parameters in the Verilog-A model, so that there's a placeholder for create
instance and edit properties. The actual default values are held in the
Verilog-A code.

What you would normally do is set the properties on the _instance_ by doing an
edit properties on the instance of adc_dnl_8bit and set them to the values you
want. That should work (I've not tried it, as I'm not in the office at the
moment, but I can't see why it wouldn't work).

Regards,

Andrew.

 

[Andrew Beckett]

On 25 May 2005 23:30:03 -0700, keylinme@yahoo.com wrote:

Andrew Beckett wrote:
Ah, I see the problem. The pin on the symbol is an input pin. Well, it
shouldn't be, and that's a bug. I'll file a PCR for that.

I filed PCR 802181 to get this pin direction corrected.

What is adc_dnl_8bit?
Is it IP that Cadence do provide?
Or is it IEEE IP?
Or what?

If you'd read the previous postings, you'd see that it is a sample verilog-a
model provided in the ahdlLib library, in:

<ICinstDir>/tools/dfII/samples/artist/ahdlLib

and is a block for characterising the DNL of an 8 bit ADC. Read the comments
in the Verilog-A code for more detail.

Regards,

Andrew.

 

[Andrew Beckett]

On 31 May 2005 22:01:45 -0700, wjcndyd@yahoo.com wrote:

Thank you, Andrew! Is input.dat the output file which contains the
DNL's for all the codes?

Yes, looking at the code, if log_to_file is set to non-zero, it writes to a
file called "%C:r.dat" - this means the input file name, stripped of its
suffix, with .dat appended. If the input file is input.scs (which it is from
within ADE), the output file will be called input.dat.

The code mentions a parameter "filename" - but that is not implemented in the
Verilog-A version of the code - it was there in the spectreHDL code. string
parameters were only recently added to Verilog-A, but this model predates
that.

Regards,

Andrew.

 

[Andrew Beckett]

On 31 May 2005 23:06:28 -0700, "stroller" <smcbutler@hotmail.com> wrote:

hi all,

i need to print to a file the following

fprintf( mFilePort "%--------------------\n")

where the % is a comment in the target syntax

i get an 'incorrect fprintf formatting' error when i try this however.
i've tried \% and that doesn't seem to work either... can anyone tell
me what i need to do to get the "%" printed here?

thx

%% is the sequence to print a %.

Andrew.

 

[S. Badel]

Got queries on your suggestion...What should be the view contents of
the abstract view..only pins?....
Mostly, they contain pins, blockages, plus some properties on the cell and on the

pins. The properties are not absolutely needed by PRFlatten, but it will complain
if it cannot find them.

if we define only pins does PRFlatten stop there...?
It generates a flat netlist using the switch/stop view lists. For this, the usual

requirement for succeeding is that cells must have the same pins. Otherwise netlisting
won't succeed. so you have to define pins, and the view must be in the stop view list.

...will I be able to connect the top level view with
these abstract view as we do with symbols...
Aaaargh... are you trying to generate a flat schematic? PRFlatten is for generating layouts,

it won't generate a schematic.
If you want to generate a schematic, you might want to look at
http://groups.google.ch/group/comp.cad.cadence/browse_frm/thread/e1eb64ad494cecc3/f622f01c0457a860?q=flatten&rnum=2&hl=fr#f622f01c0457a860

stéphane

 

[DReynolds]

Aaron, what kind of primitives do you need? If mos only, it is pretty
easy... I have done it in the past ... as for parameters, what I did
was ignore the problem and solve it in skill since verilog didn't
like w, l etc as you mention. I made a list od lists that had the
instance name and the parameters to be added to it. After the
schematic was made, I ran a skill program that called this list, went
to the instance, and added the parameters back using dbReplaceProp().


David Reynolds

 

[Andrew Beckett]

If you do a noise analysis, you can tell it where the input source is, and it
will then compute the input referred noise in whatever gain configuration
you've got. It's pretty silly measuring input referred noise in a different
conguration than you're actually going to use the amplifier.

You don't need to set an AC magnitude to do noise analysis - since it computes
the transfer function from the specified source to the output, and then
divides the output noise by that transfer function.

Regards,

Andrew.

On 2 Jun 2005 22:11:10 -0700, wjcndyd@yahoo.com wrote:

Sorry, I meant AC magnitude "1".

wjcndyd@yahoo.com wrote:
If I want to simulate input referred noise of an op amp using "Noise"
analysis in Analog Artist, is the configuration (unity-gain) below a
good way?
Vsin here is the independent source from analogLib. Since vsin itself
is noiseless, then all the noise should come from the amplifier itself,
in this case, onoise = input referred noise, right? Or Vsin can be
replaced with vdc with AC amplitude set to 0... ? Thank you for your
comments/corrections!

_________________
| |
| |
|________|\ |
| \ |
| \____|
________ |Amp/
| | /
| | /
(Vsin) |/
|
-------
---

 

[Andrew Beckett]

On 2 Jun 2005 04:58:14 -0700, "Achintya" <vs_praveen@yahoo.com> wrote:

Hi,

Thanks very much particularly for the last point as I was trying to do
exactly that. I shall follow the link and try to get the best out of
it.

-vs_p.

I guess you could always flatten it with PRflatten and then do
File->Import->Netlist View to build a schematic from the result?

If you really wanted to, that is. As Stephane pointed out, this may not be the
most efficient approach.

Andrew.

 

[Andrew Beckett]

On 2 Jun 2005 06:48:03 -0700, "Tim" <troy1@irf.com> wrote:

Hi,

I imported a spice netlist from Orcad using "Import>>>XL netlist". I
used this to get my XL connectivity and it works fine on a placed
layout. I tried using "Import>>>Netlist View"
(connectivity-to-schematic) and get the error (Could not open cell
"DESIGN1" view "netlist" in library "c025_test").

Can connectivity-to-schematic import a spice netlist into a physical
schematic? The manual doesn't list what type(s) of netlist it can use,
or how it will find which schematic symbols to use.

Thanks in Advance,
Tim

Below is my spice test netlist;

*DESIGN1

.SUBCKT DESIGN1 N00344

R1 N00344 N00343 rdp 10K
R2 N00343 N00345 rdp 20K
Q1 N00344 N00343 N00345 LGND ne1 1X
.ENDS

File->Import->CDL can do this - it now supports some (limited) device mapping.

There are plans to improve the parsing to be a little less CDL-specific. (CDL
is very SPICE-like).

Andrew.

 

[Andrew Beckett]

On 3 Jun 2005 12:59:29 -0700, wjcndyd@yahoo.com wrote:

So putting a source there (vsin or whatever) is just to let the
simulator know where the input is? Did I understand this correctly?
Thank you very much!

Yes, you need to have a current or voltage source (even if it is dc,
with zero-value), and then you need to indicate this source when you specify
the noise analysis. You're telling the noise analysis which source is the
input of the circuit.

Of course, if you don't care about input referred noise, you can tell it that
there isn't an input source.

Alternatively if you're computing noise figure or noise factor, you can tell
it that you have a port as the input (ports are like sources but have
impedance, and the impedance generates noise, which is important if you're
measuring noise figure - mostly for RF designers...)

Regards,

Andrew.

 

[Andrew Beckett]

On 1 Jun 2005 10:49:08 -0700, "mekhail" <mekhail@gmail.com> wrote:

Hi Andrew,

I hope this helps, I still have no clue as to why i am getting this
error. I will be checking this posting much more frequently.

Thanks for any help,

mekhail

Looks to me as if you have a block instantiated in the cell where the error
occurs, which has a property (hnlVerilogFormat or something like that) with
a value which is hnlVerilogPrintBehaveModel("....") where the argument is
supposed to be a list of terminal names (I think) rather than a string.

Unfortunately I don't have time to look at this in any more depth right now -
I'm out of the office for a few days.

Regards,

Andrew.

 

[S. Badel]

thanks, i have had this problem too, but i lived with it.


stéphane

Nadine@MailSys.de wrote:

Coincidence helped me here:
The problem is the flagUnconnectedVias option in the DRC rules for
UMC's 180nm
technology. Disabling this options fixes the crashes.

Nadine

 

[Andrew Beckett]

Hi,

My original requirement is a CDL Out of the flattened schematic
netlist. Will I be able to do that with above approach?

-vs_p.

Probably, if you map to the right library.

Also, there is support for flat netlisting in CDL. This is covered in the
documentation, if I remember rightly - that's probably a simpler solution.
That way you don't need to flatten the design.

Put :

cdlNetlistType='fnl

in your .simrc file.

Regards,

Andrew.

 

[Diva Physical Verificatio]

On 8 Jun 2005 14:06:14 -0700, Nadine@MailSys.de wrote:

Diva Physical Verification wrote:
On 8 Jun 2005 03:25:59 -0700, Nadine@MailSys.de wrote:

Coincidence helped me here:
The problem is the flagUnconnectedVias option in the DRC rules for
UMC's 180nm
technology. Disabling this options fixes the crashes.

Nadine

Is there any chance you could submit a SR for this problem? I have
forwarded your postings and they may be able to reproduce it with
something they have in-house, but a small testcase would help them be
sure they are fixing the problem you are seeing.

I don't have much time at the moment because we need to get our chip
ready for next week's run. Just let me know by mid next week whether
you were able to reproduce this or not. I can prepare a small example
by then. But actually really every trivial cell triggers this here.
Just place an N_18_MM instance, no pins etc., and run DRC twice with
- flagOffGrid 0.01
- flagNon45
- flagAcuteAngle
- flagUnconnectedVias
and it hangs. The last of these options is the critical one. The others
are the typical set we commonly use. I guess it would also fail without
them.

Nadine

I'll ask the Assura team if they can reproduce it, but you should assume
they can't and file the SR when you have the time. I'd try to do it
myself, but what I don't know about Assura is as great as what I DO know
about Diva. My being the Diva guy, and all that.

 

[Richard Griffith]

kvaddina wrote:

Dear all,

Problem: Could not execute an Ocean File using TCL scripting language.

I was able to execute my Ocean file from the unix command prompt. I
used the following command.
ocean</home/glitches/SIMULATION/OCEAN/startc0.ocn> /dev/null

I have made an entry in my TCL script in the following way which failed
to execute.
exec ocean</home/glitches/SIMULATION/OCEAN/startc0.ocn> /dev/null
(where "exec" is a TCL built in command.)

Can any one give me an idea where I am going wrong.

Thanks and Regards,
Kvaddina.

The redirect operators < and > are normally supported by the shell. Not
by the standard UNIX exec.

< and > are supported by TCL exec but must appear in a specific form
exec ocean </home/glitches/SIMULATION/OCEAN/startc0.ocb >/dev/null

Should be the correction needed. < and > must start an argument or can
be surrounded by space they cannot be combined into an argument as
"ocean</home". The command line can parse that. TCL can't.


----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==----
http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups
----= East and West-Coast Server Farms - Total Privacy via Encryption =----

 

[Guenther Sohler]

You can redefine the bindkey
like

hiSetBindKey("Layout" "Shift<Key>z"
"hiZoomRelativeScale(hiGetCurrentWindow() 0.666)")
hiSetBindKey("Layout" "Ctrl<Key>z"
"hiZoomRelativeScale(hiGetCurrentWindow() 1.5)")

You can put this in your .cdsinit for example

 

[sunkey]

hiZoomRelativeScale(hiGetCurrentWindow() 0.5)

set ur bindkey of 'Shift<z>' on this func, and
change the 0.5 to any value u want. ( over 1,
is zoom-in, less is zoon-out)

 

[U.R. Bitchslapped]

How to make mushroom cloud over U.S. City?

alino717@hotmail.com wrote:

Hi,

I am try to make glass conductive with SnCl2 but it require lots of
time. I use the pieces of 7-3 inch have this structure.

| _____________________ |
| == == |
| _____________________ | <----------- A pot or iron
| == == |
|_______________________|
Means that placing pieces of glass in pot by placing iorn nuts between
them to saparate them. I have to remain placed the pot in fire for
about 5 to 6 hours. Thats is only problem of time.
Please guide me any other mathod to make glass conductive in the way
that the visibility of glass should not be lossed. You can also guide
about another site.


Thanks in advance,

Asad

 

[I. Bitchslapped U]

210.56.18.14 Sat,

11 Jun 2005 02:37:34 +0000 (UTC)

Hmmm- but 7:37 PST

11 Jun 2005 02:37:34 +0000 (UTC)

That puts him pretty much somewhere between NYC and London.

U.R. Bitchslapped wrote:

How to make mushroom cloud over U.S. City?

alino717@hotmail.com wrote:

Hi,

I am try to make glass conductive with SnCl2 but it require lots of
time. I use the pieces of 7-3 inch have this structure.

| _____________________ |
| == == |
| _____________________ | <----------- A pot or iron
| == == |
|_______________________|
Means that placing pieces of glass in pot by placing iorn nuts between
them to saparate them. I have to remain placed the pot in fire for
about 5 to 6 hours. Thats is only problem of time.
Please guide me any other mathod to make glass conductive in the way
that the visibility of glass should not be lossed. You can also guide
about another site.


Thanks in advance,

Asad