cell libraries and place and route

[G Vandevalk]

And furthur note that a few Fabs specify a different grid for some
layers. ( Often requiring extra approval! )

-- Gerry

"Diva Physical Verification" <diva@cadence.com> wrote in message
news:3e0n819unher0o4f59jb1nmpnojfju9a2n@4ax.com...

On Wed, 18 May 2005 14:18:40 +0200, "S. Badel"
stephane.badel@REMOVETHISepfl.ch> wrote:

I have been using Cadence for quite soemtime now but have been stumped
by this error which says "Edge not on Grid". I am using technology data
provided by my foundry.

Each technology has a minimum grid all shapes have to be aligned on.

You can usually get this value by typing :
techGetMfgGridResolution( techGetTechFile( ddGetObj( "TECH_LIB" ) ) )
or
techGetMfgGridResolution( techGetTechFile( geGetEditCellView() ) )
if you have an open cellview.

Your layout has to comply with this. If you did a lot of layout without
observing
this rule, you might be in trouble, as it can be a tedious job to correct
all
offgrid errors.

to avoid having such errors, a simple security is to set the layout snap
grid to
a multiple of the manufacturing (minimum) grid, so no point will end
offgrid.

stéphane

I would like to add a note to stéphane's observation. Few DRC rule decks
get the manufacturing grid size from the DFII database. You should check
what the values are in the offGrid rules in the DRC rule deck as well.

 

[G Vandevalk]

Also transcendental functions accuracy after 35 bits is also somewhat
open to debate. (re http://www.fourmilab.ch/babbage/library.html )

Anyone who needs >10 digits of accurracy without understanding precision
always has me a bit worried!

-- Gerry

"David Cuthbert" <"dacut at cadence dot com"> wrote in message
news:428b58e6@news.cadence.com...

fogh wrote:
That is an interesting question actually: what is the printable
precision of a SKILL float ?
x=atan(1)
printf("%-1.30e\n" x)
printf("%-1.50e\n" x)
printf("%-1.70e\n" x)

It seems to be 49 or 50 decimal places. Much than the 16 or so that the
equality test can handle.

Nah... beyond 16 decimal places, printf() is just making stuff up.

An IEEE 754 double precision floating-point number (which is what SKILL
uses) has 52 mantissa (fraction) bits plus one implicit character
(integer) bit. log10(2^53) is roughly 15.95, which rounds up to 16.

The reason why printf() thinks it can go beyond 16 decimal places is
because it keeps multiplying an imprecise floating-point fraction by 10.

I have attached a C program which illustrates this. It prints out the
floating-point number 1.0000000000000002 (== 1 + 2*10^-16), the next
representable floating-point number after 1.0, in both hexadecimal
(base-16) form along with the standard printf %lf, %.16lf, and %.22lf
forms.

It also implements its own version of printf's %lf formatter so you can
play with what's going on under the hood.

The output you will see is:

hexform: +0x1.0000000000001e+000
%lf form: 1.000000
%.16lf form: 1.0000000000000002
%.22lf form: 1.0000000000000002220446
print_double: 1.0000000000000002220446

You can see that it's making up numbers at the end.

What's going on? To your machine, 1 + 2*10^-16 and 1 + 2^-52 have the
same representation. Of course, it doesn't maintain a decimal
representation under the hood, so 1 + 2^-52 is used. 2^-52 is roughly
2.2204460492503131*10^-16... look familiar?

--
David Cuthbert dacut at cadence dot com
Cadence Design Systems +1 (412) 599-1820

----------------------------------------------------------------------------
----

#include <assert.h
#include <stdio.h
#include <inttypes.h

#define GET_SIGN(x) ((uint64_t)(((x) & 0x8000000000000000ULL) != 0))
#define GET_EXPONENT(x) ((uint64_t)(((x) & 0x7ff0000000000000ULL) >> 52))
#define GET_MANTISSA(x) ((uint64_t)((x) & 0x000fffffffffffffULL))

void print_double(double d, int nplaces)
{
int i, integral_portion;

integral_portion = (int) d;
printf("%d.", integral_portion);
d -= (double) integral_portion;

for (i = 0; i < nplaces; ++i) {
d *= 10.0;
integral_portion = (int) d;
printf("%d", integral_portion);
d -= (double) integral_portion;
}

printf("\n");
return;
}

int main()
{
double d;
uint64_t *b = (uint64_t *) &d;

d = 1.0000000000000002;
printf("hexform: %s0x1.%013llxe+%03llx\n"
"%%lf form: %lf\n"
"%%.16lf form: %.16lf\n"
"%%.22lf form: %.22lf\n"
"print_double: ",
(GET_SIGN(*b) ? "-" : "+"),
GET_MANTISSA(*b),
GET_EXPONENT(*b) - 1023,
d,
d,
d);

print_double(d, 22);

return 0;
}

 

[S. Badel]

I have set the X and Y snap in the Display Grid options to 0.15.
(although I had a doubt if this would help)
and I still ended up getting the same error. :-(

Nice try, but this prevents from creating offgrid shapes. It does not fix existing
offgrid shapes.
If you want to see your manufacturing grid, in the display options set the minor
spacing to your grid and type to 'lines'. You will see a grid on the layout on which
your shapes should be aligned.

Also, in display options turn axis display on, and check that the origin of your cell
is on the grid. This is a stupid mistake - if you happen to move the origin offgrid then
all shapes become offgrid (you'd be lucky in that case).

Please give
the exact procedure as to what I have to do to correct it.....

Put your shapes on the grid, that's it. Lokk at this post maybe :

http://groups.google.ch/group/comp.cad.cadence/browse_frm/thread/8cc1688acf39cf1a/c809293fd8f3c8b0?q=grid+group:comp.cad.cadence&rnum=1&hl=fr#c809293fd8f3c8b0

stéphane

 

[Kholdoun TORKI]

Try this one : StreamVista : http://www.semigy.com/
A free GDSII viewer. (running Windows only)

The speed is good, with nice features including zooming, ruler, etc ...

================
Kholdoun TORKI
http://cmp.imag.fr
================

Frank E. Gennari wrote:

My layout viewer isn't open source (though I did consider that option). I
would like to make it available to others, but I don't exactly own the
copyright as it was initially developed under a research grant at UC
Berkeley. Maybe I can publish some of the algorithms and ideas involved in
that project in a future paper, but I don't think I can release it as open
source.

Frank

 

[Svenn Are Bjerkem]

guan1121@gmail.com wrote:

Hi,
I'm using Affirma Virtuoso Schematic Editor to design the circuit
and later simulate using Spectre.
The question is that I want to put a subcircuit( an OpAmp), which is
defined in SPICE description from manufacturer. What instance should I
use in schematic and where should I put the text description? Is there
any other concern when using Spectre?
I really appreciate your help.

Andrew Beckett once wrote on comp.cad.cadence:
<quote>
1. Create a symbol for the component.
2. Copy that symbol to a view called "spectre" in the library manager
3. Do Tools->CDF->Edit CDF in the CIW
4. Change the form to "Base", and pick the cell.
5. Go down to the "Simulation Information" section, and click on the
Edit button.
6. Change the simulator to "spectre", and then:
Fill in the Terminal Order as the names of the symbol pins, in the
order in which they occur in the spice macromodel subckt header.
Either specify the component name as the name of the subckt, or
specify the component name as "subcircuit", and add a parameter
(further up the CDF form) called either "model" or "macro", where
the default value is the name of the subckt.

Then when you create a schematic, and have it wired up, and start
Tools->Analog Design Environment, you can then include the macro
model as a model file.
</quote>

The steps 3 to 6 can also be done by a SKILL file. The template is the
result of the cdfDump() command. (see cdfuser.pdf in documentation).
Create a textfile on disk and copy-paste the code to it. I have put some
comments into the code on the places where changes should be done. Don't
forget to create the symbol first. Then you load this modified code into
composer by load("filename").

The spice code (from .subckt to .ends) itself you put into another text
file and include it from the ADE->Setup->Model Libraries dialogue. You
may need to put a
simulator lang=spice
at the top of the spice file to avoid some warning messages.

--- 8< ---
/****************************************************/
;; Change library to a real library in your work environment
LIBRARY = "library_name"
;; Change CELL to be the name of the cell view that will be
;; black-box'ed
CELL = "cell_name"
/****************************************************/

let( ( libId cellId cdfId )
unless( cellId = ddGetObj( LIBRARY CELL )
error( "Could not get cell %s." CELL )
)
when( cdfId = cdfGetBaseCellCDF( cellId )
cdfDeleteCDF( cdfId )
)
cdfId = cdfCreateBaseCellCDF( cellId )

;;; Simulator Information
cdfId->simInfo = list( nil )
cdfId->simInfo->spectre = '( nil
;; Change termOrder to be the pin sequence defined
;; by the .subckt command.
termOrder ("PIN1" "PIN2" "PIN3")
;; Change componentName to be the name of the
;; subcircuit defined by the .subckt command
componentName "subcircuit"
netlistProcedure nil
)

;;; Properties
cdfId->formInitProc = ""
cdfId->doneProc = ""
cdfId->buttonFieldWidth = 340
cdfId->fieldHeight = 35
cdfId->fieldWidth = 350
cdfId->promptWidth = 175
cdfId->modelLabelSet = ""
cdfId->opPointLabelSet = ""
cdfId->paramLabelSet = ""
cdfSaveCDF( cdfId )
)
--- >8 ---

--
Svenn

 

[Frank E. Gennari]

It sounds like ANUVAD is a good way to go when it's time to add OASIS
support to my company's tools (unless you're a Softjin marketer in
disgise. I guess back at the beginning of the year when I tried to get
the tool the registration system wasn't fully functional. I'll certainly
have to take a look in the near future.

My layout viewer isn't open source (though I did consider that option). I
would like to make it available to others, but I don't exactly own the
copyright as it was initially developed under a research grant at UC
Berkeley. Maybe I can publish some of the algorithms and ideas involved in
that project in a future paper, but I don't think I can release it as open
source.

Frank

On Mon, 16 May 2005 02:20:55 -0400, fogh wrote:

Frank,

I gave it a quick look. So far
The registration works fine. The code compiles nicely on solaris and
linux, even if there are some strangeties in the makefiles. I tried the
programs on a few stream files (below 2GB), and it ran without trouble.
The license allows commercial use, unreleased enhancements, and binary
distribution. The directory layout is very clear and clearly mapped to
libraries and namespaces. Both the design and the library usage are
concisely and accurately documented. Only good surprises so far.

Is your openGL layout rendering code now open sourced ?

Frank E. Gennari wrote:
I tried to get Softjin's ANUVAD a few months ago. I filled out their
request form and never got anything. Eventually they called me about it
and seemed helpful, but by that time I didn't need it anymore. It seems
like ANUVAD is the right way to go, especially if you plan to work with
OASIS sometime in the near future. I'm not sure if their free source
GDSII/OASIS tools are really free for commercial purposes. I'm planning to
look into their tools in more detail later when I need the OASIS
converter so I guess I'll find out.

Frank


On Fri, 13 May 2005 17:10:32 +0200, fogh wrote:


Gerry,

I just checked Offer Kaye's page, even if I visited it not long ago (
http://groups-beta.google.com/group/comp.cad.cadence/browse_frm/thread/b0854aebc59068d3/e43edf848494b69b?q=gds2+bnf&rnum=2&hl=en#e43edf848494b69b
)
and guess what...there is something new there !

This http://www.softjin.com/html/anuvad.htm has been added at the top of the
"open source" section. They do have a library (which alliance, electric, magic,
octools and such do not have, AFAIK), but I hope they did not misuse the term
"open source" like openAccess folk do.

Let's check it out. Perfect job for a friday afternoon

G Vandevalk wrote:

On a similar note ...

does anyone have a set of C ( or C++ or some classLibrary ) of functions
to read/write GDSII. (version 6 or 5 or ... )

At my last job a co-worker had created a compliant GDSII reader/writer
in C. This was very useful in many of our custom tools. As time went on,
our company evolved into using comercial tools and this was only used
when the commercial tools had problems ( i.e. hidden 2Gig limit or
internal cell size limits, strange illegal cell names ... ) and custom
debugging
was needed.

-- Gerry @ www.ictooling.com

(still remembering the "good-old-days" when you had to write your own tools
and GDSI was the latest fad ... )



hsphuah@usa.com> wrote in message
news:1115949649.973041.18850@o13g2000cwo.googlegroups.com...


Thank you for the information. We know CIF/GDSII conversion tools are
available in the market. Unfortunately, some of them cannot integrate
into our design flow environment. In my company, we use many EDA tools

from different vendors. All EDA tools have been customized to suit our

design flow environment here.

In my layout automation team, we have only 3 engineers customized
layout automation tools. To make the matter worse, all of us have
different education and working experience. None of us knows have solid
understand about GDSII and CIF formats. My project leader thought it
was easy to implement it. I only knew the difficulty after I read
through the CNF slides yesterday.

Anyway, I am really appreciated all your helps. I had learned a lot

from the GDSII and it is good for me to understand how software

developers handle shapes, graphics and etc in binary files.

 

[fogh]

David Cuthbert wrote:

fogh wrote:

That is an interesting question actually: what is the printable
precision of a SKILL float ?
x=atan(1)
printf("%-1.30e\n" x)
printf("%-1.50e\n" x)
printf("%-1.70e\n" x)

It seems to be 49 or 50 decimal places. Much than the 16 or so that
the equality test can handle.


Nah... beyond 16 decimal places, printf() is just making stuff up.

An IEEE 754 double precision floating-point number (which is what SKILL
uses) has 52 mantissa (fraction) bits plus one implicit character
(integer) bit. log10(2^53) is roughly 15.95, which rounds up to 16.

The reason why printf() thinks it can go beyond 16 decimal places is
because it keeps multiplying an imprecise floating-point fraction by 10.

I have attached a C program which illustrates this. It prints out the
floating-point number 1.0000000000000002 (== 1 + 2*10^-16), the next
representable floating-point number after 1.0, in both hexadecimal
(base-16) form along with the standard printf %lf, %.16lf, and %.22lf
forms.

It also implements its own version of printf's %lf formatter so you can
play with what's going on under the hood.

The output you will see is:

hexform: +0x1.0000000000001e+000
%lf form: 1.000000
%.16lf form: 1.0000000000000002
%.22lf form: 1.0000000000000002220446
print_double: 1.0000000000000002220446

You can see that it's making up numbers at the end.

What's going on? To your machine, 1 + 2*10^-16 and 1 + 2^-52 have the
same representation. Of course, it doesn't maintain a decimal
representation under the hood, so 1 + 2^-52 is used. 2^-52 is roughly
2.2204460492503131*10^-16... look familiar?


------------------------------------------------------------------------

#include <assert.h
#include <stdio.h
#include <inttypes.h

#define GET_SIGN(x) ((uint64_t)(((x) & 0x8000000000000000ULL) != 0))
#define GET_EXPONENT(x) ((uint64_t)(((x) & 0x7ff0000000000000ULL) >> 52))
#define GET_MANTISSA(x) ((uint64_t)((x) & 0x000fffffffffffffULL))

void print_double(double d, int nplaces)
{
int i, integral_portion;

integral_portion = (int) d;
printf("%d.", integral_portion);
d -= (double) integral_portion;

for (i = 0; i < nplaces; ++i) {
d *= 10.0;
integral_portion = (int) d;
printf("%d", integral_portion);
d -= (double) integral_portion;
}

printf("\n");
return;
}

int main()
{
double d;
uint64_t *b = (uint64_t *) &d;

d = 1.0000000000000002;
printf("hexform: %s0x1.%013llxe+%03llx\n"
"%%lf form: %lf\n"
"%%.16lf form: %.16lf\n"
"%%.22lf form: %.22lf\n"
"print_double: ",
(GET_SIGN(*b) ? "-" : "+"),
GET_MANTISSA(*b),
GET_EXPONENT(*b) - 1023,
d,
d,
d);

print_double(d, 22);

return 0;
}

Thanks for the clear answer, Dave.

 

[Andrew Beckett]

On 17 May 2005 20:57:42 -0700, praveen.kantharajapura@gmail.com wrote:

Hi ,

I am using NCSIM simulator to simulate my VHDL code, what i wanted to
know is how to generate a Value Change dump(VCD) file using NCSIM, to
load the wave forms offline in simvision.For ex in verilog we have
"$dumpvars" , how to do it for VHDL.


Thanks in advance ,
Praveen

You'd use tcl commands to do this. For example, if this was my VHDL
code:

entity counter is
port(count: out natural);
end entity counter;

architecture behavior of counter is
begin
incrementer : process is
variable count_value: natural:=0;
begin
count<=count_value;
loop
wait for 10 ns;
count_value:=(count_value+1) mod 16;
count<=count_value;
end loop;
end process incrementer;
end architecture behavior;

I'd then do:

ncvhdl -v93 counter.vhd
ncelab -access +rwc counter

and then I'd create a tcl script:

database -vcd mydump.vcd
probe -create :incrementer:count_value
run 200ns
exit

and then do:

ncsim -input counter.tcl counter

If you do:

ncsim -tcl counter

You can enter these commands interactively, or do
things like "help database" to get more detail (if you don't feel like reading
the manual...)

Andrew.

 

[Andrew Beckett]

On 24 May 2005 20:32:32 -0700, wjcndyd@yahoo.com wrote:

Hello, can anyone advise me what the "functional" view is in Cadence
AMS simulation? Since we already have "veriloga" view, why do we need a
"functional" view? Thanks for your help!

Often functional views contain a digital Verilog "functional" model. The view
name is purely convention though.

Andrew.

 

[Andrew Beckett]

On 24 May 2005 23:18:11 -0700, wjcndyd@yahoo.com wrote:

I'm wondering if there are detailed documentation for the usage of
adc_dnl_8bit... Thanks!

Did you read the comments at the top of the Verilog-A code? (in the veriloga
view of this cell in ahdlLib). It seemed reasonably clear to me..

Broadly speaking, this block generates the clock pulse and voltage input for
the ADC under test, and then the output of the ADC is fed back into the
adc_dnl_8bit block. It sweeps the input voltage level, does a number of
conversions, and uses the results to calculate DNL.
Various parameters control the voltage levels, timing etc.

Regards,

Andrew.

 

[S. Badel]

Is there a simpler method
(example :
1. SKILL code
not really (theoretically, yes)
2. OPTION SETTINGS IN DEF EXPORT UTILITY in ICFB.
)
not at all

The way to do it is to draw you layout using Virtuoso XL. It keeps track of the
connectivity.

Another way might be to use a tool to do connectivity extraction such as assura or
diva. using in macro-cell mode would result in an extracted view that contains your
original components plus connectivity. Then you can use skill to <<cross-probe>>
between the layout and the extracted view and <<back-annotate>> the connectivity
to the layout. not a very easy solution indeed.

why would you want to export custom layout to DEF? is it a standard-cell layout
which you placed and routed by hand?

cheers,
stéphane

 

[S. Badel]

Running skill checks we think the DBUperUU is defaulting to ~/.cdsenv
value.
DBUPerUU in 5.0+ is looked for firt on the library properties, then in the

..cdsenv, then using the default of 1.0.
If your library doesn't contain the DBUPerUU property, and you and your colleague
have different values specified in .cdsenv then that would give different results.
Figure out what is the correct DBUPerUU and add this property to the library.
as a hint, it's usually 1000 for maskLayout and 160 for schematic and schematicSymbol.

But what has that got to do with avTech library.
We did not even start Assura yet.
Nothing, as far as I know. My guess is that the complain comes from the cds.lib

defining the avTech library, but the library cannot be found. You should inspect
your colleague's setup.

stéphane

 

[Andrew Beckett]

On 25 May 2005 06:55:00 -0700, wjcndyd@yahoo.com wrote:

Dear Andrew (and others),

Thank you so much for your quick reply!! Since I'm fairly new to this,
I still have a few things which are not clear.

1. You mentioned "this block generates the clock pulse and voltage
input for
the ADC under test". But I remembered in the adc_dnl_8bit block, vout
is the only output, and vclk is supposed to be an input terminal, how
could we feed these two into the ADC under test?

No, vclk is an output as well. The model itself doesn't actually define pin
directions, but if you look in the code, there's a contribution for the vclk
output:

V(vclk) <+ transition(vclk_val,0,30u,30u);

Ah, I see the problem. The pin on the symbol is an input pin. Well, it
shouldn't be, and that's a bug. I'll file a PCR for that.

So, connect it up as if it were an output, and ignore the schematic
checker warning about you having a floating net.

If you're really worried, take a copy of the cell and change the pin direction
on the symbol of the vclk pin.

2. What I was doing is, I use a ramp source as the input for the
ADC_under_test, whose outputs go into adc_dnl_8bit block, and I use a
clock source to feed into the both blocks (ADC_under_test and
adc_dnl_8bit block), but I keep getting error: the net29 (i.e., vclk of
adc_dnl_8bit block) forms a rigid loop (shorts) when added to circuit
(Vclk: 0). Could you advise what's wrong here?

Well, this is because the V(vclk) contribution above is a voltage source, and
you're shorting it out with another voltage source. Which isn't allowed (not
without lots of sparks!).

3. What exactly is the output of adc_dnl_8bit block? How can we get the
DNL plot directly out of it?

It doesn't plot DNL - but prints it out. Look in the code, it's pretty
obvious!

Many thanks! Your help will save me days of time, so I really
appreciate your previous time!

 

[Andrew Beckett]

On Wed, 25 May 2005 19:53:49 +0100, Andrew Beckett
<andrewb@DcEaLdEeTnEcTe.HcIoSm> wrote:

Ah, I see the problem. The pin on the symbol is an input pin. Well, it
shouldn't be, and that's a bug. I'll file a PCR for that.

I filed PCR 802181 to get this pin direction corrected.

Andrew.

 

[David Cuthbert]

Aaron wrote:

Anyone know of a quick way to convert cdl netlist to verilog please ?

Hm... well, CDL is a netlist, while Verilog is a descriptive language.
I see no reason why it *couldn't* be done, but I'm not so sure it
*ought* to be done...

What problem are you trying to solve with this? Have you looked at the
Design Data Translator's Reference (cds_root/doc/transref/transref.pdf),
chapter 5? That will tell you how to import a CDL netlist into a
database; from there, you should be able to use ADE, etc., though I have
to admit that I'm unfamiliar with CDL.

--
David Cuthbert dacut at cadence dot com
Cadence Design Systems +1 (412) 599-1820

 

[Richard Griffith]

jmailguard-1@yahoo.com wrote:

In gdsii files, what are box records used for? How should they be
interpreted by a gdsii reader? Are they generated by many cad
programs?

I've seen some cadence documentation that says that they should have 5
XY coordinates (similar to a boundary) and other cadence documentation
that says that they are defined by a center coordinate and width and
height. Which is correct?

Here is a complete BNF description of the GDSII format

http://www.xs4all.nl/~kholwerd/interface/bnf/gdsformat.html#GDSBNF

<box> ::= BOX [ELFLAGS] [PLEX] LAYER BOXTYPE XY


----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet News==----
http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ Newsgroups
----= East and West-Coast Server Farms - Total Privacy via Encryption =----

 

[Frank E. Gennari]

On Thu, 26 May 2005 10:28:55 -0700, jmailguard-1@yahoo.com wrote:

Thank you, but that didn't really answer my question. There seems to
be no readily available information about several things related to box
records:

1-How are boundary and box records different? Why would a cad program
write out a box record instead of a boundary record?
2-What is the meaning of BOXTYPE?
3-There is conflicting cadence documentation on the XY data. One
reference says the XY should have 5 points (I assume the points define
the perimeter of the box) another reference says that the XY data
should contain the center point and height/width information.
4-Are box records generally accepted by cad programs / foundaries? The
mosis website says that box records are read but ignored.

The way I understand it, the box record is the same as the boundary record
except that there are exactly 5 points. Boxes are rectangles, and the five
points represent the four corners of the rectangle with the last point
being a duplicate of the first point just like in boundaries: (x1,y1),
(x2,y1), (x2,y2), (x1,y2), (x1,y1).

The boxtype is similar to a datatype (I could find no documented
difference). Some tools might write rectangles as boxes and others might
write them as boundaries. It seems to make sense to use boxes to represent
rectangles and boundaries to represent 4-vertex polygons that are not
rectangles. Or maybe boxes were originally meant to define bounding boxes
or special drawing areas of a layout. I really don't know why there is a
box record or why any program would treat boxes differently than
boundaries. Ignoring boxes seems odd, but you should definitely find out
what your foundary does with boxes and change the record types to
boundaries (and boxtypes to datatypes) if boxes are ignored.

Frank

 

[tritue]

The problem with verilog import is parameter.
let say we have a transistor w=3u l=0.5u. How can we write a verilog
description to import this transitor + parameter into a schematic? Any idea
?

It will be much simpler usinf cdlIn with ic5.141

TTT
"Jim Mittel" <ejm009@freescale.com> wrote in message
news:d6vbpt$91e$1@az33news01.freescale.net...

Aaron

I suspect you want to use VerilogIn to build a schematic.
I did the same thing once.
Enclosed is C code for cdl to Verilog converson.
My coding skills are not the best.

"Aaron" <Aaron.J.Smith@nsc.com> wrote in message
news:1116592815.163017.73420@z14g2000cwz.googlegroups.com...
Guys,
Anyone know of a quick way to convert cdl netlist to verilog please ?

Thanks,

Aaron.

 

[Pete nospam Zakel]

In article <1117183194.340337.180720@o13g2000cwo.googlegroups.com> "Flash" <flash79@gmx.de> writes:

Dear All,

I have created a Form with an InputField using hiCreateStringField()
and I want to check the entered string if it has reached a length of 10
(during typing).
Therefore I use the ?modifyCallback argument as follows:

***
l_field=list(hiCreateStringField(
?name 'strfield
?prompt "Prompt"
?modifyCallback "if(strlen(Form->strfield->value)<=10
then x=t
else x=nil)"
?value "xyz"
) 0:30 200:30 100)
***

The Form works properly until I try to enter something into the field.
Then I get this:

Form->strfield->value="xyzq"
*Error* eval: not a function - 'strfield
*Error* car: Can't take car of atom - ERROR

What have I done wrong?

The value of the field itself doesn't contain the value you want to verify,
so what you are doing wouldn't work even if it weren't the wrong thing to do
in the first place. The modify CB is passed arguments: the field name, the
new value, and the source of the change (t for programmatic, nil for user
entry).

The return value from the modify callback will be t for "accept the change",
nil for "reject the change", and a different value for "replace changed value
with this value".

You want to do something like:

(defun MyModifyCB ( field value changeSource ) strlen(value)<=10)

l_field=list(hiCreateStringField(
?name 'strfield
?prompt "Prompt"
?modifyCallback "MyModifyCB"
?value "xyz"
) 0:30 200:30 100)

-Pete Zakel
(phz@seeheader.nospam)

"The man who sets out to carry a cat by its tail learns something that will
always be useful and which will never grow dim or doubtful."
-Mark Twain

 

[S. Badel]

Use the switch/stop view lists to control netlisting.
That is, create a stopping view for the cells you want to stop at.
prFlatten wants abstract view to stop at (it will need a prCellType property,
i think). There is a hierarchy browser with prFlatten to generate auto-abstracts
for the cells that do not have one - not very user-friendly, though.
Best is to use the abstract generator.

stéphane


Achintya wrote:

Hello,

Can anybody say if we can do a flattening of the schematic netlist to
an arbitratry level?

...Because the netlist flattening tool in cadence design tools flattens
the netlist to lowest level that is till the library defined elements
such as the pmos and nmos...but what we want is to flatten till a user
defined symbol.

-vs_p.