cell libraries and place and route

[S. Badel]

But if in set switch option I set only "skip soft connect check " then in
the extracted view I am able to see nt layers.

Why don't you use device-only (without parasitics) extraction for LVS, and
parasitics extraction for simulation?
That would solve your problem, I guess. You do not need parasitics for LVS.

stéphane

 

[m]

On 4 May 2005 23:10:21 -0700, "eda_cadence" <aravindhere@gmail.com>
wrote:

hi friends
i set floorplan for my design as follow
cluster (chip )size
Top - bottom (0 -58)
left - right (0-57)
i/o - core
spacing for all t,b,l,r is 4

how i set power stripes for metal layer in Umc18 lef library
for met6 spacing is 0.60 and width is 0.44(i read from lef library).
please help what data i have to set in
stripe width =?
number of stripes =?
net names =?
start from distance =?
stop from distance =?
stripe spacing =?
net spacing =?

and i also wanna know in what way i can set the number of power
stripes.
thanks
regards
aravind

set_power_stripe_spec documentation is pretty clear but I hope I can
help you with some suggestions. The number of stripes and the width of
stripes are determined by how much power your block requires. A rough
rule of thumb is to use 1 micron per mA of power you need. To decide
the power you can use an estimate based on how many nand2 equivalent
cells you have, what frequency you're running at etc. The standard
cell library docs should have some method of estimating power
consumption of individual cells.
The net names should be the same as that you get from the cell
libraries LEF file. Use the same net names which appear in the macro
lef. Each cell should have a power and ground pin (usually VDD and
VSS).

 

[m]

On 5 May 2005 05:14:36 -0700, "eda_cadence" <aravindhere@gmail.com>
wrote:

thanks mk,
but i didnt get your point, 1u/mA means, ur telling about width of
power stripes or number of power stripes, pls tell with an example then
only i can understand. i m not so brillant to understand immediately.
The product of the two. In other words, estimate the total power

requirement and bring in enough metal to carry the current. This tells
you the total width of all stripes. You also have to consider that the
row VDD,VSS connections have some IR drop so you have to distribute
this total metal more or less evenly across the macro so put one
VDD,VSS stripe per 150~200U. So if you need 100 mA, use total of 100U
of VDD and VSS and distribute it into 20~30U stripes of say 5 micron
apart.

is it any way/command to find number of nand equalivence in my design.
pls explain with an examples
thanks

"report_area -hi -cells" in PKS. Find the area of nand2(x1) and
divide the total size to that number.

hope this helps.

 

[S. Badel]

hi
if anyone knows how to capture /save demosondemand video lecture .
thanks
have a nice day

put a cam in front of your screen
easy and it works great!

 

[S. Badel]

Hi,
thanks for your nice post. link to a picture, clear explanation, proper
english, this definitely deserves an answer.
I'll do my best...

Now what I need to do is automate the whole process of simulating this
Model (with varied bit adders) using spectre. To be frank I am not sure
whether its worth it.

I don't think so. If it's for 3 cases (8, 12 and 16 bits) then it would
probably be a lost of time trying to automate this in the general case.

I have some Idea that the Automation has to be done using Ocean
Scripting language and SKILL. But not sure exactly how I can go about
doing this.

It's not clear what you want to automate. OCEAN is great for running
simulations and extracting results, and since it's part of a
full-featured scripting (SKILL) language you can go about doing many
things - definitely worth putting your hands on it.

But when it comes to changing the circuit /topology/ (i.e. having
variable number of sources) then it can't do much for you. Still it's
feasible to modify you schematic accordingly before netlisting it, but
in my opinion for such kind of work it is easier to produce the netlist
yourself (or, at least, the varying part of it).

(I'm not sure i fully understood what you want to do, please give some
more if I didn't)

cheers,

stéphane

 

[fogh]

Hi Kvaddina and Stephane,

S. Badel wrote:

Now what I need to do is automate the whole process of simulating this
Model (with varied bit adders) using spectre. To be frank I am not sure
whether its worth it.
I don't think so. If it's for 3 cases (8, 12 and 16 bits) then it would
probably be a lost of time trying to automate this in the general case.

True. The automation will pay off only if you have to do those 3
simulations over and over ( for instance if you want to run over all
corners, temperatures, supply conditions, extracted views etc...)

I have some Idea that the Automation has to be done using Ocean
Scripting language and SKILL. But not sure exactly how I can go about
doing this.
It's not clear what you want to automate. OCEAN is great for running
simulations and extracting results, and since it's part of a
full-featured scripting (SKILL) language you can go about doing many
things - definitely worth putting your hands on it.
But when it comes to changing the circuit /topology/ (i.e. having
variable number of sources) then it can't do much for you. Still it's
feasible to modify you schematic accordingly before netlisting it, but
in my opinion for such kind of work it is easier to produce the netlist
yourself (or, at least, the varying part of it).

It seems you do not need to change the topology, but only the content
of the PWL files and the verilogA model. So you can work at the file
level. Simply overwrite your files between each run and you are done.
for instance do:
/* __ */
foreach(wl list(8 12 16)
cmd=strcat(
"cp"
" "
"path/to/veriloga/model/mymodel_" sprintf(nil "%L" wl) ".va"
" "
"path/to/veriloga/model/mymodel.va"
)
system(cmd)

;;; do the same with the pwl files
;;; run your simulations and posprocess steps relevant for this "wl"
);foreach
/* __ */

Assuming you have named the files mymodel_8.va mymodel_12.va mymodel_16.va

 

[fogh]

eda_cadence wrote:

it is difficult to capture like that . so do u know any software to
capture continuous movie in screen.

David C. mentioned vnc2swf a few days ago.

 

[Andrew Beckett]

On 5 May 2005 13:02:08 -0700, "mekhail" <mekhail@gmail.com> wrote:

Hi
I am getting an error message

"*Error* length: argument must be a list or an array - "("\"Y\" \"A\"
\"B\" \"VDD\" \"VSS\" \"VBULK\")"

when i run the spectreSverilog simulator for mixed signal design. does
anyone have any ideas as to the origin of this error? ... and what i
can do to fix it?

thanks,
mekhail

No, is the answer - which is probably why you didn't get an answer the first
time you posted the question.

It probably depends on where the error message came from. You might be able to
give me a clue by doing:

sstatus(stacktrace 50)
_stacktrace=50

(I'm never entirely certain which one is necessary - they ought to be
equivalent...)

and then doing the netlist and run, and posting the whole stacktrace from the
CDS.log file - to give a clue as to where it is failing - i..e what it is
doing at the time.

Regards,

Andrew.

 

[Svenn Are Bjerkem]

Roland.Fontaine@gmail.com wrote:

I'm trying to create a string that contains quotes and need some help.
I've tried strcat("my \"name\" is Tom") but this leaves the \ in the
result.
The result I want should look like this "My "Name" is Tom", can anyone
give me some direction on how to build this string.

printf( "%s" strcat("my \"Name\" is Svenn"))
gives
my "Name" is Svenn

so it seems that your string must be correct if it is used by some other
function accepting strings.

--
Svenn

 

[Andrew Beckett]

On Mon, 09 May 2005 17:15:11 +0200, Svenn Are Bjerkem <svenn.are@bjerkem.de>
wrote:

Roland.Fontaine@gmail.com wrote:

I'm trying to create a string that contains quotes and need some help.
I've tried strcat("my \"name\" is Tom") but this leaves the \ in the
result.
The result I want should look like this "My "Name" is Tom", can anyone
give me some direction on how to build this string.

printf( "%s" strcat("my \"Name\" is Svenn"))
gives
my "Name" is Svenn

so it seems that your string must be correct if it is used by some other
function accepting strings.

It's all to do with whether you display a string using the default print
representation of a string (which is in a form where the string could be
used as input, and hence displays the escapes), or using printf/sprintf/fprint
(as Svenn suggested) which shows the final intended output.

Regards,

Andrew.

 

[S. Badel]

Roland.Fontaine@gmail.com wrote:

I've tried this, but I don't believe you can assign the printf result
to a variable to use in the future. I have also tried the sprintf
function, but this returns the \ in the result.

What Svenn was trying to say is, the string actually holds what you want.
When you do the assignment, it displays with the escaped quotes :

a="some text \"quoted text\" some text"
=> "some text \"quoted text\" some text"

but when you use the string, its content is correct :

printf("%s\n" a)
=> some text "quoted text" some text

note, you do not need strcat().

stéphane

NB: i believe the value of string variables is displayed quoted to distinguish them from symbol
names and numbers. otherwise, you wouldn't be able to make a difference between 'a and "a", or
between 1.34 and "1.34".

 

[Andrew Beckett]

On 9 May 2005 07:09:44 -0700, "David Chinn" <drc_98@yahoo.com> wrote:

Hi there,

We are planning upgrade from DFII4.46 to the latest 5.xx, can anyone
give me an idea what exact equivlent feature names of our existing 4.46
are in 5.xx?

Right now we have licenses for:
300 Virtuoso Layout Editor
3000 Virtuoso-Xl Layout Editor
34500 Virtuoso Schematic Composer
32140 Cadence Anolog Mixed-Signal Simulation Interface Option
33301 Cadence Analog Mixed-Signal Back-Annotation Interface Option
940 Virtuoso EDIF 200 Reader
945 Virtuoso EDIF 200 Writer
SkillDev
PlotVersa
Virtuoso_Schem_Option

Thanks

David

You would be best to ask your sales account manager about that. However, the
product numbers are the same. Some of these (32140, 33301) are for
backwards compatibility - they're bundled in other tools (34510 - Analog
Design Environment - which strangely you didn't list. 32140 and 33301 are,
and always have been, useless without 34510).

Andrew.

 

[S. Badel]

You can input verilog or DEF netlists into SE.

I used to do this:
File->Export->PRFlatten
=> creates an autoLayout view
File->Export->DEF
=> export the autoLayout to DEF

stéphane


Seagull wrote:

Hi,

Could anyone pls inform me how to translate the design data details
from Virtuoso composer schematic to Silicon Ensemble

thanks in advance

Seagull

 

[Guenther Sohler]

Hallo

* gds file sizes must always be multiples of 2048 bytes. Always pad with
'0's to make file file size a multible of 2048 bytes.

* maybe you swapped decimal and hex presentation of the code for the
stream record. Which stream record did you want to put to the file ?

The format of a record is
<Total byte len of record> as 2 Bigendian Bytes
<Record type > as one byte
<Data type> as one byte
<Total byte len-4 bytes of data>

When you send me your gds file, I can probably tell you the error.

 

[Bernd Fischer]

Dear Reuben,

I'm just wondering why your ground nodes have different names
in schematic and layout, is it because you need gnd! in the schematic
as simulator reference?

Have you had a look at the inherited connections method, where
you can overwrite a default net name e.g. gnd! with a user defined one
gnda! in the schematic.

Maybe this solves the problem.

Coming back to your question, you should be able to
do a search in the extracted view
Edit->Search then search for any shape and add the
criteria net name, you can do a replacement as well
with the search form.

But you have to take care of your extraction time
stamps in the cellview properties (shift q) when you try to
simulate the extracted view.

Bernd

reubenwilcock@hotmail.com wrote:

Hi all,

I am using a flow which includes Diva LVS, but because my layouts and
schematics use different grounds (gnd! and gnda!) the LVS gets upset
about the substrate being connected to different nets. I have to create
a special LVS version of my schematic and layout and ensure that there
is only one net connected to the substrate (i.e. either gnd! or gnda!).
This is a pain to do and it would be great if I could write a script to
search the extracted view (is it just a netlist?) and replace any
occurrences of gnda! with gnd!. I would also like to be able to do this
with the schematic, but I guess it would have to be easy to change it
back after the LVS...

Any ideas or suggestions welcome.

Also did anyone ever manage to get remote simulation in analog artist
working on a machine which requires a username/password? I need some
way of auto signing into the machine without requiring a password - I
can do this with ssh but I think the remote simulation uses rsh?

Cheers,

Reuben

 

[Bernd Fischer]

Reuben,

Hope that makes sense. I shall look at inherited nets - I never really
understood exactly how they functioned.

I think inherited connection will then not help here to solve the LVS
issue.
But you can find a good app not here:
http://sourcelink.cadence.com/en/infomgmt/AppNoteResult.jhtml?product=Composer&displayname=Virtuoso+Composer

I most of the design kits I have seen, there is a dummy layer
to separate substrate if you have more than one net connected
to it in layout, for LVS purpose.

The Diva rule file should then look similar to this, somewhere at the
top:

;; derive Substrate
bulk = geomBkgnd()
psub = geomAndNot( bulk nwell )
psub2_up_03 = geomSize( psub2 .03 )
psub_temp_a = geomAndNot( psub psub2_up_03 )
psub_temp_b = geomAnd( psub psub2 )
psub = geomOr( psub_temp_a psub_temp_b )

where pusb2 is the dummy layer to separate the substrate.
psub2 = geomOr( "PSUB2" )


If you follow your idea,
the problem of a change to one common ground node is
to remember where and what the old values for the nets have been.
No mater if you change them manually or over a user interface
or over a script.
You have to have anyhow two cellview pairs for LVS and one
for real live I guess.


Bernd



reubenwilcock@hotmail.com wrote:

Bernd,

Sorry, I must have not been clear - both the schematic and layout are
identical - both have both gnd! and gnda! in various places to seperate
digital and analogue functionality. So, the LVS should work as they
*are* identical. However, it appears that it gets confused because it
assumes one net for the whole substrate so having two net names on
there throws up (incorrect) mismatches. All I want to do is to
temporarily change *both* the layout and schematic so that all the
gnda! nets (in both the layout and schematic) are renamed gnd! just for
the LVS. Of course at a higher level (e.g. testbench circuit) the gnda!
and gnd! are connected (through a tiny resistor for example) but I need
to keep them as seperate nets becuase they will be connected to two
different pins on the chip (for noise reasons).

Hope that makes sense. I shall look at inherited nets - I never really
understood exactly how they functioned.

Cheers,

Reuben

 

[S. Badel]

i don't think so.
the numbers are written differently but they are the same.

stéphane

tnk11@yahoo.com wrote:

Hi all,
I would like to generate hspiceS for my digital layout. Since the
layout contains more than 10 thousands transistors, generating hspiceS
for this big layout becomes a big problem. What I did is generating the
netlist in spectre format and changing it to hspice format using perl.
I notice that the ways of representing the floating number in two
different netlist formats is as follow.
hspice --> 0.123e-6
spectre --> 1.23e-7
So when I convert from spectre netlist to hspice netlist, do I have to
change this floating format also? If I don't change it and use it in
nanosim simulator, will it effect the accuracy of simulation result?
thank in advance.

tnk

 

[fogh]

Michael wrote:

Problem Solved,
Cadence version compatibility issue.
Please give more details, and this will be a solution that goes into the Great

Wide Marvelous Usenet Knowlege Base. Otherwise it will be useless. Choose you side.

Is there any version of IC that flattens pcells improperly ?
(And, BTW, why are you flattening pcells when it seems you simply want to stream
out ?)

 

[fogh]

S. Badel wrote:

But if in set switch option I set only "skip soft connect check " then in
the extracted view I am able to see nt layers.


Why don't you use device-only (without parasitics) extraction for LVS, and
parasitics extraction for simulation?
That would solve your problem, I guess. You do not need parasitics for LVS.

But probing is much nicer if you can do an "lvsbx" ...

 

[G Vandevalk]

I think that you really need 3 ground nets.

As per the paper I wrote for the 1996 ICU:
you have only one substrate
you have a ground connection for analog
you have a ground connection for digital

The reasons for this are very clear. (i.e. Kelvin connection
co-efficents. )

The analog circuit needs to be quiet so that frequency noise is minimized.
(i.e. Star routed supplies minimizing the common mode paths to coupled
ccts.)

The digital circuit needs to be a solid rail. The smaller the deviation from
reference
ground, the more the problems.
( So a mesh layout of this net reduces the resistance at the cost of more
coupled HF noise. )

Since these design constraints are at odds with each other, some circuits
separate out the
digital gnd from the analog gnd. This is complicated by the use of global
nets. Global
nets are problematic in Cadence when you try to short them directly.

My personal solution is to model connections to the substrate ( i.e. P+
diffusion in the
P-Sub ) as a small (>1ohm) resistor. This device is something I require in
the schematic
when a cct has a substrate contact. ( it is a 1 terminal device with the
second terminal connected
to the virtual ground net 0! ) Also LVS allows permuteParallel on this
device.

Now you can get clean LVS without needing two versions of everything.

YMMV.

-- Gerry Vandevalk ( www.ictooling.com )





<reubenwilcock@hotmail.com> wrote in message
news:1115807480.705496.168570@g49g2000cwa.googlegroups.com...

Hi all,

I am using a flow which includes Diva LVS, but because my layouts and
schematics use different grounds (gnd! and gnda!) the LVS gets upset
about the substrate being connected to different nets. I have to create
a special LVS version of my schematic and layout and ensure that there
is only one net connected to the substrate (i.e. either gnd! or gnda!).
This is a pain to do and it would be great if I could write a script to
search the extracted view (is it just a netlist?) and replace any
occurrences of gnda! with gnd!. I would also like to be able to do this
with the schematic, but I guess it would have to be easy to change it
back after the LVS...

Any ideas or suggestions welcome.

Also did anyone ever manage to get remote simulation in analog artist
working on a machine which requires a username/password? I need some
way of auto signing into the machine without requiring a password - I
can do this with ssh but I think the remote simulation uses rsh?

Cheers,

Reuben