cell libraries and place and route

Aby wrote:
Hi everyone,
I am trying to write some SKILL code for generating a custom power
grid. After dumping the metal rails at different layers, I am now
trying to create vias that would connect rails on different metal
layers. Is there any function in SKILL that would compute the overlap
region between the metal rails at different layers and automatically
insert vias?

Would appreciate any comments.

saby.
Have fun. This makes a whole lot of contacts. Masks the contact sets by
the top and bottom layers of the vias undersized by the via clearance.
Then screen the remaining shapes to make sure they are all still full
size. This was even tied to a bindkey.

Make sure you get the via properties correct.


;; RGfillVias() - fill areas below selected metals with vias


;; Contains
;; RGfillVias( ?cv - cellView, defaults togeGetEditCellView()
;; ?dontFill - layerPurposePair, defaults to NIL
;; )
;; does via fill below the selected set in the current cell (cv)
;; RGshapeFillVias( cv fillShape viaSpec ?grid 0.005)
;; does via fill guided by the fillShape of the specified via
;; RGgetLayerShapes( cv layer purpose ?applyToShape func
;; ?applyToShapes func ?delete t)
;; general operator/iterator on shapes


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RGfillVias
procedure( RGfillVias(@key cv dontFill )
let( (selectedShapes viaLayers viaProps
top bot via maskShape
;; layer definitions
(poly '("POLY1" "drawing"))
(m1 '("METAL1" "drawing"))
(m2 '("METAL2" "drawing"))
(m3 '("METAL3" "drawing"))
(m4 '("METAL4" "drawing"))
(m5 '("METAL5" "drawing"))
(m6 '("METAL6" "drawing"))
;; via definitions with properties
(contactprops '(nil layer ("CONT" "drawing")
size 0.22 space 0.25
over 0.1 res 0.02 ))
(via12props '(nil layer ("VIA12" "drawing")
size 0.26 space 0.26
over 0.06 res 0.02 ))
(via23props '(nil layer ("VIA23" "drawing")
size 0.26 space 0.26
over 0.06 res 0.02 ))
(via34props '(nil layer ("VIA34" "drawing")
size 0.26 space 0.26
over 0.06 res 0.02 ))
(via45props '(nil layer ("VIA45" "drawing")
size 0.26 space 0.26
over 0.06 res 0.02 ))
(via56props '(nil layer ("VIA56" "drawing")
size 0.36 space 0.35
over 0.51 res 0.02 ))
;; temporary layers
(tly1pp '("y0" "drawing")) ;; must not be
;; clobbered by RGshapeFillVias
(tly2pp '("y1" "drawing")) ;; ok to be
;; clobbered
) ;; END let

if( !cv then cv = geGetEditCellView())
if( !cv then
printf("ERROR: RGfillVias, can't find cell view\n")
else ;; good to end

selectedShapes = geGetSelectedSet()
if( !selectedShapes then
printf("ERROR: RGfillVias, no selected shapes, select
shapes to via down from\n")
else ;; good to end

;; Finish Datatables
;; source layers in order
viaLayers = list(poly m1 m2 m3 m4 m5 m6)
;; via layers in matching order, contact is below m1
viaProps = list(nil contactprops via12props
via23props via34props via45props via56props)

foreach( shape selectedShapes
for(lidx 1 length(viaLayers)-1
top = nth(lidx viaLayers)
;; check to see if top of a via layer lpp
if( and( car(shape->lpp) == car(top)
cadr( shape->lpp) == cadr(top)) then
printf("Vias down from layer %L in area %L\n"
shape->lpp shape->bBox)
;; shape is on top of via layer
bot = nth(lidx-1 viaLayers)
maskShape = dbCopyFig(shape cv)
maskShape->lpp = tly1pp ;; mask1 is tly1pp
leLayerAnd(cv tly1pp bot tly2pp)
;;tly2pp = shape && bottomLayer
dbDeleteObject(maskShape) ;; clear tly1pp
if(dontFill then
leLayerAndNot(cv tly2pp dontFill
tly1pp) ;; tly1pp = mask &! dontfill
else
leLayerAnd(cv tly2pp tly2pp tly1pp)
)
RGgetLayerShapes( cv car(tly2pp) cadr(tly2pp) ?delete t)

;; do fill of all shapes on tly1pp
via = nth(lidx viaProps)
RGgetLayerShapes( cv car(tly1pp) cadr(tly1pp)
?applyToShape
lambda( (shape)
RGshapeFillVias(cv shape via)
)
)
;; cleanup
RGgetLayerShapes( cv car(tly1pp) cadr(tly1pp) ?delete t)
) ;; END if
);; END for lidx
) ;; END foreach shape
)) ;; END tests
)) ;; END let procedure RGfillVias

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RGshapeFillVias
procedure( RGshapeFillVias(cv fillShape viaspec @key
(grid 0.005))
let( (sx1 sy1 sx2 sy2 xl
;; temporary layers
maskShape
(tly1pp '("y1" "drawing"))
(tly2pp '("y2" "drawing"))
(tly3pp '("y3" "drawing"))
(epsilon 0.1) ;; normalized rounding offset
)
;; vias
;; clear temporary layers
RGgetLayerShapes(cv car(tly1pp) cadr(tly1pp)
?delete t)
RGgetLayerShapes(cv car(tly2pp) cadr(tly2pp)
?delete t)
RGgetLayerShapes(cv car(tly3pp) cadr(tly3pp)
?delete t)

;; start with original shape and size of shape
maskShape = dbCopyFig(fillShape cv)
maskShape->lpp = tly2pp
sx1 = caar(maskShape->bBox)
sy1 = cadar(maskShape->bBox)
sx2 = caadr(maskShape->bBox)
sy2 = cadadr(maskShape->bBox)
;; tly1 is masking shape for via coverage
if( viaspec->over then
;; shrink fill area by viaspec->over
leLayerSize(cv tly2pp -viaspec->over tly1pp)
sx1 = sx1 + viaspec->over
sx2 = sx2 - viaspec->over
sy1 = sy1 + viaspec->over
sy2 = sy2 - viaspec->over
else
leLayerSize(cv tly2pp 0 tly1pp)
)
dbDeleteObject(maskShape)

;; now fill entier bBox area with via shapes in tly2pp
while( sy1<sy2
xl = sx1
while( xl<sx2
dbCreateRect(cv tly2pp list(list(xl sy1)
list(xl+viaspec->size sy1+viaspec->size)))
xl = xl+viaspec->size+viaspec->space
)
sy1 = sy1+viaspec->size+viaspec->space
)

;; apply mask to tly3pp
leLayerAnd(cv tly1pp tly2pp tly3pp)

;; delete clipped shapes
RGgetLayerShapes(cv car(tly3pp) cadr(tly3pp)
?applyToShape
lambda( (shape) ;; rectangle of size viaspec->size
if( or( shape->objType != "rect"

fix((caadr(shape->bBox)-caar(shape->bBox))/grid+epsilon)

!= fix(viaspec->size/grid+epsilon)

fix((cadadr(shape->bBox)-cadar(shape->bBox))/grid+epsilon)

!= fix(viaspec->size/grid+epsilon)
) then
dbDeleteObject(shape)
)
) ;; END lambda
)

;; move good shapes to contact layer
;;printf("INFO: vias to layer %s %s\n",car(viaspec->layer)
cadr(viaspec->layer))
leLayerAnd(cv tly1pp tly3pp viaspec->layer)
;; clear temporary layers
RGgetLayerShapes(cv car(tly1pp) cadr(tly1pp)
?delete t)
RGgetLayerShapes(cv car(tly2pp) cadr(tly2pp)
?delete t)
RGgetLayerShapes(cv car(tly3pp) cadr(tly3pp)
?delete t)

)
);; END RGshapeFillVias


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
RGgetLayerShapes
(procedure RGgetLayerShapes( cv layer purpose
@key (delete nil) (applyToShape nil)
(applyToShapes nil))
(let (shapes)
foreach( lpp cv~>layerPurposePairs
if( and( lpp~>layerName==layer
lpp~>purpose==purpose) then
shapes=lpp~>shapes
))

if( length(shapes) != 0 then
if( applyToShapes then ;; applyToShapes
apply(applyToShapes list(shapes))
)
if( applyToShape then ;; applyToShape
foreach( shape shapes
apply(applyToShape list(shape)))
)
if( delete then ;; delete
foreach( shape shapes
dbDeleteObject( shape ))
)
)
shapes
)
) ;; END procedure RGgetLayerShapes



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On Thu, 21 Apr 2005 23:27:42 -0700, Aby wrote:

Hi everyone,
I am trying to write some SKILL code for generating a custom power
grid. After dumping the metal rails at different layers, I am now trying
to create vias that would connect rails on different metal layers. Is
there any function in SKILL that would compute the overlap region
between the metal rails at different layers and automatically insert
vias?

Would appreciate any comments.

saby.
Saby,
You can use leLayerAnd to get the overlap shapes between a pair of metal
layers. You can then make the result of the layer AND output to the via
layer and use some sort of negative growby on the resulting shapes to get
the vias. You could also iterate over the result of the layer AND with a
foreach and insert one or more vias of the proper size at the center of
each shape. It depends on whether the overlap regions are
simple squares or some other geometry.

Frank
 
You need to provide more information. Are you seeing an error marker
that is just an edge? Are you seeing an error message saying something
like "edge input out of order"? What tool are you using when you see
this thing?

On Sun, 24 Apr 2005 06:57:16 -0400, "brajesh" <brajesh153@yahoo.co.in>
wrote:

i am doing layout and getting some problem in the form of "edge error"
while doing drc.
i tried to remove it from display options but it is not helping. can
somebody give idea how to remove it.
thanks
brajes
 
the eddor is shown on the edges.no i am getting only the edge error. i m
using virtuso layout.
 
Allen wrote:
I got the data of ac response diagram. The x axis is frequency, y axis
is the amplitude. I want to modify the data and plot it using Excel
or Matlab. But there are "u, m, K, M, G" in the data, how can I plot
the diagram?
I'm assuming you mean that the data looks like:

Frequency,Amplitude
1M,1.005u
1.5M,1.230u
...

This is a perfect application for sed. "man sed" and/or borrow
someone's awk/sed book to learn about it. To get you started:

sed -e '1 p' -e '1 d' \
-e 's/p/e-12/g' \
-e 's/n/e-9/g' \
-e 's/u/e-6/g' \
-e 's/m/e-3/g' \
-e 's/k/e+3/g' \
-e 's/M/e+6/g' \
-e 's/G/e+9/g' filename_in.csv > filename_out.csv

What this means:
-e XXXX Execute sed command XXXX.
'1 p' If this is line #1, print it.
'1 d' If this is line #1, skip the rest of the commands.
's/u/e-6/g' Substitute ('s') the 'u' character with 'e-6'.
The 'g' on the end means do it globally; otherwise
only the first occurrence is replaced.

Text processing data files using sed, awk, etc., is admittedly a hack,
but a very useful hack for one's toolbox nonetheless.

--
David Cuthbert dacut at cadence dot com
Cadence Design Systems +1 (412) 599-1820
 
On 25 Apr 2005 20:01:39 -0700, chloe_music2003@yahoo.co.uk wrote:

Hello Andrew,

Thanks for your suggestion. I actually tried using the "Reinvoke
Simulator" option in SimVision. The simulation restarts, but the
waveforms in the Waveform window disappear, and the results come back
"????".
I tried closing the Waveform window and reopening it, but the results
are the same. No waveforms.
What did I do wrong?
Please help. Thanks very much in advance.

Kind regards,
Chloe
No idea. What version are you using? It certainly didn't do what you
describe when I tried it.

I'd also take a look in the simulator log files to see if that shows up what
is happening...

I assume you re-ran the simulation after re-invoking?

Regards,

Andrew.
 
I think you have on grid problem. Because the vistuoso suppose you draw
everything on gird.

brajesh wrote:
i am doing layout and getting some problem in the form of "edge error"
while doing drc.
i tried to remove it from display options but it is not helping. can
somebody give idea how to remove it.
thanks
brajes
 
On 27 Apr 2005 20:04:32 -0700, "eda_cadence" <aravindhere@gmail.com>
wrote:

im facing problem when i synthesis in PKS.
when i import tlf library it say
error in version ur using older 4.1v . pks 5+ need newer verison 4.3
and above. how i fix this error. i cant find any tlf library
information in www.artisan.com
how i fix my problem.
pls help me
thanks
Are you using an artisan library ? If yes, you should have a liberty
library (.lib extension) which you can read with read_dotlib instead
of read_tlf. In any case, see if you have a .lib file for the cell
library and use it instead of the tlf file.
 
On 28 Apr 2005 06:32:01 GMT, ptkwt@aracnet.com (Phil Tomson) wrote:

In article <40E4C9F9.38C71406@yahoo.com>, rickman <john@bluepal.net> wrote:
JJ wrote:

Ever hear of VPN?

I'm not sure what you are trying to suggest. If you mean he should run
the programs on an office machine using interface software from home,
that is what he wants to get away from. If you are talking about
checking out the license over the network, that is what is forbidden by
the license.

What are you suggesting?


But with VPN the license is still checked out only on the machine at
work. VPN only allows you to see your work desktop at home, so
technically it's probably legal since the tool is not actually running on
your home machine at all (your home machine only acts as a terminal).

Phil
I'm no lawyer, but I imagine most of the restrictions you are talking
about are aimed at preventing someone from buying a bunch of licenses
and renting them out. When you buy a copy of Adobe Photoshop, you're
buying the right to use it yourself, not let people with occasional need
use it instead of buying their own. Places like Kinkos that have
machines with Photoshop that you can rent by the hour have special
licensing, in much the same way video rental stores do. It allows the
vendor to recoup some of the loss from not selling more licenses. You
can buy Photoshop for $600 or so. Kinkos probably pays ten times that. I
know a $15 video at Target costs a video rental store around $100,
having worked for one once.

So stop whining about it and have your management talk to your vendor
rep. It is entirely possible that bringing up the VPN puts your home
machine "inside" your company network in a way that satisfies the
license agreement. That you are an employee of the company that bought
the license, using it to do work for the company that bought it, may
entitle you to treat your home as a qualifying work location, as long as
the VPN is up.

I work for Cadence, but I don't represent Cadence in any legal sense. So
everything but "talk to your vendor rep" is just speculation and my
opinion. Talking to your rep when you have an issue is what they are
there for, so do it. Nobody here is going to solve *this* problem for
you.
 
On 27 Apr 2005 20:04:32 -0700, "eda_cadence" <aravindhere@gmail.com>
wrote:

im facing problem when i synthesis in PKS.
when i import tlf library it say
error in version ur using older 4.1v . pks 5+ need newer verison 4.3
and above. how i fix this error. i cant find any tlf library
information in www.artisan.com
how i fix my problem.
pls help me
thanks
This is not something you are going to fix by modifying the library
yourself. Contact Artisan to get a newer library version. They stay more
or less up to date with the software changes as they come out. Your
license to use the library includes library updates, assuming you bought
the support package.
 
On 27 Apr 2005 21:53:24 -0700, "eda_cadence" <aravindhere@gmail.com> wrote:

hi
i cant install SPW 4.8.1 and 4.8.2 in my RHEL 3 WS .
" incorrect build binary which accesses errno or h_error directly.
Needs to be fixed"
if install spw with this error at every % completion it says same
error. i fix this error.
pls help me. thanks
setenv LD_ASSUME_KERNEL 2.4.1

This has come up numerous times before - try searching on google first...

Andrew.
 
Diva Physical Verification wrote:
I'm no lawyer, but I imagine most of the restrictions you are talking
about are aimed at preventing someone from buying a bunch of licenses
and renting them out.
Likewise, IANAL[*] -- IDEPOOTV[**] -- in my experience, these
restrictions are written because someone, somewhere, has abused the
system. If this is making it harder to do your job, *please* bring it
up with your salesperson or apps engineer.

A lot of us who work at Cadence (myself included) were customers of
Cadence at one point, too.

[*] I Am Not A Lawyer
[**] I Don't Even Play One On T.V.

--
David Cuthbert dacut at cadence dot com
Cadence Design Systems +1 (412) 599-1820
 
David Cuthbert wrote:
kentauta wrote:

According to a network monitoring software, a lot of packets are
trasfered between the X-server software and the Linux server running
Cadence while the property window is being closed. I do not have
such a problem at all when I run Cadence locally on the Linux server
probably because those packets are internally transferred very
quickly. In addition, I have not had this kind of problem with
SunOS-based Cadence.


Linux is... different. With the direction that X.org is taking X11, I
would expect remote X to become a non-option in a couple years.
Basically, they're trying to put a lot of stuff in the X layer (better
font services, antialiasing, vectored graphics, message busses), but
this means the client has to interrogate the server far more often.

The X11 protocol was designed in an era when CPUs were ~20 MHz, networks
bandwidth was ~10 Mbit/sec and latency was < 10 msec, and graphics
resources were tight. It made a lot of sense for the client program to
interrogate the X server -- preserving CPU and graphics resources were
very important.

Today, CPU, graphics, and network bandwidth have all increased 100x --
but the speed of light has not kept up. Interrogations between the
client and server are now (relatively) 100x more expensive.

As Zhiheng noted, VNC generally fares better. After the initial
connection is set up, the client and server generally don't interrogate
each other. The server just pushes screen updates as fast as it can to
your client, and your client sends keystrokes and mouse movements back
when appropriate.

The downside is that VNC doesn't know anything about fonts, characters,
lines, rectangles, etc. -- everything is just a bitmap to it (hence why
its protocol is called the Remote Framebuffer protocol). Large updates
(like repainting a schematic) eat up a fair chunk of bandwidth even
though relatively little data is being transferred.

I have some side/personal projects in mind on how to improve this, but
at the rate I'm going on those, I should be getting to them in 10-15
years. <sigh
Dave,

I find it a quite insightfull comment. Do you have more to say on the
matter ? like comments on LBX , nomachine NX, citrix or tarentella ?

k.r.
 
On 28 Apr 2005 15:28:17 -0700, "kk" <bkkishore@gmail.com> wrote:

Hi all,


I've genric parameter control from command line while simulating in
modelsim.


vsim -GBUSWIDTH=64


Is there any such command line option for ncsim.
+define+BUSWIDTH=64 ?
 
kvaddina wrote:

I have added my Verilog-A symbol to my circuit(8-bit Adder) and now
wanted to check whether the Verilog-A model does what it is suppossed
to do. When I try to simulate it (Transient mode..) it gives me the
following error.

Running Artist Hierarchical Netlisting ...
ERROR: Netlister: unable to descend into any of the views defined in
the view list: "spectreS cmos_sch schematic" for instance I5 in cell
Add_rpl_8.
The magic lies in the view list: veriloga is not listed, and thus the
netlister does not use your verilog-A model. You have to prepend your view
list with veriloga.

Either add one of these views to: Library:MyLib Cell:GlitchAnalyzer or
modify the view list to contain an existing view.

End netlisting Apr 28 18:59:57 2005

"Netlister: There were errors, no netlist was produced."
...unsuccessful.
...unsuccessful.

Can some one help me out. I am a Newbie to cadence.
Depending on if you use a config or schematic view for simulation you extend
the view list in the simulation window Setup->Environment ... or extend it
in the hierarchy editor directly.

I also recomend to read the anasimhelp.pdf in the
$CDS_INST_DIR/doc/anasimhelp/ directory.

--
Svenn
 
During elaboration of the design you have to add the "-generic" parameter

ncelab .... -generic GBUSWIDTH=\>64 ....
ncsim
In my case the commands look like this for setting generics of VHDL code:

ncelab -cdslib ./cds_nc/cds.lib -hdlvar ./cds_nc/hdl.var -work
worklib -message -nostdout -logfile ./cds_nc/ncelab.log -access
+wc -generic width=\>6 worklib.mult_multiplier:structure
ncsim -cdslib ./cds_nc/cds.lib -hdlvar ./cds_nc/hdl.var -logfile
../cds_nc/ncsim.log -gui -nokey -input
/vlsi_soft/etc/cds_nc/ncsim_vhdl.tcl -input ./STIM/mult_multiplier.tcl
worklib.mult_multiplier:structure


I hope this helps.

Kind regards,
Johannes Wolkerstorfer

----------------------------------------------------------------
Johannes Wolkerstorfer <Johannes.Wolkerstorfer@iaik.tugraz.at>
Institute for Applied Information Processing and Communications,
Graz University of Technology, Inffeldg. 16a, 8010 Graz, Austria
tel: +43 316 873-5515 fax: +43 316 873-5596 http://www.iaik.at/

"kk" <bkkishore@gmail.com> wrote in message
news:1114727297.165045.212990@f14g2000cwb.googlegroups.com...
Hi all,


I've genric parameter control from command line while simulating in
modelsim.


vsim -GBUSWIDTH=64


Is there any such command line option for ncsim.
 
I also face the same problem sometimes. That's true that Virtuoso expects
us to draw everything on grid. Can you tell me what should be the size of
the grid (in terms of feature size).
 
And the obvious ... passing DRC is required too!

-- G

<jayl-news@accelerant.net> wrote in message
news:1114617998.675588.110860@l41g2000cwc.googlegroups.com...
Allen wrote:
Hi,

I am making the layout of my circuit that is designed using IBM 7WL
BiCMOS technique. For space sake, I put a circuit under a dualmim
capacitor. It passed the LVS, but I still don't know if it's allowed
to do it that way?

I don't have documentation for this process, so this is just
general comments for MiM capacitors (and TSMC MiM capacitors,
where I do have experience and documentation).

1) Read the Design Rule documentation carefully. If it's
not forbidden, it's allowed. Assuming you've got an
IBM-provided DRC flow, you've run that, of course, correct?

2) Make sure the bottom plate of your MiM cap is ground, and that
it is well-connected to ground, or that you have a ground
shield underneath the MiM cap. Otherwise, you better make
sure your parasitic extraction tool is capturing the coupling
between the circuit and the bottom plate.

-Jay-
 
No -- Virtuoso does not care.

Diva/Dracula/Calibre/Hercules may care however.

The feature size is a function of who you send the data to! (and how!)


- G

"meghna" <meghna@protected_id> wrote in message
news:8484a8600c6e7b38edb7c8ce34e7f78e@localhost.talkaboutcad.com...
I also face the same problem sometimes. That's true that Virtuoso expects
us to draw everything on grid. Can you tell me what should be the size of
the grid (in terms of feature size).
 
On 29 Apr 2005 04:11:42 -0700, "eda_cadence" <aravindhere@gmail.com> wrote:

hi friends
if any one working cadence spw pls give setenv setting .
i facing problem in setting of spw.
thanks
This is how I've done it in the past:

setenv SPW_HOME /path/to/SPWinstallation
if ($SPW_HOME != "") then
set path = ($path $SPW_HOME/tools/bin)
setenv CDS_LIC_FILE 5280@myserver
setenv SPW_SYS_DB $SPW_HOME
if (-r $SPW_HOME/site_data/config/spw.cshrc) then
source $SPW_HOME/site_data/config/spw.cshrc
endif
endif

Now, I can't remember whether SPW_HOME is a required env var, or one I just
used for convenience - I think it isn't required.

Note, this is what we did when SPW was Cadence - it may need slightly
different setup now that it is released by CoWare. I don't think that much has
changed though.

Best Regards,

Andrew.
 

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