Can somebody take a peek at this circuit for me?

[Michael Noone]

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in news:%
TY%d.35$e%3.343@news.uswest.net:

You need to consider:

1. What range of output voltage (with respect to ground)
can the op-amp output cover given its connections?

-10V to 10V.

2. Given the FET source connection, how does answer
to 1 affect the gate-to-source voltage applied to the FET?

I guess that could range from 390-410

3. What is the rated gate-to-source voltage of the FET?

30V. I see your point.

When you have answers to those questions, you will have
the answer to "Why would it get killed?"

OK then well now I'm just confused - how would you switch a very high
voltage signal with a mosfet with a low voltage input? I thought one of the
big ideas of fets was that you could take a small input voltage and switch
a large input voltage - but that seems to not be right? Thanks,

-M. Noone

 

[Tim Wescott]

Michael Noone wrote:

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in news:%
TY%d.35$e%3.343@news.uswest.net:


You need to consider:

1. What range of output voltage (with respect to ground)
can the op-amp output cover given its connections?


-10V to 10V.

Not with a 741! Look at the data sheet for output range -- it'll be
"large signal output range" or just "output". At any rate it'll be more
like -8V to +8V if you're lucky.

2. Given the FET source connection, how does answer
to 1 affect the gate-to-source voltage applied to the FET?


I guess that could range from 390-410


3. What is the rated gate-to-source voltage of the FET?


30V. I see your point.


When you have answers to those questions, you will have
the answer to "Why would it get killed?"


OK then well now I'm just confused - how would you switch a very high
voltage signal with a mosfet with a low voltage input? I thought one of the
big ideas of fets was that you could take a small input voltage and switch
a large input voltage - but that seems to not be right? Thanks,

-M. Noone

I assume you're a student, and that you've gotten the usual amount of

practical knowledge (i.e. almost none).

First, be careful of the word "switch". MOSFETs will switch large
amounts of power, but "switch" implies that the device is either on
(high current but low S-D voltage drop) or off (high S-D voltage drop
but no current). What you are asking for is a circuit where the active
device is in its linear region, so you'll have high S-D voltage drop
_and_ significant current. This will cause your device to generate
heat, which you will have to arrange to dissipate.

Second, you have a non-circuit there. It looks like you've seen the
correct circuit but don't understand it. I'm going to show you a
suggested circuit, and _strongly_ suggest that you get something like
Switcher CAD from Linear Technology or some other simulation package to
investigate your circuit. So here's the circuit:


+450V
+
|
.-.
| | R3
| |
'-'
R2 |
___ |
.----|___|----------o
| | output
R1 | o------------
input ___ | |\ |
--------|___|----o----|+\ |
| >--------||-+
.-|-/ ||<- Q1
+5V | |/ ||-+
+ R4 | |
| ___ | || |
'--|___|---o-------||-------o
|| |
|
C1 .-.
| | R5
| |
'-'
|
|
===
GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

This is totally off the top of my head, and I always get at least one
thing wrong when I do that, so it's your job to figure out whether it
works, correct component values, why it works, why you need R4, R5 and
C1, and how big of a heat sink you need on Q1.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Michael Noone]

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in
news:YiZ%d.45$e%3.160@news.uswest.net:

"Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...
"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in
news:% TY%d.35$e%3.343@news.uswest.net:
...
Regarding circuit shown at:
https://netfiles.uiuc.edu/mnoone/www/Linearamplifierwithfet.jpg
[Why the FET dies resolved.]

OK then well now I'm just confused - how would you switch a very high
voltage signal with a mosfet with a low voltage input?

To do that in a DC coupled manner with a ground
referenced load and a ground referenced controller
normally requires at least 1 more transistor, itself
having similar HV withstand. The process of getting
a signal from one voltage range to another is often
called "translating". A common base amplifier could
do it for your application.

Could you reccomend a transistor that would be able to serve this
function? I've looked before for high voltage transistors and found very
little.

And don't call it "switch" when you mean to drive
the FET so that it has varying transconductance.

Well - actually I meant switch. Switching is the usage of mosfets that
I'm familiar with, using them to make a linear output is something I'm
not fully comfortable with just yet. I was asking in general, not about
the schematic that I posted.

I thought one of the
big ideas of fets was that you could take a small input voltage and
switch a large input voltage - but that seems to not be right?

That has not been contravened here.

Thanks,

You're welcome. I've set followups to sci.electronics.basics
because this kind of discussion is more topical there.

So - once a high volage transistor is used to drive the gate, what else
do I need to change to make the circuit work? Best regards,

-M. Noone

 

[Rich Grise]

On Tue, 22 Mar 2005 01:08:14 -0600, Michael Noone wrote:

xray <notreally@hotmail.invalid> wrote in
news:inev311tn8ucreeq4fg71m0hktjek74q7s@4ax.com:

Any better?

Nope.

-Michael

You seem to have attracted a couple of personal trolls.

About the circuit,
https://netfiles.uiuc.edu/mnoone/www/Linearamplifierwithfet.jpg
Where's the 400V Vdd coming from? About the only thing I really
know about "high" voltages is that they're dangerous, and hard
to design stuff with/for. And something tells me that that circuit
is smoke waiting to be let out.

Sorry.

Good Luck!
Rich

 

[John Fields]

On Tue, 22 Mar 2005 11:31:23 -0600, Michael Noone
<mnoone.uiuc.edu@127.0.0.1> wrote:

John Larkin <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in
news:8ig041puudk80v93lqk5i64dcqbn8m5h1j@4ax.com:

On Tue, 22 Mar 2005 03:13:09 -0600, Michael Noone
mnoone.uiuc.edu@127.0.0.1> wrote:

Paul Burke <paul@scazon.com> wrote in
news:3aa449F675aq5U2@individual.net:

Michael Noone wrote:


Huh?

I think that Mr. Genome is suggesting that the circuit is trivial:
if you don't KNOW whether it will work or not, you should get one of
the electronic department's technicians to look at it for you and
swap wages with him. I think he might be rather afraid that you are
one of the teaching staff of some academic institution.

Paul Burke

Well - it's a very foreign idea to me. So far in school (I'm a second
year EE) all I've been taught with FETs is how to use them as
switches.

So this will work?

Regards,

-M. Noone

Looks to me, as I understand the stated voltages, that you have 400
volts gate-to-source on this fet. That will kill it.

John


I was planning on using a high voltage FET. I was thinking something
along the lines of this: http://www.irf.com/product-info/datasheets/data/irfb17n50l.pdf - it's designed to switch 500V...
Why would it get killed? Thanks,

-M. Noone

--
John Fields

 

[Jonathan Kirwan]

On Tue, 22 Mar 2005 10:31:29 -0800, Tim Wescott
<tim@wescottnospamdesign.com> wrote:

This is totally off the top of my head, and I always get at least one
thing wrong when I do that, so it's your job to figure out whether it
works, correct component values, why it works, why you need R4, R5 and
C1, and how big of a heat sink you need on Q1.

And the rail voltages for the opamp would be .. ?

Jon

 

[Tim Wescott]

Jonathan Kirwan wrote:

On Tue, 22 Mar 2005 10:31:29 -0800, Tim Wescott
tim@wescottnospamdesign.com> wrote:


This is totally off the top of my head, and I always get at least one
thing wrong when I do that, so it's your job to figure out whether it
works, correct component values, why it works, why you need R4, R5 and
C1, and how big of a heat sink you need on Q1.


And the rail voltages for the opamp would be .. ?

Jon

Adequate for the task, if he does his job right. With the common-source
circuit shown and the right MOSFET you may be able to do this with his
+/- 10V rails, and certainly with +20V & 0V rails.

It's his job to figure out what they need to be, and how they may
interact with other component values in the system. There's a distinct
tradeoff between the choice of Q1, R3, R5, the power-handling
capabilities of the circuit, the ease of gaining circuit stability, and
the rail voltages.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Michael Noone]

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in
news:8D_%d.51$e%3.573@news.uswest.net:

Go to www.onsemi.com and try again.

OK - well I'm not entirely sure what I should be looking for, so I just
looked for a high voltage NPN BJT, and found this:
http://www.onsemi.com/pub/Collateral/MPSA44-D.PDF - Is that what you
were describing?

So - once a high volage transistor is used to drive the gate, what
else
do I need to change to make the circuit work?

I would use this configuration:

VCC
+
.----)---.
| |
.-. .-.
| | | |
| | | |
'-' '-'
| |
| |
o-----||-+
| ||-
| ||-+
| |
| |
| o------.OUT
| | |
|| | | .-.
.-----||--. |/ | | |
| || | GND-| | | |
| | |> | '-'
___ | |\| | | | |
GND-|___|-o--|-\ | ___ | | GND
| >---o---|___|----o |
.--|+/ . |
| |/| | |
| GND-|<- |
| |
___ | ___ |
IN -|___|-o---------|___|-----------------'
(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

You can set the resistors associated with the FET to
control loop gain while setting the emitter resistor
to limit the max gate drive. The response will tend
to be stable if you do not set the power amp stage
gain too high and make the integrator feedback
network pole in about the same place that the
power amp stage has its lowest frequency pole.
It inverts, so if your heart is set on the transfer
function you posted, you'll need to adjust.

I still think you need to

Correct me if I'm completely wrong [I probabaly am ] - but to me it
looks like The input could get stuck sinking a decent amount of current.
The input to this circuit is coming from a very low current (I think
about 2ma max or so) DAC board, so that needs to be avoided. I guess I'd
just buffer the input if that is the case - but I thought I should ask
to be sure.

Also - I'm having alot of difficulty figuring out what exactly is
happening in this circuit. To me - it looks like the output from the op-
amp just goes through a resistor and is then grounded. It's as if the
output form the op-amp pretty much doesn't do anything at all.
Similarly, it looks like both the base and the emitter of the transistor
are grounded, which again seems odd. Maybe I'm misunderstanding the
circuit? To me it looks like the node connecting the resistor on the
output of the op-amp and the emitter of the bjt is grounded, but maybe
I'm wrong?

Thanks for all your help, and for putting up with all my questions

-Michael

 

[John Fields]

On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:emr041dnld7pmj6v7emf5bdsvng962tqgv@4ax.com...
On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
mnoone.uiuc.edu@127.0.0.1> wrote:
...
+400V>--+-----+---D S---+----------+-------->>--+
| | G | | |
| | | [ZENER] | |
[R1] [R2] | |K | |
| | +-----+ | |
| | | | |
| +-----+ | |
| | | |
+-------------------+ Vin [R2] |
| | | | | |
| D /-|--+ | [RL]
|K G---< | | |
[REF] S \+|-------+-----+ |
| | | | | |
| | | [R3] [C1] |
| | | | | |
GND>----+-----------+-------+--------+-----+-->>--+


Use a little high-voltage FET to drive the big FET's gate. They're
cheap and it doesn't take much (damn near nothing) to drive them. Use
a micropower opamp and you can get its supply voltage from a resistor
and a low-current shunt reference tied to the 400V rail (or even just
a resistive divider) The Zener is to make sure the big MOSFET's gate
voltage never goes higher than it's supposed to, WRT to the source,
R2 R3 is the 40:1 divider, and C1 is to keep the thing from
oscillating.

It cannot oscillate no matter what value you use for C1.
Study it carefully and I'm sure you can see why.

---
Typical behavior for you. As the erroree, when you find what you
think is an error, instead of simply stating what you think it is that
makes it an error, you hold back and try to get some mileage out of it
by requiring a lot of work to be done by whom you consider to be the
errorer.

In this case, good catch, but... the larger C1 becomes, the greater
the output ripple becomes, until it starts to look like an
oscillation. The best C1 is no C1, according to bitethedust.asc which
you can find on abse and which you can run if you've downloaded
LTSPICE

--
John Fields

 

[John Fields]

On Tue, 22 Mar 2005 15:57:07 -0800, "Larry Brasfield"
<donotspam_larry_brasfield@hotmail.com> wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:fg81411s2adq8t2bhtil31jgjqmhjbubua@4ax.com...
On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:emr041dnld7pmj6v7emf5bdsvng962tqgv@4ax.com...
On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
mnoone.uiuc.edu@127.0.0.1> wrote:
...
+400V>--+-----+---D S---+----------+-------->>--+
| | G | | |
| | | [ZENER] | |
[R1] [R2] | |K | |
| | +-----+ | |
| | | | |
| +-----+ | |
| | | |
+-------------------+ Vin [R2] |
| | | | | |
| D /-|--+ | [RL]
|K G---< | | |
[REF] S \+|-------+-----+ |
| | | | | |
| | | [R3] [C1] |
| | | | | |
GND>----+-----------+-------+--------+-----+-->>--+


Use a little high-voltage FET to drive the big FET's gate. They're
cheap and it doesn't take much (damn near nothing) to drive them. Use
a micropower opamp and you can get its supply voltage from a resistor
and a low-current shunt reference tied to the 400V rail (or even just
a resistive divider) The Zener is to make sure the big MOSFET's gate
voltage never goes higher than it's supposed to, WRT to the source,
R2 R3 is the 40:1 divider, and C1 is to keep the thing from
oscillating.

It cannot oscillate no matter what value you use for C1.
Study it carefully and I'm sure you can see why.

---
Typical behavior for you. As the erroree, when you find what you
think is an error, instead of simply stating what you think it is that
makes it an error, you hold back and try to get some mileage out of it
by requiring a lot of work to be done by whom you consider to be the
errorer.

The post you quoted is one I canceled a couple of
minutes after hitting send. I mistakenly read your
upper MOSFET as a reversed P-channel device,
assuming, incorrectly, that you intended to produce
the 400V output first mentioned by the OP. As I
was reading your schematic, filling in the missing
polarity, it looked like a bistable latch. And if that
was what you had drawn, (or meant to draw), it
would have taken little time to spot it.

In this case, good catch, but... the larger C1 becomes, the greater
the output ripple becomes, until it starts to look like an
oscillation. The best C1 is no C1, according to bitethedust.asc which
you can find on abse and which you can run if you've downloaded
LTSPICE

I'm game. It's not showing up on my newserver
in alt.binaries.schematics.electronic . Can you
either email it or state what part values and
transistors you used? Or post, the .asc, which
is ASCII, so can be pasted into a post.

---
I can, but I won't. You know where it is, so find it and fend for
yourself. Or piss off.
---

I presume your comments apply to my post of
12:50, where I asked about loop gain shifts
and dominant poles. Since you elect to not
answer that, I want to simulate your circuit
and see for myself.

---
Fine. You know where the file is, so retrieve it and have at it.
---

Where did the output ripple come from? I can
see no source for it in your schematic other
than an oscillation. I'm about 95% confidant
that it will oscillate until C1 becomes huge.
The only question is where the limiting occurs.

---
Geez, I thought you said in an earlier post that there was _no way_
the circuit could oscillate, regardless of the value of C1.

Backpedaling, you phony piece of shit?

--
John Fields

 

[John Fields]

On Wed, 23 Mar 2005 00:18:43 GMT, "Genome" <ilike_spam@yahoo.co.uk>
wrote:

John, that is piss poor. Whilst Larry might not have the bananas to
tell you why he will probably sweat buckets coming up with some
'reasons'. You have done yourself and Spice a big unfavour.

---
I'm sorry to hear that and, since I respect your opinion, I'd like to
hear where I've gone awry.

--
John Fields

 

[Pooh Bear]

Michael Noone wrote:

So far in school (I'm a second year EE) all I've been taught with FETs is
how to use them as switches.

Ahah ! A fairly typical EE course by the sound of it !

So this will work?

No.


Graham

 

[Pooh Bear]

Leon Heller wrote:

Why not simulate it? If it simulates OK you can actually build it and see
what happens.

Simulation regrettably doesn't simulate the fire caused by kilowatts of
dissipation in the feedback Rs !


Graham

 

[John Larkin]

On Tue, 22 Mar 2005 11:54:38 -0600, Michael Noone
<mnoone.uiuc.edu@127.0.0.1> wrote:

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in
news:8HS%d.1$e%3.253@news.uswest.net:


You should learn to say what a circuit has to do in
terms of performance, preferably quantifiable. I
could say your circuit will "work", because you
have not really specified what that means.

Well - right now I just want to see if it even sort of works - but
eventually I want a circuit that can amplify a 0-10V signal to 0-400 with
response time of about 1ms and with accuracy to the nearest volt on the
output.

I did post my little HV amplifier circuit to a.b.s.e. a while back. It
uses an opamp driving a pair of high-voltage optocouplers, with the
phototransistor sides as the output totem pole across the 400 volt
supply. This eliminated all sorts of level shifting problems... lets
light do it! It should be about good for 1 mA drive from 400 volt
rails.

What are you going to drive?

John

 

[Larry Brasfield]

Demonstrating a reading comphrension problem here.
Reversable Derf transform applied.

"John Fields" <jfields@austininstruments.com> wrote in message
news:1vf14115li2mdsdlvjpgcqulo61sn1ged5@4ax.com...

On Tue, 22 Mar 2005 15:57:07 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:
"John Fields" <jfields@austininstruments.com> wrote in message
news:fg81411s2adq8t2bhtil31jgjqmhjbubua@4ax.com...
On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:
....
It cannot oscillate no matter what value you use for C1.
Study it carefully and I'm sure you can see why.
....
The post you quoted is one I canceled a couple of
minutes after hitting send. I mistakenly read your
upper MOSFET as a reversed P-channel device,
assuming, incorrectly, that you intended to produce
the 400V output first mentioned by the OP. As I
was reading your schematic, filling in the missing
polarity, it looked like a bistable latch.
....
I presume your comments apply to my post of
12:50, where I asked about loop gain shifts
and dominant poles.
....
Where did the output ripple come from? I can
see no source for it in your schematic other
than an oscillation. I'm about 95% confidant
that it will oscillate until C1 becomes huge.
The only question is where the limiting occurs.
---
Geez, I thought you said in an earlier post that there was _no way_
the circuit could oscillate, regardless of the value of C1.

Backpedaling [d1]?

Let's review the sequence of events here:
0. JF posts a schematic.
1. LB posts "cannot oscillate ... Study it carefully".
2. LB spots an error in said post and cancels it.
3. LB posts, 13 minutes after 1, about loop gain and dominant poles.
4. JF replies to something by quoting the cancelled post, 2 hours
and 32 minutes after post 3, (the correction) was posted.
5. LB replies, informing JF that post 1 cancelled, post 3 is up,
and claiming confidence that JF designed an oscillator.
6. JF replies, 1 hour and 13 minutes later, noting that posts 1 and 5
are inconsistent, suggests post 5 should be called "backpedaling".

To me, that sequence of events clearly indicates, at best, a
severe reading comprehension problem. Either that, or in
JFWorld, an error caught and fixed by the same person,
without any outside impetus, and freely acknowledged,
is to be deemed "backpedaling". The problem with that
view is that the "retreat" was already history, long before
you came up with any reply to either the canceled post
or its replacement. You've got the tense wrong.

I find it odd that you are happy to castigate me for never
voluntarily changing my mind, and then, given an instance
of that very action, latch onto it as cause for denigration.
I hope you will forgive me for not caring what you think.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

Derf transform extractions follow:
Dreck:
[d1: , you phony piece of shit]

 

[Fred Bloggs]

Larry Brasfield wrote:

"Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
news:Xns9621752B7559Bmnooneuiucedu127001@216.196.97.136...

John Larkin <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote in
news:8ig041puudk80v93lqk5i64dcqbn8m5h1j@4ax.com:

...

Looks to me, as I understand the stated voltages, that you have 400
volts gate-to-source on this fet. That will kill it.

John


I was planning on using a high voltage FET. I was thinking something
along the lines of this: http://www.irf.com/product-
info/datasheets/data/irfb17n50l.pdf - it's designed to switch 500V...
Why would it get killed? Thanks,


You need to consider:

1. What range of output voltage (with respect to ground)
can the op-amp output cover given its connections?
2. Given the FET source connection, how does answer
to 1 affect the gate-to-source voltage applied to the FET?
3. What is the rated gate-to-source voltage of the FET?

When you have answers to those questions, you will have
the answer to "Why would it get killed?"

That's what you say but now, but your earlier post said that it would
just be "always on"- so which is it? You're real big on being an
after-the-fact expert aren't you? After someone else told you what the
facts were...so typical of a fraud and sleaze.

 

[Fred Bloggs]

Larry Brasfield wrote:

"Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
news:Xns96217F7D8C823mnooneuiucedu127001@216.196.97.136...

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in
news:YiZ%d.45$e%3.160@news.uswest.net:

"Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...

...

OK then well now I'm just confused - how would you switch a very high
voltage signal with a mosfet with a low voltage input?

To do that in a DC coupled manner with a ground
referenced load and a ground referenced controller
normally requires at least 1 more transistor, itself
having similar HV withstand. The process of getting
a signal from one voltage range to another is often
called "translating". A common base amplifier could
do it for your application.

Could you reccomend a transistor that would be able to serve this
function? I've looked before for high voltage transistors and found very
little.


Go to www.onsemi.com and try again.

Don't know of any HV transistors off the top of your head? Hey, if
you're as clueless as the OP then why are you posing as the big expert
answering his questions?

And don't call it "switch" when you mean to drive
the FET so that it has varying transconductance.

Well - actually I meant switch. Switching is the usage of mosfets that
I'm familiar with, using them to make a linear output is something I'm
not fully comfortable with just yet. I was asking in general, not about
the schematic that I posted.


In the context you used the word, it was inappropriate
and indicates, to people sharing the same language,
that you either misconceive the circuit or are not yet
familiar with what the word really means.

That's the typical pseudo-intellectual dodge: if you're clueless about
technical issues, introduce peripheral material about semantics. The OP
may be too damned dumb to know a fake when he reads one, but not the ret
of us.

...

So - once a high volage transistor is used to drive the gate, what else
do I need to change to make the circuit work?


I would use this configuration:

VCC
+
.----)---.
| |
.-. .-.
| | | |
| | | |
'-' '-'
| |
| |
o-----||-+
| ||-
| ||-+
| |
| |
| o------.OUT
| | |
|| | | .-.
.-----||--. |/ | | |
| || | GND-| | | |
| | |> | '-'
___ | |\| | | | |
GND-|___|-o--|-\ | ___ | | GND
| >---o---|___|----o |
.--|+/ . |
| |/| | |
| GND-|<- |
| |
___ | ___ |
IN -|___|-o---------|___|-----------------'
(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

You can set the resistors associated with the FET to
control loop gain while setting the emitter resistor
to limit the max gate drive.

The response will tend
to be stable if you do not set the power amp stage
gain too high and make the integrator feedback
network pole in about the same place that the
power amp stage has its lowest frequency pole.

Really? And since when the hell does anyone design around "tend to be
stable" pseudo-intellectual? How does one go about finding the power amp
stage pole? And placing "network pole" coincident with power amp lowest
frequency pole?- You mean the "network" zero don't you, mental midget?

It inverts, so if your heart is set on the transfer
function you posted, you'll need to adjust.

You're not kidding he needs to make adjustments to things like adding a
+400V supply and a trash circuit that goes open loop for IN>0. Yeah-
that's real useful.

I still think you need to

Needs to what? Lost your thoughts? You regurgitated your p.o.s. circuit
with a bunch of nebulous references to poles and gain control resistors,
but not a single specific bit of information about any of it. Talk about
"garbage electronics"- take at look at your worthless posts.

 

[Fred Bloggs]

Michael Noone wrote:

"Larry Brasfield" <donotspam_larry_brasfield@hotmail.com> wrote in
news:8D_%d.51$e%3.573@news.uswest.net:


Go to www.onsemi.com and try again.


OK - well I'm not entirely sure what I should be looking for, so I just
looked for a high voltage NPN BJT, and found this:
http://www.onsemi.com/pub/Collateral/MPSA44-D.PDF - Is that what you
were describing?



So - once a high volage transistor is used to drive the gate, what

else

do I need to change to make the circuit work?

I would use this configuration:

VCC
+
.----)---.
| |
.-. .-.
| | | |
| | | |
'-' '-'
| |
| |
o-----||-+
| ||-
| ||-+
| |
| |
| o------.OUT
| | |
|| | | .-.
.-----||--. |/ | | |
| || | GND-| | | |
| | |> | '-'
___ | |\| | | | |
GND-|___|-o--|-\ | ___ | | GND
| >---o---|___|----o |
.--|+/ . |
| |/| | |
| GND-|<- |
| |
___ | ___ |
IN -|___|-o---------|___|-----------------'
(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

You can set the resistors associated with the FET to
control loop gain while setting the emitter resistor
to limit the max gate drive. The response will tend
to be stable if you do not set the power amp stage
gain too high and make the integrator feedback
network pole in about the same place that the
power amp stage has its lowest frequency pole.
It inverts, so if your heart is set on the transfer
function you posted, you'll need to adjust.

I still think you need to


Correct me if I'm completely wrong [I probabaly am ] - but to me it
looks like The input could get stuck sinking a decent amount of current.
The input to this circuit is coming from a very low current (I think
about 2ma max or so) DAC board, so that needs to be avoided. I guess I'd
just buffer the input if that is the case - but I thought I should ask
to be sure.

Also - I'm having alot of difficulty figuring out what exactly is
happening in this circuit. To me - it looks like the output from the op-
amp just goes through a resistor and is then grounded. It's as if the
output form the op-amp pretty much doesn't do anything at all.
Similarly, it looks like both the base and the emitter of the transistor
are grounded, which again seems odd. Maybe I'm misunderstanding the
circuit? To me it looks like the node connecting the resistor on the
output of the op-amp and the emitter of the bjt is grounded, but maybe
I'm wrong?

Thanks for all your help, and for putting up with all my questions

-Michael

LOL! GOOD CALL! And no response from the fake, Larry Brasfield. Larry
Brasfield gets put down by a complete newbie- Larry Brasfield gets
exposed as a fake, and Larry Brasfield ***skulks*** off- nowhere to be
found. LOL!!!!!!!!!!!!!

 

[Fred Bloggs]

Larry Brasfield wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:emr041dnld7pmj6v7emf5bdsvng962tqgv@4ax.com...

On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
mnoone.uiuc.edu@127.0.0.1> wrote:

...

+400V>--+-----+---D S---+----------+-------->>--+
| | G | | |
| | | [ZENER] | |
[R1] [R2] | |K | |
| | +-----+ | |
| | | | |
| +-----+ | |
| | | |
+-------------------+ Vin [R2] |
| | | | | |
| D /-|--+ | [RL]
|K G---< | | |
[REF] S \+|-------+-----+ |
| | | | | |
| | | [R3] [C1] |
| | | | | |
GND>----+-----------+-------+--------+-----+-->>--+


Use a little high-voltage FET to drive the big FET's gate. They're
cheap and it doesn't take much (damn near nothing) to drive them. Use
a micropower opamp and you can get its supply voltage from a resistor
and a low-current shunt reference tied to the 400V rail (or even just
a resistive divider) The Zener is to make sure the big MOSFET's gate
voltage never goes higher than it's supposed to, WRT to the source,
R2 R3 is the 40:1 divider, and C1 is to keep the thing from
oscillating.


It cannot oscillate no matter what value you use for C1.
Study it carefully and I'm sure you can see why.

Okay- let's see- your own circuit is a blatant p.o.s., the OP called you
on it, you ran away from answering, and now you come over to make a
comment on JF's circuit? A dumb comment by the way- two high gain stages
in the loop and you say it can't oscillate- pathetic.

 

[Fred Bloggs]

Larry Brasfield wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:fg81411s2adq8t2bhtil31jgjqmhjbubua@4ax.com...

On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
donotspam_larry_brasfield@hotmail.com> wrote:


"John Fields" <jfields@austininstruments.com> wrote in message
news:emr041dnld7pmj6v7emf5bdsvng962tqgv@4ax.com...

On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
mnoone.uiuc.edu@127.0.0.1> wrote:

...

+400V>--+-----+---D S---+----------+-------->>--+
| | G | | |
| | | [ZENER] | |
[R1] [R2] | |K | |
| | +-----+ | |
| | | | |
| +-----+ | |
| | | |
+-------------------+ Vin [R2] |
| | | | | |
| D /-|--+ | [RL]
|K G---< | | |
[REF] S \+|-------+-----+ |
| | | | | |
| | | [R3] [C1] |
| | | | | |
GND>----+-----------+-------+--------+-----+-->>--+


Use a little high-voltage FET to drive the big FET's gate. They're
cheap and it doesn't take much (damn near nothing) to drive them. Use
a micropower opamp and you can get its supply voltage from a resistor
and a low-current shunt reference tied to the 400V rail (or even just
a resistive divider) The Zener is to make sure the big MOSFET's gate
voltage never goes higher than it's supposed to, WRT to the source,
R2 R3 is the 40:1 divider, and C1 is to keep the thing from
oscillating.

It cannot oscillate no matter what value you use for C1.
Study it carefully and I'm sure you can see why.

---
Typical behavior for you. As the erroree, when you find what you
think is an error, instead of simply stating what you think it is that
makes it an error, you hold back and try to get some mileage out of it
by requiring a lot of work to be done by whom you consider to be the
errorer.


The post you quoted is one I canceled a couple of
minutes after hitting send. I mistakenly read your
upper MOSFET as a reversed P-channel device,
assuming, incorrectly, that you intended to produce
the 400V output first mentioned by the OP. As I
was reading your schematic, filling in the missing
polarity, it looked like a bistable latch. And if that
was what you had drawn, (or meant to draw), it
would have taken little time to spot it.

Bistable latch? More big technical words from the clueless lightweight
and poser? Looks like a common drain buffering his common source stage
to me, and anyone else who knows anything at all....

In this case, good catch, but... the larger C1 becomes, the greater
the output ripple becomes, until it starts to look like an
oscillation. The best C1 is no C1, according to bitethedust.asc which
you can find on abse and which you can run if you've downloaded
LTSPICE


I'm game. It's not showing up on my newserver
in alt.binaries.schematics.electronic . Can you
either email it or state what part values and
transistors you used? Or post, the .asc, which
is ASCII, so can be pasted into a post.

I presume your comments apply to my post of
12:50, where I asked about loop gain shifts
and dominant poles. Since you elect to not
answer that, I want to simulate your circuit
and see for myself.

Why should he answer your questions? You don't answer any questions put
to you.....Sounds like a free-loader looking for a free education to me.

Where did the output ripple come from? I can
see no source for it in your schematic other
than an oscillation. I'm about 95% confidant
that it will oscillate until C1 becomes huge.
The only question is where the limiting occurs.

"confidant"? This underlying implicit assumption you make about people
valuing your opinion is the height of mental illness- especially after
all the demonstration that you don't know your ass from a hole in the
ground.