Can I \"reset\" an AD9901?...

[server]

On Wed, 9 Mar 2022 21:51:40 -0000 (UTC), Mike Monett <spamme@not.com>
wrote:

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 08.03.22 um 21:19 schrieb Mike Monett:
Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 08.03.22 um 19:02 schrieb Mike Monett:

The AD9901 is a truly horrible phase detector. The concept starts with
a deep misunderstanding of the reason for deadband near the center of
the transfer curve.

No. The AD9901 is good. I had excellent results with it.


Deadband is not produced in the digital portion of the phase detector.
It is produced in the following analog section when the propagation
delay through one path is slower than the delay through the other
path.

What are you talking about?
There is no analog section in the AD9901.

I even have a compilable VHDL version of it that fits
into a tiny corner of a Xilinx Coolrunner II.


An example is shown in Jim Thompson\'s MC4044 phase/frequency detector.
The pullup path is a complicated discrete inverter, and the pulldown
path is a simple diode. The pullup path is much slower than the
pulldown path, and the detector produces no output for late samples
near the center of the transfer curve.

What has the Helgoland island to do with all of this?

This is shown in the LTspice file DEADBAND.ASC in the following link:

https://tinyurl.com/2p97vht8

The companion file, FASTDIOD.ASC shows the pullup path replaced by a
diode, the same as the pulldown path. The pullup and pulldown paths
are
both equal and very fast, and the phase detector output is now
continuous through zero.

You can duplicate this performance at low frequencies by using
ordinary
CMOS 74AC74 and 74AC00 chips. For higher frequencies, MECL ECLINPS
ic\'s
will work. There are also a number of commerial chips, but beware of
AD9901 clones. Stay away from any ones that feature XOR operation to
eliminate deadband. They have terrible ripple and drift.

I have the impression that you mix something with the CD4046 and its
ilk. That has the problem that the charge pumps deliver no
gain Kp when there is no phase error. That can be mostly healed
with a 1 Meg bleed resistor.

And even there, the 9046 has corrected that for good.

I would really like the 9046 if I could switch off its VCO.
I do not want an unneeded frequency on my board.

??? Do you understand LTspice?

Methinks yes, I do.

And generic Spice also from the inside. Back then(R) we had to
program all the interesting algorithms ourselves before we
were given the 2G6 sources. Later I ported V3 to
Interactive Unix on a 386.

Did you even notice that we were talking about AD9901 and
not about your MC4044?

Hint: They could not be more different.


Gerhard

My post is about the MC4044 and deadband. The AD9901 is an XOR phase
detector with horrible ripple and drift. It is also very slow. The MC9046
has the same deadband problem as the MC4044.

XOR pd\'s have low gain, volts per second. The virtue of the 9901 is
that it can run at 200 MHz, and that might avoid dividing down into a
slower phase detector.

Of course, you can run an ecl xor or a diode mixer at GHz\'s, but you
need to get into lock range, which the 9901 does for you.

We\'ve done dpflop phase detectors in PLLs at 155 MHz. The gain is
basically infinite. We run the loop super wideband to achieve lock,
then narrow down after we have lock, to get better phase noise.

One can also do dumb things in an fpga, like comparing counters, to
get into lock, then cut over to some high-gain phase detector.



--

I yam what I yam - Popeye

 

[Anthony William Sloman]

On Friday, March 11, 2022 at 2:50:33 PM UTC+11, jla...@highlandsniptechnology.com wrote:

On Wed, 9 Mar 2022 21:51:40 -0000 (UTC), Mike Monett <spa...@not.com
wrote:
Gerhard Hoffmann <dk...@arcor.de> wrote:

Am 08.03.22 um 21:19 schrieb Mike Monett:
Gerhard Hoffmann <dk...@arcor.de> wrote:

Am 08.03.22 um 19:02 schrieb Mike Monett:

The AD9901 is a truly horrible phase detector. The concept starts with
a deep misunderstanding of the reason for deadband near the center of
the transfer curve.

No. The AD9901 is good. I had excellent results with it.


Deadband is not produced in the digital portion of the phase detector.
It is produced in the following analog section when the propagation
delay through one path is slower than the delay through the other
path.

What are you talking about?
There is no analog section in the AD9901.

I even have a compilable VHDL version of it that fits
into a tiny corner of a Xilinx Coolrunner II.


An example is shown in Jim Thompson\'s MC4044 phase/frequency detector.
The pullup path is a complicated discrete inverter, and the pulldown
path is a simple diode. The pullup path is much slower than the
pulldown path, and the detector produces no output for late samples
near the center of the transfer curve.

What has the Helgoland island to do with all of this?

This is shown in the LTspice file DEADBAND.ASC in the following link:

https://tinyurl.com/2p97vht8

The companion file, FASTDIOD.ASC shows the pullup path replaced by a
diode, the same as the pulldown path. The pullup and pulldown paths
are
both equal and very fast, and the phase detector output is now
continuous through zero.

You can duplicate this performance at low frequencies by using
ordinary
CMOS 74AC74 and 74AC00 chips. For higher frequencies, MECL ECLINPS
ic\'s
will work. There are also a number of commerial chips, but beware of
AD9901 clones. Stay away from any ones that feature XOR operation to
eliminate deadband. They have terrible ripple and drift.

I have the impression that you mix something with the CD4046 and its
ilk. That has the problem that the charge pumps deliver no
gain Kp when there is no phase error. That can be mostly healed
with a 1 Meg bleed resistor.

And even there, the 9046 has corrected that for good.

I would really like the 9046 if I could switch off its VCO.
I do not want an unneeded frequency on my board.

??? Do you understand LTspice?

Methinks yes, I do.

And generic Spice also from the inside. Back then(R) we had to
program all the interesting algorithms ourselves before we
were given the 2G6 sources. Later I ported V3 to
Interactive Unix on a 386.

Did you even notice that we were talking about AD9901 and
not about your MC4044?

Hint: They could not be more different.

My post is about the MC4044 and deadband. The AD9901 is an XOR phase
detector with horrible ripple and drift. It is also very slow. The MC9046
has the same deadband problem as the MC4044.

XOR pd\'s have low gain, volts per second.

It\'s highly stable and utterly predictable. \"Low\" isn\'t an issue.

The virtue of the 9901 is that it can run at 200 MHz, and that might avoid dividing down into a slower phase detector.

Of course, you can run an ecl xor or a diode mixer at GHz\'s, but you need to get into lock range, which the 9901 does for you.

Bistable-based phase detectors make it easy to get to the lock range. They don\'t \"do it for you\" - you do have to know what they are doing before you can make them work for you.

> We\'ve done dpflop phase detectors in PLLs at 155 MHz. The gain is basically infinite.

If you haven\'t got a clue about what\'s going on. The output can be made to flip from high to low as you go through the frequency you are trying to lock to, but it can run into metastablity at that point. In that application it is kind of difficult to guarantee the setup and hold times the bistable needs to offer predictable performance.

> We run the loop super wideband to achieve lock, then narrow down after we have lock, to get better phase noise.

Or think they have.

> One can also do dumb things in an fpga, like comparing counters, to get into lock, then cut over to some high-gain phase detector.

Of course. People who don\'t really know what they are doing go in for all sorts of needless complications.

--
Bill Sloman, Sydney

 

[Phil Hobbs]

jlarkin@highlandsniptechnology.com wrote:

On Thu, 10 Mar 2022 12:55:25 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

If it were my measurement, I\'d certainly use the unbalanced path length
trick--that puts everything into time and frequency, provided that the
measurement is sufficiently fast compared with the thermal timescales.

1/2 cycle at 300 MHz is 1.7 ns, so 1 ps is 600 ppm of that delay. Takes
quite a temperature shift to make a dent in that.

Here\'s our flipflop tester:

https://www.dropbox.com/s/398g74u4xmutf3j/99S394A.pdf?dl=0




Nowhere near physicsy enough.


True. A real physicsy tunable delay line would eliminate the jitter of
the two comparators, and really resolve the jitter of the flop.

You don\'t need the delay to be tunable, though--you can put in some
integral number of cycles\' worth of extra path delay in one arm, and
just change the rep rate of the pulses. If the jitter in the clock is
too large for that to work, the clock probably has other problems. (If
the duty cycle is known to be stable enough, you can use half the delay.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[server]

On Fri, 11 Mar 2022 03:35:01 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 12:55:25 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

If it were my measurement, I\'d certainly use the unbalanced path length
trick--that puts everything into time and frequency, provided that the
measurement is sufficiently fast compared with the thermal timescales.

1/2 cycle at 300 MHz is 1.7 ns, so 1 ps is 600 ppm of that delay. Takes
quite a temperature shift to make a dent in that.

Here\'s our flipflop tester:

https://www.dropbox.com/s/398g74u4xmutf3j/99S394A.pdf?dl=0




Nowhere near physicsy enough.


True. A real physicsy tunable delay line would eliminate the jitter of
the two comparators, and really resolve the jitter of the flop.

You don\'t need the delay to be tunable, though--you can put in some
integral number of cycles\' worth of extra path delay in one arm, and
just change the rep rate of the pulses. If the jitter in the clock is
too large for that to work, the clock probably has other problems. (If
the duty cycle is known to be stable enough, you can use half the delay.)

Generating a programmable-frequency clock with provable fs jitter
would be another problem.

Differential delay programmed with varicaps or biased capacitors might
be good enough.

We could use the differential inputs of the flop itself as
comparators; just seesaw the diff DC offsets, like we did with the two
comparators.

Why didn\'t we do that?



--

I yam what I yam - Popeye

 

[Anthony William Sloman]

On Saturday, March 12, 2022 at 2:13:29 AM UTC+11, jla...@highlandsniptechnology.com wrote:

On Fri, 11 Mar 2022 03:35:01 -0500, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
jla...@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 12:55:25 -0500, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
jla...@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jla...@highlandsniptechnology.com:

<snip>

True. A real physicsy tunable delay line would eliminate the jitter of
the two comparators, and really resolve the jitter of the flop.

https://www.onsemi.com/pdf/datasheet/mc100ep195-d.pdf

https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf

They are electronically controllable delay lines. The 195 data sheet specifies about one psec of jitter and about 10psec of resolution.

The 196 throws in a continuously variable extra delay from 0 to 60psec , but the jitter is worse, at about 3psec.

The delays are temperature sensitive, and you\'d probably want to measure them frequently - when I wanted to use the 195 I certainly planned to.

--
Bill Sloman, Sydney

 

[Phil Hobbs]

jlarkin@highlandsniptechnology.com wrote:

On Fri, 11 Mar 2022 03:35:01 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 12:55:25 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

If it were my measurement, I\'d certainly use the unbalanced path length
trick--that puts everything into time and frequency, provided that the
measurement is sufficiently fast compared with the thermal timescales.

1/2 cycle at 300 MHz is 1.7 ns, so 1 ps is 600 ppm of that delay. Takes
quite a temperature shift to make a dent in that.

Here\'s our flipflop tester:

https://www.dropbox.com/s/398g74u4xmutf3j/99S394A.pdf?dl=0




Nowhere near physicsy enough.


True. A real physicsy tunable delay line would eliminate the jitter of
the two comparators, and really resolve the jitter of the flop.

You don\'t need the delay to be tunable, though--you can put in some
integral number of cycles\' worth of extra path delay in one arm, and
just change the rep rate of the pulses. If the jitter in the clock is
too large for that to work, the clock probably has other problems. (If
the duty cycle is known to be stable enough, you can use half the delay.)


Generating a programmable-frequency clock with provable fs jitter
would be another problem.

The delay discriminator thing is nearly totally insensitive to
low-frequency jitter, which is where most of it lives.

That\'s where the RF guys come in. A 300 MHz sinusoidal signal with 100
fs of jitter between adjacent pulses would have a phase uncertainty of

<dPhi> = 2 pi * 100 fs * 300 MHz = 0.0002 radian.

in the corresponding bandwidth (which we\'ll get to).

That\'s a total phase noise power of -74 dBc. The sensitive bandwidth
peaks at 150 MHz with a cosine squared characteristic, so its bandwidth
is effectively 150 MHz. If we can get to the Johnson noise limit with a
signal of 0 dBm, even in the full 150 MHz Nyquist interval, that\'s

CNR = -174.5 dBm/Hz + 10 log (150e6) = -92.0 dBc,

well within spec. With a decent sine wave source, it should be no
problem to do that with a filter of, say, 10 MHz bandwidth.

A power amp running into a Schottky diode clipper should square the
waveform up nicely, so a reasonably vanilla RF synthesizer should work
fine, I should think.

One could check that by building two of them, one having the delay in
the clock and the other in the data--cross-correlating the results would
be a reasonable measure of the clock\'s jitter contribution vs. the dflop\'s.

Anyway, that\'s one applied physicist\'s approach. Fun problem, for
sure--it sure isn\'t the sort of regime one would normally expect to be in!

Cheers

Phil Hobbs

Differential delay programmed with varicaps or biased capacitors might
be good enough.

We could use the differential inputs of the flop itself as
comparators; just seesaw the diff DC offsets, like we did with the two
comparators.

Why didn\'t we do that?

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

jlarkin@highlandsniptechnology.com wrote:

On Wed, 9 Mar 2022 21:51:40 -0000 (UTC), Mike Monett <spamme@not.com
wrote:

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 08.03.22 um 21:19 schrieb Mike Monett:
Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 08.03.22 um 19:02 schrieb Mike Monett:

The AD9901 is a truly horrible phase detector. The concept starts with
a deep misunderstanding of the reason for deadband near the center of
the transfer curve.

No. The AD9901 is good. I had excellent results with it.


Deadband is not produced in the digital portion of the phase detector.
It is produced in the following analog section when the propagation
delay through one path is slower than the delay through the other
path.

What are you talking about?
There is no analog section in the AD9901.

I even have a compilable VHDL version of it that fits
into a tiny corner of a Xilinx Coolrunner II.


An example is shown in Jim Thompson\'s MC4044 phase/frequency detector.
The pullup path is a complicated discrete inverter, and the pulldown
path is a simple diode. The pullup path is much slower than the
pulldown path, and the detector produces no output for late samples
near the center of the transfer curve.

What has the Helgoland island to do with all of this?

This is shown in the LTspice file DEADBAND.ASC in the following link:

https://tinyurl.com/2p97vht8

The companion file, FASTDIOD.ASC shows the pullup path replaced by a
diode, the same as the pulldown path. The pullup and pulldown paths
are
both equal and very fast, and the phase detector output is now
continuous through zero.

You can duplicate this performance at low frequencies by using
ordinary
CMOS 74AC74 and 74AC00 chips. For higher frequencies, MECL ECLINPS
ic\'s
will work. There are also a number of commerial chips, but beware of
AD9901 clones. Stay away from any ones that feature XOR operation to
eliminate deadband. They have terrible ripple and drift.

I have the impression that you mix something with the CD4046 and its
ilk. That has the problem that the charge pumps deliver no
gain Kp when there is no phase error. That can be mostly healed
with a 1 Meg bleed resistor.

And even there, the 9046 has corrected that for good.

I would really like the 9046 if I could switch off its VCO.
I do not want an unneeded frequency on my board.

??? Do you understand LTspice?

Methinks yes, I do.

And generic Spice also from the inside. Back then(R) we had to
program all the interesting algorithms ourselves before we
were given the 2G6 sources. Later I ported V3 to
Interactive Unix on a 386.

Did you even notice that we were talking about AD9901 and
not about your MC4044?

Hint: They could not be more different.


Gerhard

My post is about the MC4044 and deadband. The AD9901 is an XOR phase
detector with horrible ripple and drift. It is also very slow. The MC9046
has the same deadband problem as the MC4044.

XOR pd\'s have low gain, volts per second. The virtue of the 9901 is
that it can run at 200 MHz, and that might avoid dividing down into a
slower phase detector.

Of course, you can run an ecl xor or a diode mixer at GHz\'s, but you
need to get into lock range, which the 9901 does for you.

We\'ve done dpflop phase detectors in PLLs at 155 MHz. The gain is
basically infinite. We run the loop super wideband to achieve lock,
then narrow down after we have lock, to get better phase noise.

One can also do dumb things in an fpga, like comparing counters, to
get into lock, then cut over to some high-gain phase detector.

Of course, since the dflop and a 4046-style PFD both want to lock at
zero degrees, you could just sum the two and let the dflop keep the loop
in the centre of the deadband, where the PFD doesn\'t do anything.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[server]

On Fri, 11 Mar 2022 12:06:14 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Fri, 11 Mar 2022 03:35:01 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 12:55:25 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

If it were my measurement, I\'d certainly use the unbalanced path length
trick--that puts everything into time and frequency, provided that the
measurement is sufficiently fast compared with the thermal timescales.

1/2 cycle at 300 MHz is 1.7 ns, so 1 ps is 600 ppm of that delay. Takes
quite a temperature shift to make a dent in that.

Here\'s our flipflop tester:

https://www.dropbox.com/s/398g74u4xmutf3j/99S394A.pdf?dl=0




Nowhere near physicsy enough.


True. A real physicsy tunable delay line would eliminate the jitter of
the two comparators, and really resolve the jitter of the flop.

You don\'t need the delay to be tunable, though--you can put in some
integral number of cycles\' worth of extra path delay in one arm, and
just change the rep rate of the pulses. If the jitter in the clock is
too large for that to work, the clock probably has other problems. (If
the duty cycle is known to be stable enough, you can use half the delay.)


Generating a programmable-frequency clock with provable fs jitter
would be another problem.

The delay discriminator thing is nearly totally insensitive to
low-frequency jitter, which is where most of it lives.

That\'s where the RF guys come in. A 300 MHz sinusoidal signal with 100
fs of jitter between adjacent pulses would have a phase uncertainty of

dPhi> = 2 pi * 100 fs * 300 MHz = 0.0002 radian.

in the corresponding bandwidth (which we\'ll get to).

That\'s a total phase noise power of -74 dBc. The sensitive bandwidth
peaks at 150 MHz with a cosine squared characteristic, so its bandwidth
is effectively 150 MHz. If we can get to the Johnson noise limit with a
signal of 0 dBm, even in the full 150 MHz Nyquist interval, that\'s

CNR = -174.5 dBm/Hz + 10 log (150e6) = -92.0 dBc,

well within spec. With a decent sine wave source, it should be no
problem to do that with a filter of, say, 10 MHz bandwidth.

A power amp running into a Schottky diode clipper should square the
waveform up nicely, so a reasonably vanilla RF synthesizer should work
fine, I should think.

One could check that by building two of them, one having the delay in
the clock and the other in the data--cross-correlating the results would
be a reasonable measure of the clock\'s jitter contribution vs. the dflop\'s.

Anyway, that\'s one applied physicist\'s approach. Fun problem, for
sure--it sure isn\'t the sort of regime one would normally expect to be in!

Cheers

Phil Hobbs

OK, but I want more like 1 fs resolution and jitter to test that flop.


--

I yam what I yam - Popeye

 

[Phil Hobbs]

jlarkin@highlandsniptechnology.com wrote:

On Fri, 11 Mar 2022 12:06:14 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Fri, 11 Mar 2022 03:35:01 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 12:55:25 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

jlarkin@highlandsniptechnology.com wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

If it were my measurement, I\'d certainly use the unbalanced path length
trick--that puts everything into time and frequency, provided that the
measurement is sufficiently fast compared with the thermal timescales.

1/2 cycle at 300 MHz is 1.7 ns, so 1 ps is 600 ppm of that delay. Takes
quite a temperature shift to make a dent in that.

Here\'s our flipflop tester:

https://www.dropbox.com/s/398g74u4xmutf3j/99S394A.pdf?dl=0




Nowhere near physicsy enough.


True. A real physicsy tunable delay line would eliminate the jitter of
the two comparators, and really resolve the jitter of the flop.

You don\'t need the delay to be tunable, though--you can put in some
integral number of cycles\' worth of extra path delay in one arm, and
just change the rep rate of the pulses. If the jitter in the clock is
too large for that to work, the clock probably has other problems. (If
the duty cycle is known to be stable enough, you can use half the delay.)


Generating a programmable-frequency clock with provable fs jitter
would be another problem.

The delay discriminator thing is nearly totally insensitive to
low-frequency jitter, which is where most of it lives.

That\'s where the RF guys come in. A 300 MHz sinusoidal signal with 100
fs of jitter between adjacent pulses would have a phase uncertainty of

dPhi> = 2 pi * 100 fs * 300 MHz = 0.0002 radian.

in the corresponding bandwidth (which we\'ll get to).

That\'s a total phase noise power of -74 dBc. The sensitive bandwidth
peaks at 150 MHz with a cosine squared characteristic, so its bandwidth
is effectively 150 MHz. If we can get to the Johnson noise limit with a
signal of 0 dBm, even in the full 150 MHz Nyquist interval, that\'s

CNR = -174.5 dBm/Hz + 10 log (150e6) = -92.0 dBc,

well within spec. With a decent sine wave source, it should be no
problem to do that with a filter of, say, 10 MHz bandwidth.

A power amp running into a Schottky diode clipper should square the
waveform up nicely, so a reasonably vanilla RF synthesizer should work
fine, I should think.

One could check that by building two of them, one having the delay in
the clock and the other in the data--cross-correlating the results would
be a reasonable measure of the clock\'s jitter contribution vs. the dflop\'s.

Anyway, that\'s one applied physicist\'s approach. Fun problem, for
sure--it sure isn\'t the sort of regime one would normally expect to be in!


OK, but I want more like 1 fs resolution and jitter to test that flop.

The correlation measurement ought to do that. Even at 0 dBm, the filter
/ amp / clipper ought to get down to 12 fs or so--it\'s 18 dB quieter
than it needs to be.

With the filter placed after a power amp (maybe with a 3 dB pad between
filter and clipper), the noise floor will still be near the Johnson
noise but the signal amplitude will be much larger.

So starting with +24 dBm, filtering, and then clipping should reach 1 fs
RMS.

Maybe Gerhard or even Joerg will chime in with a sanity check of my
numbers, but I think they\'re reasonable, and the method is sure
convenient to use--the delay is self-calibrating, so the phase shift vs.
frequency is super well defined.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Chris Jones]

On 11/03/2022 11:59, Joe Gwinn wrote:

On Thu, 10 Mar 2022 13:06:03 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Joe Gwinn wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

In phased-array radar applications, the \"Teflon knee\" can be very
important, to the point that ordinary Teflon cables cannot be used.
The phase change per degree Kelvin (=centigrade) becomes very large
around 20 C, where there is a phase change between crystal types. I
thing that glass transition is a different beast.


I\'m pretty sure the 20 C thing is the glass transition. Interestingly,
teflon capacitors show virtually no effect whatsoever--the change in
epsilon cancels out the dimensional change. Propagation delay in cables
has a different functional dependence, so it doesn\'t cancel completely.

It\'s the transition between two crystalline phases, versus crystalline
to amorphous.

I gather that the glass transition temperature of Teflon (PTFE) is
126 C or so. It\'s the transition between two beta crystalline phases
that occur around 20 C. I have an article on this somewhere.


There is an Amorphous Teflon that has no Teflon knee:

.<https://www.teflon.com/en/products/resins/amorphous-fluoropolymer

This has a minimum glass transition temp of 160 C.


Joe Gwinn

I was wondering whether anyone bothers to ovenize teflon boards, for
example with some SMT power resistors and thermistors scattered between
the RF stuff or on the back side of the board. You could stabilise each
region of the board at say 50 C, so the phase shifts might stay put a
bit better (after a brief warm-up). I had thought that might be worth
doing also for semi-rigid cabling inside test equipment.

 

[server]

On Sun, 13 Mar 2022 22:06:13 +1100, Chris Jones
<lugnut808@spam.yahoo.com> wrote:

On 11/03/2022 11:59, Joe Gwinn wrote:
On Thu, 10 Mar 2022 13:06:03 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Joe Gwinn wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

In phased-array radar applications, the \"Teflon knee\" can be very
important, to the point that ordinary Teflon cables cannot be used.
The phase change per degree Kelvin (=centigrade) becomes very large
around 20 C, where there is a phase change between crystal types. I
thing that glass transition is a different beast.


I\'m pretty sure the 20 C thing is the glass transition. Interestingly,
teflon capacitors show virtually no effect whatsoever--the change in
epsilon cancels out the dimensional change. Propagation delay in cables
has a different functional dependence, so it doesn\'t cancel completely.

It\'s the transition between two crystalline phases, versus crystalline
to amorphous.

I gather that the glass transition temperature of Teflon (PTFE) is
126 C or so. It\'s the transition between two beta crystalline phases
that occur around 20 C. I have an article on this somewhere.


There is an Amorphous Teflon that has no Teflon knee:

.<https://www.teflon.com/en/products/resins/amorphous-fluoropolymer

This has a minimum glass transition temp of 160 C.


Joe Gwinn


I was wondering whether anyone bothers to ovenize teflon boards, for
example with some SMT power resistors and thermistors scattered between
the RF stuff or on the back side of the board. You could stabilise each
region of the board at say 50 C, so the phase shifts might stay put a
bit better (after a brief warm-up). I had thought that might be worth
doing also for semi-rigid cabling inside test equipment.

We\'ve done that, but on FR4. The intent was to stabilise the parts,
not so much the pcb dielectric constant.

https://www.dropbox.com/sh/8s2qbyh5emhvsda/AABG72Yx5sWCKNEvysMU_4Lba?dl=0

A few of those have manganin current shunts buried in the blocks.

The e/o modulator thing has SMA feedthrus and long coaxes inside the
oven brick to block heat (ie cold) flow through the cables.

The largish amounts of aluminum keep the boards isothermal. PCBs don\'t
conduct heat well, so would have hot spots without some help.



--

I yam what I yam - Popeye

 

[Joe Gwinn]

On Sun, 13 Mar 2022 22:06:13 +1100, Chris Jones
<lugnut808@spam.yahoo.com> wrote:

On 11/03/2022 11:59, Joe Gwinn wrote:
On Thu, 10 Mar 2022 13:06:03 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Joe Gwinn wrote:
On Thu, 10 Mar 2022 09:17:56 -0500, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Gerhard Hoffmann wrote:
Am 10.03.22 um 04:01 schrieb jlarkin@highlandsniptechnology.com:

I\'d expect that most materials have a dielectric constant that varies
with DC bias. Lithium niobate refractive index varies with bias, which
is how Mach-Zender things work.

It wouldn\'t surprise me if teflon Er changes with bias. That would be
easy to check.

It changes big time with temperature, just above room temp.
I remember a swearing colleage with a clima chamber and reels
of teflon coax. One of the sorry moments when you think you
remember the numbers instead of writing them down.

The glass fibers in a board reduce the effect, maybe?


Gerhard

The glass transition in Teflon mainly shows up in the mechanical
properties--the CTE goes up to over 2000 ppm/K. The effect on
transmission lines is much less, but still important.

In phased-array radar applications, the \"Teflon knee\" can be very
important, to the point that ordinary Teflon cables cannot be used.
The phase change per degree Kelvin (=centigrade) becomes very large
around 20 C, where there is a phase change between crystal types. I
thing that glass transition is a different beast.


I\'m pretty sure the 20 C thing is the glass transition. Interestingly,
teflon capacitors show virtually no effect whatsoever--the change in
epsilon cancels out the dimensional change. Propagation delay in cables
has a different functional dependence, so it doesn\'t cancel completely.

It\'s the transition between two crystalline phases, versus crystalline
to amorphous.

I gather that the glass transition temperature of Teflon (PTFE) is
126 C or so. It\'s the transition between two beta crystalline phases
that occur around 20 C. I have an article on this somewhere.


There is an Amorphous Teflon that has no Teflon knee:

.<https://www.teflon.com/en/products/resins/amorphous-fluoropolymer

This has a minimum glass transition temp of 160 C.


Joe Gwinn


I was wondering whether anyone bothers to ovenize teflon boards, for
example with some SMT power resistors and thermistors scattered between
the RF stuff or on the back side of the board. You could stabilise each
region of the board at say 50 C, so the phase shifts might stay put a
bit better (after a brief warm-up). I had thought that might be worth
doing also for semi-rigid cabling inside test equipment.

I\'m sure somebody has done this. Typical OCXO oven temperature is
like 80 C, well above the Teflon knee, so Teflon may be well enough
behaved up there.

Joe Gwinn

 

[Mike Monett]

jlarkin@highlandsniptechnology.com wrote:

On Wed, 9 Mar 2022 21:51:40 -0000 (UTC), Mike Monett <spamme@not.com
wrote:

[...]

My post is about the MC4044 and deadband. The AD9901 is an XOR phase
detector with horrible ripple and drift. It is also very slow. The MC9046
has the same deadband problem as the MC4044.

MC9046 was a typo copied from Gerhard. It should be MC4046.

> XOR pd\'s have low gain, volts per second.

The AD9901 is 0.2568V/Rad. Fig 7, Gain/Phase Plot, Page 6,

https://datasheet.octopart.com/AD9901KPZ-Analog-Devices-datasheet-19020.pdf

Doesn\'t matter. You can make it up in the amplifier. However, the penalty
with an XOR is the horrible ripple output when locked. The AD9901 swings
from VOH to VOL, or about 2V p-p. This creates unwanted spurs in the
oscillator output.

The virtue of the 9901 is
that it can run at 200 MHz, and that might avoid dividing down into a
slower phase detector.

The AD9901 is a very old chip. The datasheet is copyrighted 1999. It claims
to use ecl, but the output is collector driven instead of emitter follower.
This is one reason why the performance is so poor.

It already divides by two to drive the XOR. The linear region starts
compressing at 50 MHz. The device is almost useless at 200 MHz. See
Gain/Phase plot, above.

Of course, you can run an ecl xor or a diode mixer at GHz\'s, but you
need to get into lock range, which the 9901 does for you.

You can make your own phase/frequency detector with 100EP chips that may
run up to 1 GHz. The Hittite HMC series of 13 GHz chips can run faster.

The beauty of a dual d-flop phase/frequency detector is guaranteed
frequency lock when in range, and zero ripple output when locked.

We\'ve done dpflop phase detectors in PLLs at 155 MHz. The gain is
basically infinite. We run the loop super wideband to achieve lock,
then narrow down after we have lock, to get better phase noise.

If you are running a dual d-flop pfd, I don\'t see why you need to run at
high bandwidth to achieve lock. The dual-d already does that for you.

The problem with switching gain after lock is now the loop has to correct
the offsets caused by switching while in slow mode. This can take a long
time.

If you need to synthesize different frequencies, modern synthesizer chips
such as the TI LMX2820 go up to 22.6 GHz, include the VCO and integer-
boundary spur (IBS) removal, and offer very low PLL phase noise of -236
dBc/Hz:

https://www.ti.com/rf-microwave/rf-plls-synthesizers/products.html

ADI has a large variety of Fractional-N synthesizers that go up to 32 GHz:

https://www.analog.com/en/parametricsearch/11322#/

One can also do dumb things in an fpga, like comparing counters, to
get into lock, then cut over to some high-gain phase detector.

--
MRM

 

[Brent Locher]

On Tuesday, March 8, 2022 at 10:54:19 AM UTC-5, Jean-Pierre Coulon wrote:

I am using an Analog-devices AD9901 to lock the phase between two 1-MHz
signals.

The problem is that the state of the flip-flops is random at power on. Since
the phase between my 2 signals varies in a limited phase domain, sometimes my
output signal remains stuck at either limit of its range. Of course a 2*pi
phase variation would solve my problem. I cheat by disabling either input
signal for a brief moment.

Is there any way to force the statusses of both flip-flops on request?

Regards,

--
Jean-Pierre Coulon

That\'s nothing.....George Soros and BillGates can reset the whole world

 

[Mike Monett]

Mike Monett <spamme@not.com> wrote:

jlarkin@highlandsniptechnology.com wrote:

On Wed, 9 Mar 2022 21:51:40 -0000 (UTC), Mike Monett <spamme@not.com
wrote:

[...]

The problem with switching gain after lock is now the loop has to
correct the offsets caused by switching while in slow mode. This can
take a long time.

[...]

One can also do dumb things in an fpga, like comparing counters, to
get into lock, then cut over to some high-gain phase detector.

As above, when you switch from one mode to another, you have to correct for
unavoidable phase errors. These will usually occur in the slow mode, which
can take a long time and is difficult to define. I had this problem in my
Memorex patent of 1971, where I had to start a vco and phase detector in
phase with the incoming data in the minimum amount of time and with the
minimum phase error. See

https://patents.google.com/patent/US3810234A/

The approach shown in this patent not only solved the problem, but it also
led to another invention that changed the magnetic recording industry and
led to the incredible orders of magnitude increase in disk drive
performance since then. Many brilliant individuals have made significant
contributions to the technology, but they relied on this invention to tell
them the correct path.

The invention is described here:

https://tinyurl.com/2bmuz3n2




--
MRM