Bizzare behaviour from SG/UC3525

[Frithiof Andreas Jensen]

"Pooh Bear" <rabbitsfriendsandrelations@hotmail.com> wrote in message
news:42B8B135.8312B355@hotmail.com...

Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Layout is critical ... and decoupling ... I have had trouble squezing enough
decoupling onto those chips before. Seem to remember that there is an
applciation note for the layout of that chip and that is pretty much *it* -
it will *not* work in any other way.

Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !

You are picking up noise, and the 3525 output drivers are perfectly fast
enough to generate it themselves. The driver chip probably plenty fast also.
Maybe you slam the supply rails together.

Once you get the good scope out, you will see that one of the pins of the
3525 *will* have a tiny 6 ns spike on it, which will reset the latch in the
chip. causing more spikes to be generated.

 

[Pooh Bear]

Tony Williams wrote:

In article <42BA3BB7.D55ABE03@hotmail.com>,
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> wrote:

Tony Williams wrote:
Perhaps point your bifocals at the 3525 UVLO,

Yes, I looked at that area. I'm unhappy it's adequate so I'm
intending to add my own over-riding UVLO that monitors all the
rails.

I'd be tempted to link the Shutdown pin to 0V and
do external shutdown with a clamp across the slow
start capacitor. This would avoid uncontrolled
re-starts if the shutdown command glitched.

You just read my mind !

One 'jellybean' transistor should do nicely.

Perhaps use a MOSFET with pullup to 12V so that
any global undervoltage circuit has to generate
an active pulldown to keep the 3524 Enabled.

This is where it gets fun - trying to second guess how the part actually
works !

;-)

In the instance I mention however I had already asserted the
shutdown function on the 3525 before allowing the rails to decay
- i.e. OutA and B were both inactive. Then the IR2110 expired as
the volts dropped !

The SG3525 data sheet does not say what happens to
the (active) logic-low levels of the OUTs when it's
power supply goes below 8v.

I bet it doesn't !

You read my mind - *again* ! I've been 'sleeping on it' btw.

At some unknown low
supply voltage the OUTs might go to an open circuit.
Would it be prudent to have safety pull-down R's on
the IR2110 inputs?

I suspect we're heading towards a solution here.

Thanks, Graham

 

[Pooh Bear]

Fritz Schlunder wrote:

"Tony Williams" <tonyw@ledelec.demon.co.uk> wrote in message
news:4d7f6f4dcbtonyw@ledelec.demon.co.uk...

At some unknown low
supply voltage the OUTs might go to an open circuit.
Would it be prudent to have safety pull-down R's on
the IR2110 inputs?

This is a good point, however it appears the designer of the IR2110
envisioned this scenario and took care of it. Presumably the IR2110 inputs
have both schmitt triggers and internal pull downs.

They did it seems !

That's interesting. Makes a pleasant change !

Graham

 

[Pooh Bear]

Pooh Bear wrote:

Hi,

I mis-spelt Bizarre ! That's what warm temps do to you !

Apologies, Graham ;-)

 

[Fritz Schlunder]

"Pooh Bear" <rabbitsfriendsandrelations@hotmail.com> wrote in message
news:42B940A2.3014FE0F@hotmail.com...

It seemed to stop the 'jitter' on the trailing high side edge but then I
went and switched the damn thing off and the IR2110 went Fizzzz as the
rails decayed ! And it was the the *low* side driver that had gone bad !
It measured 2 ohms form Vs to out after this incident !

It usually takes quite a bit of power to make a component audibly fizzle.
While not totally inconceivable, a 14V bias supply (which was just turned
off before the failure, is that what you are suggesting?) isn't too likely
to be able to deliver this much juice. So that leaves the question, if it
didn't come from the IR2110 supply rail, where did the power come from?

Perhaps the power came from the main input capacitor(s) charged to what,
340V? The IR2110 is connected to this high voltage supply, so this isn't
totally inconceivable even if the IGBT gates don't get blasted.

After the failure, did you check to see if the bootstrap diode (which is
used by the IR2110 to charge the bootstrap capacitor Cboot) was still good?
What is the part number you are using for this bootstrap diode? If this
part failed it could conceivably cause the symptoms described. The
temptation when selecting this part would be to use a low voltage schottky
diode, however this would not be a good choice since the part must be able
to block the full high voltage supply voltage plus around 15V plus margin.
During turn off of the IR2110 Vcc supply it is conceivable this diode would
experience slightly higher voltage stress than during normal operation. If
improperly selected, this might help explain why it failed at power off.
This may not be your problem, but it is a theory at least.


What does your power stage look like? Do your half bridge IGBTs have
antiparallel diodes on them?

This is probably unrelated, but 14V is rather too low by conventional
standards for driving normal IGBTs. Normal IGBTs expect about 15V of gate
drive for good performance, and since the high side IGBT will only receive
at the most one diode drop less than the IR2110 bias supply voltage, this is
a bit lower than what is conventionally considered optimum.

 

[Rich Grise]

On Thu, 23 Jun 2005 05:45:30 +0100, Pooh Bear wrote:

Ol' Duffer wrote:

Going entirely from memory...
I thought the SG3525 was a push-pull flyback converter, but
you use terms like "high side driver" and "half bridge", which
make no sense in that context.

The 3525 is simply being used to generate the timing waveforms. The 3525
outputs drive an IR2110 half bridge arrangement.

I can't tell from your scattered verbal description what you are
trying to do, but it sounds fishy.

It's a configuration very similar to one used by one of the major
pro-audio amplifier companies in a mildly different incarnation which
has proven reliability. The differences are modest and I've added some
further protective features in fact.


Got a schematic?

Not that I can post right now sadly.

Well, I should know better than to look at data sheets in my delicate
condition *hic*, but you _did_ say that the low side went pfft? Where
does it get its Vcc? Plus, I don't trust black boxes in general. ;-)

Thanks,
Rich

 

[Fritz Schlunder]

"Pooh Bear" <rabbitsfriendsandrelations@hotmail.com> wrote in message
news:42BABB9C.F13B1BF6@hotmail.com...

As
for the OutA/OutB jitter/unequal pulse width problems (as well as the
human
hand near the design and it changes performance), this can probably be
explained by either your implementation of or your understanding of 3525
pins 1, 2, 8, 9, and 10 (for dual inline package).

1 and 2 are tied since we only need max duty cycle. 9 is therefore open -
we
don't use the error amp at all. 8 has the usual cap to gnd.

The datasheet doesn't seem tremendously clear, but pin 9 (compensation)
doesn't appear to have a tremendously strong driver. Although I doubt this
is causing any problems, it may be at least conceivable very powerful noise
could disrupt this signal. They show a 10nF capacitor hooked up to this pin
in their lab test fixture.

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

I doubt this is your problem, but you might try putting such a capacitor in
place just to verify this to be the case.

The more you write about it, the more suspect in my mind pin 10 becomes
however (shutdown).

What exactly do you have all hooked up to the shutdown pin and how?

As far as I saw, the shutdown pin simply discharges the soft start cap. I
*know*
it does this slowly since asserting shutdown briefly *doesn't* immediately
reset
the duty cycle to zero. This is a failure in someone else's implementation
of
this part that I'm aware of. I put a 555 mono there to stop that. It gets
a damn
good long shutdown signal from me.

Better go back to that datasheet I linked to above and re-read the text that
appears on page 6 again. When driven high the shutdown pin will instantly
turn off the output as well as set a latch that will keep the output off for
the remainder of the given oscillator cycle. This means the output won't
remain off for very long (as the output will turn back on again the very
next oscillator cycle) unless the shutdown pin stays high.

The shutdown pin does more than just this however. It also activates a
roughly 150uA current sink (extremely crude one if you study the block
diagram) which begins discharging the soft start capacitor. If the shutdown
pin doesn't stay high for very long, then the soft start capacitor voltage
will not appreciably change. In this case the pulses would resume normally
at full width the very next cycle of the main oscillator. On the other
hand, if the shutdown pin is asserted for long enough to significantly
discharge the soft start capacitor (through the roughly 150uA constant
current sink), then the device should exhibit soft start effects when the
shutdown signal is finally removed (actively driven to ground, the shutdown
pin should never be left floating).

As for your IR2110 fizzling... It seems to me that if the output IGBTs
haven't failed,

They do normally !

That isn't encouraging news. What does your output power stage look like?
In particular what is the arrangement of the secondary(s) of the main power
transformer? How is the output rectified? Do you use two inductors on the
output for smoothing, or does the output of the transformer directly try to
charge the output capacitors through the rectifiers? What is the output
capacitance? Input capacitance and input voltage?

Aside from these considerations... Current limiting? You are using it
right? Right??

Implemented my own way using a current sense R in the return path to the
Vbus
centre tap.

I've got an LM393 looking at + - volts across the current sense shunt and
sending a level shifted signal to a 555 mono that then asserts shutdown on
the
3525. I used a 555 since I saw in advance that shutdown on the 3525
wasn't fast
acting.

Been tested ( adjusted the sensitivity to play with it ) - works a treat.
It
does that perfect 'burp mode'.

If the output power stage doesn't use inductors (and maybe even if it does,
especially if the soft start feature doesn't function adequately), then the
restart will be extremely stressful, especially if the output capacitors are
large (which I assume they are). This can very easily lead to the
desruction of IGBTs with no clear cause or reason for failure. Presumably
the output capacitors store many joules of energy. If a capacitor is
charged from a voltage source (without inductance, or with a small amount of
inductance but in an uncontrolled fashion) the energy lost in the parasitic
resistance is equal to the energy stored in the capacitors after they are
fully charged. If the capacitors are allowed to charge rapidly and in an
uncontrolled fashion without inductance, the IGBTs represent the bulk of the
parasitic resistance and can therefore easily be destroyed. If the device
is operated in burp/hiccup mode then the uncontrolled rapid
charging/discharging/recharging stresses is all the worse. Device failure
(presumably thermal failure) can occur even when the package is physically
cool to the touch.

Without it you are liable to get some kind of STD

STD ? I rather think you don't mean sexually transmitted disease ! That
acronym
I'm not familiar with I regret.

It seems you know the acronym I was referring to.

 

[Fritz Schlunder]

"Pooh Bear" <rabbitsfriendsandrelations@hotmail.com> wrote in message
news:42BA3F22.AE034989@hotmail.com...

After others' comments I'm going to concentate on pin 10 - the shutdown
pin.
Despite the fact that the block diagram of the chip's internals shows no
obvious route for this to cause the effect,

I'm starting to see where some of this confusion might be coming from. The
datasheets aren't very good.

On Texas Instruments datasheet:

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

They show the block diagram on page one. In that block diagram they show
how the internal connection is made between the shutdown input and the PWM
latch as well as directly to the NOR output gates. When a high input
voltage is provided at the shutdown pin (IE: 5.1V of Vref) current flows in
through the internal resistor activating the internal "1.4V reference"
composed of two diode drops as well as the crude current sink made by the
NPN and 5k resistor. Evidently this 1.4V is enough to be registered as
logical highs by the PWM latch and NOR gates.

I notice now that on the figure on page seven labeled "Lab test fixture"
they don't depict the internal connection between shutdown and the PWM latch
or NOR gates. I can see how that might make it hard to see why it should
instantly (typically 200ns, max. 500ns) deactivate the output.

ST's datasheet shows a similar picture. The block diagram shows the
connection while the lab test fixture does not.

http://www.st.com/stonline/products/literature/ds/4286/sg3525.pdf

Shame on ST and TI and whoever else does this in their 3525 datasheet. TI's
text fixture is a little better than ST's datasheet in that they didn't
leave pin 10 floating under any conditions.

 

[Tony Williams]

In article <42BABB9C.F13B1BF6@hotmail.com>,
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> wrote:

1 and 2 are tied since we only need max duty cycle.

From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1.

9 is therefore open - we don't use the error amp at all.

An open-collector comparator into pin 9 (COMP input)
is SG's first choice for pulse_by_pulse limiting.

They say that the Shutdown input can be used for p_by_p
but only when there is no capacitor on the Slow-Start pin.

Radical rethink needed Graham.......

Shutdown pin to 0v.
Your p_by_p Overcurrent comparator into COMP input.
Any external UVLO discharges the Slow-Start cap.

8 has the usual cap to gnd.

What value is it, and could you please measure
at some time what voltage it finally rises to?

--
Tony Williams.

 

[Pooh Bear]

Tony Williams wrote:

In article <42BABB9C.F13B1BF6@hotmail.com>,
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> wrote:

1 and 2 are tied since we only need max duty cycle.

From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1.

Sorry. I didn't mean tied together !

One's tied low ( gnd ) and the other is tied to Vref.

9 is therefore open - we don't use the error amp at all.

An open-collector comparator into pin 9 (COMP input)
is SG's first choice for pulse_by_pulse limiting.

That could be potentially useful actually ! It's simply a no-connect on
my pcb at present.

And where did you get that nugget of info about the pulse limiting ?
That's very, very interesting.

They say that the Shutdown input can be used for p_by_p
but only when there is no capacitor on the Slow-Start pin.

Quite !

Radical rethink needed Graham.......

Interesting. That explains how Big Company A's implementation has a
failure mode I accidentally visited once. ;-)

Shutdown pin to 0v.
Your p_by_p Overcurrent comparator into COMP input.
Any external UVLO discharges the Slow-Start cap.

8 has the usual cap to gnd.

What value is it, and could you please measure
at some time what voltage it finally rises to?

It's 47uF currently since I deliberately wanted a very slow soft start
to look at it closely. It would be 4.7 or 10 uF in practice most likely.

And yes - I'll measure the volts there.

Cheers, Graham

 

[Pooh Bear]

Frithiof Andreas Jensen wrote:

"Pooh Bear" <rabbitsfriendsandrelations@hotmail.com> wrote in message
news:42B8B135.8312B355@hotmail.com...

Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Layout is critical ... and decoupling ... I have had trouble squezing enough
decoupling onto those chips before.

How much ( value, type ) would you typically use ? 0.1uF box film polyester type
here. An MLC type presents no probs to me but modern film types are pretty hot.

Seem to remember that there is an
applciation note for the layout of that chip and that is pretty much *it* -
it will *not* work in any other way.

Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !

You are picking up noise, and the 3525 output drivers are perfectly fast
enough to generate it themselves. The driver chip probably plenty fast also.
Maybe you slam the supply rails together.

Once you get the good scope out, you will see that one of the pins of the
3525 *will* have a tiny 6 ns spike on it, which will reset the latch in the
chip. causing more spikes to be generated.

That sounds suspiciously likely !

Graham

 

[Pooh Bear]

Fritz Schlunder wrote:

Better go back to that datasheet I linked to above and re-read the text that
appears on page 6 again. When driven high the shutdown pin will instantly
turn off the output as well as set a latch that will keep the output off for
the remainder of the given oscillator cycle. This means the output won't
remain off for very long (as the output will turn back on again the very
next oscillator cycle) unless the shutdown pin stays high.

Yes, I follow you.

I rather suspect a draughting error on the data sheet !

As you say, it's not especially clear.

The shutdown pin does more than just this however. It also activates a
roughly 150uA current sink (extremely crude one if you study the block
diagram) which begins discharging the soft start capacitor. If the shutdown
pin doesn't stay high for very long, then the soft start capacitor voltage
will not appreciably change.

Yes.

In this case the pulses would resume normally
at full width the very next cycle of the main oscillator.

Yes. I've seen this.

On the other
hand, if the shutdown pin is asserted for long enough to significantly
discharge the soft start capacitor (through the roughly 150uA constant
current sink), then the device should exhibit soft start effects when the
shutdown signal is finally removed

Indeed.

(actively driven to ground, the shutdown
pin should never be left floating).

Now look at the application circuit ! Tell me if pin 10 isn't effectively
'floating' !

This data sheet is just truly awful.

As for your IR2110 fizzling... It seems to me that if the output IGBTs
haven't failed,

They do normally !

That isn't encouraging news. What does your output power stage look like?

Just a plain vanilla half-bridge !

In particular what is the arrangement of the secondary(s) of the main power
transformer? How is the output rectified? Do you use two inductors on the
output for smoothing, or does the output of the transformer directly try to
charge the output capacitors through the rectifiers? What is the output
capacitance? Input capacitance and input voltage?

Haven't even got as far as rectifying anything yet, I'm just trying to get the
driver power waveforms right.

< snip >

If the output power stage doesn't use inductors (and maybe even if it does,
especially if the soft start feature doesn't function adequately), then the
restart will be extremely stressful, especially if the output capacitors are
large (which I assume they are).

There are small Ls on the secondary side. I plan to look very carefully at the
current waveforms. I'm not going to be caught out by that particular one.

This can very easily lead to the
desruction of IGBTs with no clear cause or reason for failure. Presumably
the output capacitors store many joules of energy. If a capacitor is
charged from a voltage source (without inductance, or with a small amount of
inductance but in an uncontrolled fashion) the energy lost in the parasitic
resistance is equal to the energy stored in the capacitors after they are
fully charged. If the capacitors are allowed to charge rapidly and in an
uncontrolled fashion without inductance, the IGBTs represent the bulk of the
parasitic resistance and can therefore easily be destroyed. If the device
is operated in burp/hiccup mode then the uncontrolled rapid
charging/discharging/recharging stresses is all the worse. Device failure
(presumably thermal failure) can occur even when the package is physically
cool to the touch.

Without it you are liable to get some kind of STD

STD ? I rather think you don't mean sexually transmitted disease ! That
acronym
I'm not familiar with I regret.

It seems you know the acronym I was referring to.

Lol !

Graham

 

[Pooh Bear]

Rich Grise wrote:

On Thu, 23 Jun 2005 05:45:30 +0100, Pooh Bear wrote:

Ol' Duffer wrote:

Going entirely from memory...
I thought the SG3525 was a push-pull flyback converter, but
you use terms like "high side driver" and "half bridge", which
make no sense in that context.

The 3525 is simply being used to generate the timing waveforms. The 3525
outputs drive an IR2110 half bridge arrangement.

I can't tell from your scattered verbal description what you are
trying to do, but it sounds fishy.

It's a configuration very similar to one used by one of the major
pro-audio amplifier companies in a mildly different incarnation which
has proven reliability. The differences are modest and I've added some
further protective features in fact.


Got a schematic?

Not that I can post right now sadly.


Well, I should know better than to look at data sheets in my delicate
condition *hic*, but you _did_ say that the low side went pfft? Where
does it get its Vcc? Plus, I don't trust black boxes in general. ;-)

Yes, the last failure was indeed the low side driver. ( rolls eyes in
puzzlement ) Its Vcc comes from the same supervisory supply as everything
else. Locally decoupled. Didn't take any IGBTs out that time though. Just
literally fizzzzed as I removed power and the rails sagged. The 3525 shouldn't
have been switching at the time - I'd already asserted shutdown via a switch.

Graham

 

[Pooh Bear]

Fritz Schlunder wrote:

"Pooh Bear" <rabbitsfriendsandrelations@hotmail.com> wrote in message
news:42B940A2.3014FE0F@hotmail.com...

It seemed to stop the 'jitter' on the trailing high side edge but then I
went and switched the damn thing off and the IR2110 went Fizzzz as the
rails decayed ! And it was the the *low* side driver that had gone bad !
It measured 2 ohms form Vs to out after this incident !

It usually takes quite a bit of power to make a component audibly fizzle.
While not totally inconceivable, a 14V bias supply (which was just turned
off before the failure, is that what you are suggesting?)

Yes. It would have decayed slowly too but faster than Vbus.

isn't too likely
to be able to deliver this much juice. So that leaves the question, if it
didn't come from the IR2110 supply rail, where did the power come from?

Perhaps the power came from the main input capacitor(s) charged to what,
340V?

Yeah - 320V.

The IR2110 is connected to this high voltage supply, so this isn't
totally inconceivable even if the IGBT gates don't get blasted.

After the failure, did you check to see if the bootstrap diode (which is
used by the IR2110 to charge the bootstrap capacitor Cboot) was still good?

Actually I didn't. Interesting point but it worked when I replaced the IR2110 so
I guess it's fine. A UF4006. Fast 1A 600V.

What is the part number you are using for this bootstrap diode?

See above. ;-)

If this
part failed it could conceivably cause the symptoms described. The
temptation when selecting this part would be to use a low voltage schottky
diode, however this would not be a good choice since the part must be able
to block the full high voltage supply voltage plus around 15V plus margin.

Quite.

During turn off of the IR2110 Vcc supply it is conceivable this diode would
experience slightly higher voltage stress than during normal operation. If
improperly selected, this might help explain why it failed at power off.
This may not be your problem, but it is a theory at least.

I'll check it's a 4006 and not a 4004. Even so, the 4004 ( 400V ) should be
fine.

What does your power stage look like? Do your half bridge IGBTs have
antiparallel diodes on them?

The ones I'm currently using don't have the 'body diodes' so I have some MUR460s
in parallel. Fast 600V 4A.

This is probably unrelated, but 14V is rather too low by conventional
standards for driving normal IGBTs. Normal IGBTs expect about 15V of gate
drive for good performance, and since the high side IGBT will only receive
at the most one diode drop less than the IR2110 bias supply voltage, this is
a bit lower than what is conventionally considered optimum.

Yes, I agree. I just 'bumped up' the volts slightly actually. I plan to use a
regulated supply ( flyback switcher ) to supply this rail in the final version.
Probably about 16 ~ 17 V.

Graham

 

[Tony Williams]

On 24 Jun, Tony Williams <tonyw@ledelec.demon.co.uk> wrote:

In article <42BABB9C.F13B1BF6@hotmail.com>,
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> wrote:

1 and 2 are tied since we only need max duty cycle.

From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1. /|\
|

Misread. Should be N.Inv IN________|

The max CMV of the error amp is 5.2V, so it could
be possible to connect pin 2 to the 5.1V ref and
pin 2 at least 0.7V below it. This should put
the output of the error amp at 3.8Vdc.

--
Tony Williams.

 

[Tony Williams]

In article <d9f5bb$atm$1@domitilla.aioe.org>,
Fritz Schlunder <me@privacy.net> wrote:

I'm starting to see where some of this confusion might be coming
from. The datasheets aren't very good.

I'm beginning to wonder whether a more modern chip
(LT1105?) might be easier/cheaper..............

--
Tony Williams.

 

[Pooh Bear]

Fritz Schlunder wrote:

I'm starting to see where some of this confusion might be coming from. The
datasheets aren't very good.

Tell me about it !

On Texas Instruments datasheet:

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

< snip >

I notice now that on the figure on page seven labeled "Lab test fixture"
they don't depict the internal connection between shutdown and the PWM latch
or NOR gates. I can see how that might make it hard to see why it should
instantly (typically 200ns, max. 500ns) deactivate the output.

Good isn't it ! ;-)

ST's datasheet shows a similar picture. The block diagram shows the
connection while the lab test fixture does not.

http://www.st.com/stonline/products/literature/ds/4286/sg3525.pdf

Shame on ST and TI and whoever else does this in their 3525 datasheet. TI's
text fixture is a little better than ST's datasheet in that they didn't
leave pin 10 floating under any conditions.

Oh yes. You're right ! I'd previously taken the 2 data sheets to be effectively
clones. That's an intruiging difference. Could explain a few things !


Many thanks, Graham

 

[Tony Williams]

In article <42BBD0FB.71763B3D@hotmail.com>,
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> wrote:

Tony Williams wrote:
An open-collector comparator into pin 9 (COMP input)
is SG's first choice for pulse_by_pulse limiting.

That could be potentially useful actually ! It's simply a
no-connect on my pcb at present.
And where did you get that nugget of info about the pulse
limiting ? That's very, very interesting.

Off a 1989 Silicon General data sheet, 6th page,
labelled Shutdown Options. Just above the test
fixture circuit.... which also leaves pin 10 open
when running.

Just to be sure. Pull COMP to 0v to do a shutdown
via the PWM stage and R-S flipflop.

What value is it, and could you please measure
at some time what voltage it finally rises to?

It's 47uF currently since I deliberately wanted a very slow soft
start to look at it closely. It would be 4.7 or 10 uF in practice
most likely.

Resistor needed in series with the pulldown Tr then.

And yes - I'll measure the volts there.

Thanks. Best guess atm would be up near the 5v1 Vref.

BTW: It's only a 60uA pulldown current. If I assume
47uF, and a required pulldown from 4V to 0.5V,
then that would mean that the Shutdown pin has to
be held high for 2.7 seconds before a full (safe)
soft re-start can happen.

--
Tony Williams.

 

[Pooh Bear]

Tony Williams wrote:

On 24 Jun, Tony Williams <tonyw@ledelec.demon.co.uk> wrote:
In article <42BABB9C.F13B1BF6@hotmail.com>,
Pooh Bear <rabbitsfriendsandrelations@hotmail.com> wrote:

1 and 2 are tied since we only need max duty cycle.

From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1. /|\
|
Misread. Should be N.Inv IN________|

The max CMV of the error amp is 5.2V, so it could
be possible to connect pin 2 to the 5.1V ref and
pin 2 at least 0.7V below it. This should put
the output of the error amp at 3.8Vdc.

That is indeed what I've done.

Graham

 

[Pooh Bear]

Tony Williams wrote:

In article <d9f5bb$atm$1@domitilla.aioe.org>,
Fritz Schlunder <me@privacy.net> wrote:

I'm starting to see where some of this confusion might be coming
from. The datasheets aren't very good.

I'm beginning to wonder whether a more modern chip
(LT1105?) might be easier/cheaper..............

Me too ! The 3525 was chosen simply since almost *every* similar design
I've seen uses it.

LT are a bit pricey normally though. I'm wondering about On-Semi.

Incidentally, another company ( Italian FWIW ) makes their 'audio smps'
with one of IR's 'electronic ballast driver' chips. Basically any old
cheap way to make the necessary waveforms !

Graham