Attainable PWM accuracy?

[George Herold]

On Friday, October 11, 2019 at 5:17:16 PM UTC-4, Tim Williams wrote:

Do you need so many bits if you just add the 50V offset and DAC the
remaining 5ish volts? Well, not too many less, about 3, but still. That's
closer to 12 than 16, or maybe even 8 than 12. Use a 2.5 or 5V PWM ref and
add the offset with op-amps.

Yeah I was thinking about something like that.
or a digipot from 55 to 50 volts. (I've never used a digipot and
have no idea if you can float 'em. Probably more trouble than it's
worth.)

As a silly idea, run two MPPC's, one with a constant light input and
servo the voltage for the desired gain. (or switch one between
'standard' light source and signal.)

George H.

As long as you have an op-amp or two in circuit, you might as well use a
3-pole active filter to sharpen up the cutoff. Lower ripple for a given
cutoff, faster response...

(Maybe a 4-pole, with the added pole being a small RC out front to help
arrest the sharp edges, to cover up the active filter not handling edges so
neatly.)

Do you have a DAC sensing the MPPC bias, or multiplication factor, and
servoing on that? That may be justificationi for it.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

"Phil Hobbs" <pcdhSpamMeSenseless@electrooptical.net> wrote in message
news:cuqdnROW7KJFJT3AnZ2dnUU7-XHNnZ2d@supernews.com...
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a bias
supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from ~0
to 2E6 between 52 and 55 volts' bias. (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)

Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often. Accordingly, I'm tentatively planning
to use a 12 to 16-bit PWM with good filtering. It'll obviously have to be
buffered with a tinylogic gate running from a stiff reference supply, to
prevent voltage sags inside the LPC845 MCU from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to get
the output ripple on the MPPC supply down to a millivolt or so, so that's
3 RC sections with 33 dB attenuation each, i.e. corner frequencies of 2.5
Hz to 40 Hz (TCs of 4 to 60 ms). Not horrible--100k*0.68uF at 16 bits,
40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought of
that might limit the accuracy? How good can you make a PWM, anyway?

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[George Herold]

On Saturday, October 12, 2019 at 12:40:35 PM UTC-4, George Herold wrote:

On Friday, October 11, 2019 at 5:17:16 PM UTC-4, Tim Williams wrote:
Do you need so many bits if you just add the 50V offset and DAC the
remaining 5ish volts? Well, not too many less, about 3, but still. That's
closer to 12 than 16, or maybe even 8 than 12. Use a 2.5 or 5V PWM ref and
add the offset with op-amps.

Yeah I was thinking about something like that.
or a digipot from 55 to 50 volts. (I've never used a digipot and
have no idea if you can float 'em. Probably more trouble than it's
worth.)

Put the digipot on the bottom?
GH

As a silly idea, run two MPPC's, one with a constant light input and
servo the voltage for the desired gain. (or switch one between
'standard' light source and signal.)

George H.

As long as you have an op-amp or two in circuit, you might as well use a
3-pole active filter to sharpen up the cutoff. Lower ripple for a given
cutoff, faster response...

(Maybe a 4-pole, with the added pole being a small RC out front to help
arrest the sharp edges, to cover up the active filter not handling edges so
neatly.)

Do you have a DAC sensing the MPPC bias, or multiplication factor, and
servoing on that? That may be justificationi for it.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

"Phil Hobbs" <pcdhSpamMeSenseless@electrooptical.net> wrote in message
news:cuqdnROW7KJFJT3AnZ2dnUU7-XHNnZ2d@supernews.com...
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a bias
supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from ~0
to 2E6 between 52 and 55 volts' bias. (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)

Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often. Accordingly, I'm tentatively planning
to use a 12 to 16-bit PWM with good filtering. It'll obviously have to be
buffered with a tinylogic gate running from a stiff reference supply, to
prevent voltage sags inside the LPC845 MCU from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to get
the output ripple on the MPPC supply down to a millivolt or so, so that's
3 RC sections with 33 dB attenuation each, i.e. corner frequencies of 2.5
Hz to 40 Hz (TCs of 4 to 60 ms). Not horrible--100k*0.68uF at 16 bits,
40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought of
that might limit the accuracy? How good can you make a PWM, anyway?

Thanks

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

Winfield Hill <winfieldhill@yahoo.com> wrote:

Phil Hobbs wrote...

The '845 can run its PWM clocks ... I'd need about
100 dB of filtering to get the output ripple ...

You could take a look at the x-Chapters section,
4x.25 Ripple Reduction in PWM, where we explore
Stephen Woodward's clever ripple-reduction trick.

https://www.dropbox.com/s/ir4k21hibg7a8z0/4x.25_PWM_ripple.pdf?dl=1

I concluded for my project, that a 16-bit DAC
made more sense, in terms of minimum PCB space.

Cute circuit. However, this is clearly second order
filter so fair comparizon would be with cascade of
two RC steps. If I did my calculations correctly
for R1 = R2 and C1 = C2 and assuming infinite impedance
load Woodward's circuit has the same response as
two step RC cascade. RC cascade does not need extra
inverter, so it is not clear for me if there are
reasons to prefer Woodward's circuit.

In some sense optimal tradeoff between filtering ripple
and response time is given by Gaussian filter. Multistep
RC cascade give good approximation to Gaussian, so in
general it is not clear if more fancy (than RC cascade)
filtering has advantages for PWM. Phil plans to use three
stage RC cascade which already should be pretty good.

--
Waldek Hebisch

 

[Joseph Gwinn]

On Oct 11, 2019, Phil Hobbs wrote
(in article<cuqdnROW7KJFJT3AnZ2dnUU7-XHNnZ2d@supernews.com&gt:

Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).



MPPCs are extremely voltage sensitive--the gain of this one goes from ~0
to 2E6 between 52 and 55 volts' bias. (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)

Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often. Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering. It'll obviously
have to be buffered with a tinylogic gate running from a stiff reference
supply, to prevent voltage sags inside the LPC845 MCU from spoiling the
accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms). Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought of
that might limit the accuracy? How good can you make a PWM, anyway?

I´m not sure I follow what you are doing, but on hearing all the stuff
about delta-sigma conversion, it occurs to me that one can improve rejection
of power supply ripple by using an explicit charge-pump circuit in a
delta-sigma DAC.

Joe Gwinn

 

[Robert Baer]

Phil Hobbs wrote:

Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from ~0
to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll obviously
have to be buffered with a tinylogic gate running from a stiff reference
supply, to prevent voltage sags inside the LPC845 MCU from spoiling the
accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought of
that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs

Use switched filtering?

 

[bitrex]

On 10/12/19 7:17 AM, Piglet wrote:

On 11/10/2019 20:00, Winfield Hill wrote:
Phil Hobbs wrote...

The '845 can run its PWM clocks ... I'd need about
100 dB of filtering to get the output ripple ...

 You could take a look at the x-Chapters section,
 4x.25 Ripple Reduction in PWM, where we explore
 Stephen Woodward's clever ripple-reduction trick.

https://www.dropbox.com/s/ir4k21hibg7a8z0/4x.25_PWM_ripple.pdf?dl=1

 I concluded for my project, that a 16-bit DAC
 made more sense, in terms of minimum PCB space.



Here's an earlier incarnation of Woodward's idea:

https://www.dropbox.com/s/997fixfek6afwga/woodward_dac_precision_ifd.pdf?raw=1


piglet

Nice $5 power supply for a single white LED in there too, lol

 

[Phil Hobbs]

On 2019-10-13 01:06, Robert Baer wrote:

Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs

   Use switched filtering?

One approach to the PWM ripple problem is to use a S/H to sample the
filter output at the beginning of the PWM cycle. The subtle problem is
that even if the higher harmonics of the PWM frequency have died away
adequately, the phase of the fundamental ripple component depends on the
PWM code, which hurts the linearity.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

On 2019-10-12 13:04, George Herold wrote:

On Saturday, October 12, 2019 at 12:40:35 PM UTC-4, George Herold wrote:
On Friday, October 11, 2019 at 5:17:16 PM UTC-4, Tim Williams wrote:
Do you need so many bits if you just add the 50V offset and DAC the
remaining 5ish volts? Well, not too many less, about 3, but still. That's
closer to 12 than 16, or maybe even 8 than 12. Use a 2.5 or 5V PWM ref and
add the offset with op-amps.

Yeah I was thinking about something like that.
or a digipot from 55 to 50 volts. (I've never used a digipot and
have no idea if you can float 'em. Probably more trouble than it's
worth.)
Put the digipot on the bottom?
GH

As a silly idea, run two MPPC's, one with a constant light input and
servo the voltage for the desired gain. (or switch one between
'standard' light source and signal.)

That sort of thing is sometimes done with ordinary APDs, but in this
instance we're down in the guts of a SEM chamber with lots of other
things going on. We have to worry about running into other detectors,
and of course all SEMs of my acquaintance have video cameras inside,
which require light sources....

Digital pots are generally pretty crappy--unless you go for the
expensive ones that use metal resistors, the end-to-end resistance
tolerance is typically 30%, with a poor tempco. Thus you have to use
them ratiometrically and can't easily put a resistor in series to reduce
the adjustment range.

Floating them at some weird voltage is perfectly possible but requires a
fair number of additional parts. (One of our products has a
set-and-forget laser current limit using a nonvolatile dpot that gets
programmed at test time using a laptop--the dpot hangs off a +14V rail,
but the laptop is floating, so neither it nor the dpot notices. If we
were in mass production, it would need something like a Bus Pirate and a
USB isolator.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

On 2019-10-11 20:38, Lasse Langwadt Christensen wrote:

lørdag den 12. oktober 2019 kl. 02.20.29 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 15:34:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 12. oktober 2019 kl. 00.11.46 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 14:15:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

fredag den 11. oktober 2019 kl. 22.52.50 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 16:17:51 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 15:54, Andy Bennet wrote:
On 11/10/2019 18:16, Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs


Rather than PWM, have a look at pulse density modulation which will ease
the filtering requirement. Not sure if this is do-able in software, but
I have used FPGA implementations of this with great success.

Sort of a delta-sigma thing? You can put an M-bit delta-sigma extension
on an N-bit PWM pretty easily using a timer interrupt. I don't think
we could get the required accuracy bit-banging something like that.

Cheers

Phil Hobbs

You can also delta-sigma the LSB of a PWM to effectively add more
bits. That basically interpolates between two PWM levels.

I think that may have filtering advantages. I don't know if a uP can
reasonably do that; we did it in an FPGA.

I guess you could even PWM the LSB of a PWM.

AND a fast and a slow PWM?

You could certainly analog sum two PWMs, maybe before the filter. They
could run at a much higher frequency than a single PWM of the same
resolution.

but then you get the issue of how well analog matched the two outputs are



in hardware there's also the trick of inverting some or all of the bits
in the counter

Sorry, that's too hard to think about.

by inverting I meant reversing the bit order

i.e. 50% output becomes
hi-lo-hi-lo-hi-lo-hi-lo instead of hi-hi-hi-hi-lo-lo-lo-lo


That's even harder.

nah, swapping bits just means the counter counts in a different order

but amount of numbers larger/smaller than the set point is still
the same

i.e. it doesn't matter if you count to 1 to 256 in a random order, half
of the numbers are bigger than 128

We'd have to bitbang that, for one thing, and for another there would be
different numbers of transitions per cycle, which would hurt the
linearity on account of the slew artifacts.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Andy Bennet]

On 13/10/2019 08:19, Phil Hobbs wrote:

On 2019-10-13 01:06, Robert Baer wrote:
Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an
output frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of
filtering to get the output ripple on the MPPC supply down to a
millivolt or so, so that's 3 RC sections with 33 dB attenuation each,
i.e. corner frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs

    Use switched filtering?

One approach to the PWM ripple problem is to use a S/H to sample the
filter output at the beginning of the PWM cycle.  The subtle problem is
that even if the higher harmonics of the PWM frequency have died away
adequately, the phase of the fundamental ripple component depends on the
PWM code, which hurts the linearity.

Cheers

Phil Hobbs

Um then have a PWM gated constant current source feeding a capacitor,
followed by a s/h.

 

[Phil Hobbs]

On 2019-10-13 04:09, Andy Bennet wrote:

On 13/10/2019 08:19, Phil Hobbs wrote:
On 2019-10-13 01:06, Robert Baer wrote:
Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm
doing a bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one
goes from ~0 to 2E6 between 52 and 55 volts' bias. (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)



Sooo, there's a bit of pressure to keep the bias very stable,
but it doesn't have to change very often. Accordingly, I'm
tentatively planning to use a 12 to 16-bit PWM with good
filtering. It'll obviously have to be buffered with a
tinylogic gate running from a stiff reference supply, to
prevent voltage sags inside the LPC845 MCU from spoiling the
accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an
output frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB
of filtering to get the output ripple on the MPPC supply down
to a millivolt or so, so that's 3 RC sections with 33 dB
attenuation each, i.e. corner frequencies of 2.5 Hz to 40 Hz
(TCs of 4 to 60 ms). Not horrible--100k*0.68uF at 16 bits, 40k
and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't
thought of that might limit the accuracy? How good can you
make a PWM, anyway?

Thanks

Phil Hobbs

Use switched filtering?

One approach to the PWM ripple problem is to use a S/H to sample
the filter output at the beginning of the PWM cycle. The subtle
problem is that even if the higher harmonics of the PWM frequency
have died away adequately, the phase of the fundamental ripple
component depends on the PWM code, which hurts the linearity.

Cheers

Phil Hobbs


Um then have a PWM gated constant current source feeding a capacitor,
followed by a s/h.

Yeah, there are lots of ways to do it if you don't mind a bunch of extra
parts.

What I wound up with is a vanilla 12-bit PWM driving a SN74LVC1G04
inverter that's powered by a REF5030 3-ppm/K reference, followed by a
three-stage RC filter.

It's sort of funny, putting in a $5 reference just to drive a five-cent
logic inverter, but that's where error budgets take you sometimes.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Chris Jones]

On 12/10/2019 08:17, Tim Williams wrote:

Do you need so many bits if you just add the 50V offset and DAC the
remaining 5ish volts?  Well, not too many less, about 3, but still.
That's closer to 12 than 16, or maybe even 8 than 12.  Use a 2.5 or 5V
PWM ref and add the offset with op-amps.
Makes a lot of sense.

As long as you have an op-amp or two in circuit, you might as well use a
3-pole active filter to sharpen up the cutoff.  Lower ripple for a given
cutoff, faster response...

(Maybe a 4-pole, with the added pole being a small RC out front to help
arrest the sharp edges, to cover up the active filter not handling edges
so neatly.)

It might be worth exploring ways to put a zero in the filter response,
at the PWM frequency. Maybe need less poles then.

 

[Winfield Hill]

Phil Hobbs wrote...

Lasse Langwadt Christensen wrote:
lørdag den 12. oktober 2019 kl. 02.20.29 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 15:34:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 12. oktober 2019 kl. 00.11.46 UTC+2 skrev John Larkin:

You could certainly analog sum two PWMs, maybe before the filter.
They could run at a much higher frequency than a single PWM of
the same resolution.

We'd have to bitbang that, for one thing, and for another there
would be different numbers of transitions per cycle, which would
hurt the linearity on account of the slew artifacts.

Not sure what you were answering to, but the main and vernier
PWMs could both be setup for a constant number of transitions.


--
Thanks,
- Win

 

[Lasse Langwadt Christense]

søndag den 13. oktober 2019 kl. 11.14.27 UTC+2 skrev Phil Hobbs:

On 2019-10-13 04:09, Andy Bennet wrote:
On 13/10/2019 08:19, Phil Hobbs wrote:
On 2019-10-13 01:06, Robert Baer wrote:
Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm
doing a bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one
goes from ~0 to 2E6 between 52 and 55 volts' bias. (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)



Sooo, there's a bit of pressure to keep the bias very stable,
but it doesn't have to change very often. Accordingly, I'm
tentatively planning to use a 12 to 16-bit PWM with good
filtering. It'll obviously have to be buffered with a
tinylogic gate running from a stiff reference supply, to
prevent voltage sags inside the LPC845 MCU from spoiling the
accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an
output frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB
of filtering to get the output ripple on the MPPC supply down
to a millivolt or so, so that's 3 RC sections with 33 dB
attenuation each, i.e. corner frequencies of 2.5 Hz to 40 Hz
(TCs of 4 to 60 ms). Not horrible--100k*0.68uF at 16 bits, 40k
and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't
thought of that might limit the accuracy? How good can you
make a PWM, anyway?

Thanks

Phil Hobbs

Use switched filtering?

One approach to the PWM ripple problem is to use a S/H to sample
the filter output at the beginning of the PWM cycle. The subtle
problem is that even if the higher harmonics of the PWM frequency
have died away adequately, the phase of the fundamental ripple
component depends on the PWM code, which hurts the linearity.

Cheers

Phil Hobbs


Um then have a PWM gated constant current source feeding a capacitor,
followed by a s/h.


Yeah, there are lots of ways to do it if you don't mind a bunch of extra
parts.

What I wound up with is a vanilla 12-bit PWM driving a SN74LVC1G04
inverter that's powered by a REF5030 3-ppm/K reference, followed by a
three-stage RC filter.

It's sort of funny, putting in a $5 reference just to drive a five-cent
logic inverter, but that's where error budgets take you sometimes.

isn't something like this http://www.ti.com/product/DAC80501
close to doing it all in one ic?

 

On Sun, 13 Oct 2019 03:01:35 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 20:38, Lasse Langwadt Christensen wrote:
lřrdag den 12. oktober 2019 kl. 02.20.29 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 15:34:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lřrdag den 12. oktober 2019 kl. 00.11.46 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 14:15:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

fredag den 11. oktober 2019 kl. 22.52.50 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 16:17:51 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 15:54, Andy Bennet wrote:
On 11/10/2019 18:16, Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs


Rather than PWM, have a look at pulse density modulation which will ease
the filtering requirement. Not sure if this is do-able in software, but
I have used FPGA implementations of this with great success.

Sort of a delta-sigma thing? You can put an M-bit delta-sigma extension
on an N-bit PWM pretty easily using a timer interrupt. I don't think
we could get the required accuracy bit-banging something like that.

Cheers

Phil Hobbs

You can also delta-sigma the LSB of a PWM to effectively add more
bits. That basically interpolates between two PWM levels.

I think that may have filtering advantages. I don't know if a uP can
reasonably do that; we did it in an FPGA.

I guess you could even PWM the LSB of a PWM.

AND a fast and a slow PWM?

You could certainly analog sum two PWMs, maybe before the filter. They
could run at a much higher frequency than a single PWM of the same
resolution.

but then you get the issue of how well analog matched the two outputs are



in hardware there's also the trick of inverting some or all of the bits
in the counter

Sorry, that's too hard to think about.

by inverting I meant reversing the bit order

i.e. 50% output becomes
hi-lo-hi-lo-hi-lo-hi-lo instead of hi-hi-hi-hi-lo-lo-lo-lo


That's even harder.

nah, swapping bits just means the counter counts in a different order

but amount of numbers larger/smaller than the set point is still
the same

i.e. it doesn't matter if you count to 1 to 256 in a random order, half
of the numbers are bigger than 128


We'd have to bitbang that, for one thing, and for another there would be
different numbers of transitions per cycle, which would hurt the
linearity on account of the slew artifacts.

Cheers

Phil Hobbs

What I've never understood about delta-sigma is that you can make 25%
duty cycle from

01001000 or from 00011000

but one has twice as many transitions as the other. Rise and fall
edges aren't perfect, so they won't make the same average voltage.
Since the codes vary in density with the output voltage, that would
seem to cause a linearity error and some excess noise. PWM should be
better because it always has two transitions per cycle.

I guess the people who design ICs can apply tricks to fix that to 20
or 24 bit level. I suspect that, using discrete parts, we can't.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

On Sun, 13 Oct 2019 05:14:20 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-13 04:09, Andy Bennet wrote:
On 13/10/2019 08:19, Phil Hobbs wrote:
On 2019-10-13 01:06, Robert Baer wrote:
Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm
doing a bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one
goes from ~0 to 2E6 between 52 and 55 volts' bias. (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)



Sooo, there's a bit of pressure to keep the bias very stable,
but it doesn't have to change very often. Accordingly, I'm
tentatively planning to use a 12 to 16-bit PWM with good
filtering. It'll obviously have to be buffered with a
tinylogic gate running from a stiff reference supply, to
prevent voltage sags inside the LPC845 MCU from spoiling the
accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an
output frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB
of filtering to get the output ripple on the MPPC supply down
to a millivolt or so, so that's 3 RC sections with 33 dB
attenuation each, i.e. corner frequencies of 2.5 Hz to 40 Hz
(TCs of 4 to 60 ms). Not horrible--100k*0.68uF at 16 bits, 40k
and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't
thought of that might limit the accuracy? How good can you
make a PWM, anyway?

Thanks

Phil Hobbs

Use switched filtering?

One approach to the PWM ripple problem is to use a S/H to sample
the filter output at the beginning of the PWM cycle. The subtle
problem is that even if the higher harmonics of the PWM frequency
have died away adequately, the phase of the fundamental ripple
component depends on the PWM code, which hurts the linearity.

Cheers

Phil Hobbs


Um then have a PWM gated constant current source feeding a capacitor,
followed by a s/h.


Yeah, there are lots of ways to do it if you don't mind a bunch of extra
parts.

What I wound up with is a vanilla 12-bit PWM driving a SN74LVC1G04
inverter that's powered by a REF5030 3-ppm/K reference, followed by a
three-stage RC filter.

It's sort of funny, putting in a $5 reference just to drive a five-cent
logic inverter, but that's where error budgets take you sometimes.

Cheers

Phil Hobbs

Looks like the best sub-10 PPM ref that we use is ADR363B, 3v 9 PPM,
$1.89.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Lasse Langwadt Christense]

søndag den 13. oktober 2019 kl. 16.51.08 UTC+2 skrev jla...@highlandsniptechnology.com:

On Sun, 13 Oct 2019 03:01:35 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 20:38, Lasse Langwadt Christensen wrote:
lørdag den 12. oktober 2019 kl. 02.20.29 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 15:34:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 12. oktober 2019 kl. 00.11.46 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 14:15:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

fredag den 11. oktober 2019 kl. 22.52.50 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 16:17:51 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 15:54, Andy Bennet wrote:
On 11/10/2019 18:16, Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs


Rather than PWM, have a look at pulse density modulation which will ease
the filtering requirement. Not sure if this is do-able in software, but
I have used FPGA implementations of this with great success.

Sort of a delta-sigma thing? You can put an M-bit delta-sigma extension
on an N-bit PWM pretty easily using a timer interrupt. I don't think
we could get the required accuracy bit-banging something like that.

Cheers

Phil Hobbs

You can also delta-sigma the LSB of a PWM to effectively add more
bits. That basically interpolates between two PWM levels.

I think that may have filtering advantages. I don't know if a uP can
reasonably do that; we did it in an FPGA.

I guess you could even PWM the LSB of a PWM.

AND a fast and a slow PWM?

You could certainly analog sum two PWMs, maybe before the filter. They
could run at a much higher frequency than a single PWM of the same
resolution.

but then you get the issue of how well analog matched the two outputs are



in hardware there's also the trick of inverting some or all of the bits
in the counter

Sorry, that's too hard to think about.

by inverting I meant reversing the bit order

i.e. 50% output becomes
hi-lo-hi-lo-hi-lo-hi-lo instead of hi-hi-hi-hi-lo-lo-lo-lo


That's even harder.

nah, swapping bits just means the counter counts in a different order

but amount of numbers larger/smaller than the set point is still
the same

i.e. it doesn't matter if you count to 1 to 256 in a random order, half
of the numbers are bigger than 128


We'd have to bitbang that, for one thing, and for another there would be
different numbers of transitions per cycle, which would hurt the
linearity on account of the slew artifacts.

Cheers

Phil Hobbs

What I've never understood about delta-sigma is that you can make 25%
duty cycle from

01001000 or from 00011000

but one has twice as many transitions as the other. Rise and fall
edges aren't perfect, so they won't make the same average voltage.
Since the codes vary in density with the output voltage, that would
seem to cause a linearity error and some excess noise. PWM should be
better because it always has two transitions per cycle.

a delta-sigma modulator usually have (should have) a much more
"chaotic" output so it averages out

constant input to a delta-sigma modulator is "dangerous" because it can
get stuck in some periodic pattern that result in tones in the pass band

and it is really hard to analyse/predict because it is not a linear system

 

On Sun, 13 Oct 2019 08:53:12 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

sřndag den 13. oktober 2019 kl. 16.51.08 UTC+2 skrev jla...@highlandsniptechnology.com:
On Sun, 13 Oct 2019 03:01:35 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 20:38, Lasse Langwadt Christensen wrote:
lřrdag den 12. oktober 2019 kl. 02.20.29 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 15:34:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lřrdag den 12. oktober 2019 kl. 00.11.46 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 14:15:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

fredag den 11. oktober 2019 kl. 22.52.50 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 16:17:51 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 15:54, Andy Bennet wrote:
On 11/10/2019 18:16, Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs


Rather than PWM, have a look at pulse density modulation which will ease
the filtering requirement. Not sure if this is do-able in software, but
I have used FPGA implementations of this with great success.

Sort of a delta-sigma thing? You can put an M-bit delta-sigma extension
on an N-bit PWM pretty easily using a timer interrupt. I don't think
we could get the required accuracy bit-banging something like that.

Cheers

Phil Hobbs

You can also delta-sigma the LSB of a PWM to effectively add more
bits. That basically interpolates between two PWM levels.

I think that may have filtering advantages. I don't know if a uP can
reasonably do that; we did it in an FPGA.

I guess you could even PWM the LSB of a PWM.

AND a fast and a slow PWM?

You could certainly analog sum two PWMs, maybe before the filter. They
could run at a much higher frequency than a single PWM of the same
resolution.

but then you get the issue of how well analog matched the two outputs are



in hardware there's also the trick of inverting some or all of the bits
in the counter

Sorry, that's too hard to think about.

by inverting I meant reversing the bit order

i.e. 50% output becomes
hi-lo-hi-lo-hi-lo-hi-lo instead of hi-hi-hi-hi-lo-lo-lo-lo


That's even harder.

nah, swapping bits just means the counter counts in a different order

but amount of numbers larger/smaller than the set point is still
the same

i.e. it doesn't matter if you count to 1 to 256 in a random order, half
of the numbers are bigger than 128


We'd have to bitbang that, for one thing, and for another there would be
different numbers of transitions per cycle, which would hurt the
linearity on account of the slew artifacts.

Cheers

Phil Hobbs

What I've never understood about delta-sigma is that you can make 25%
duty cycle from

01001000 or from 00011000

but one has twice as many transitions as the other. Rise and fall
edges aren't perfect, so they won't make the same average voltage.
Since the codes vary in density with the output voltage, that would
seem to cause a linearity error and some excess noise. PWM should be
better because it always has two transitions per cycle.

a delta-sigma modulator usually have (should have) a much more
"chaotic" output so it averages out

But a mid duty cycle has more adjacent bits without transitions than a
low or high duty cycle, hence the linearity error. I think.

constant input to a delta-sigma modulator is "dangerous" because it can
get stuck in some periodic pattern that result in tones in the pass band

1st order delta-sigma can have periodic patterns. Presumably
higher-order modulators don't.

and it is really hard to analyse/predict because it is not a linear system

I posted an LT Spice 2nd order delta-sigma modulator here a while
back, but I didn't analyze it much beyond some FFTs.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Rick C]

On Sunday, October 13, 2019 at 10:51:08 AM UTC-4, jla...@highlandsniptechnology.com wrote:

On Sun, 13 Oct 2019 03:01:35 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 20:38, Lasse Langwadt Christensen wrote:
lørdag den 12. oktober 2019 kl. 02.20.29 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 15:34:20 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

lørdag den 12. oktober 2019 kl. 00.11.46 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 14:15:06 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

fredag den 11. oktober 2019 kl. 22.52.50 UTC+2 skrev John Larkin:
On Fri, 11 Oct 2019 16:17:51 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2019-10-11 15:54, Andy Bennet wrote:
On 11/10/2019 18:16, Phil Hobbs wrote:
Hi, all,

As part of the aforementioned cathodolumiescence system, I'm doing a
bias supply for multipixel photon counters (MPPCs).

MPPCs are extremely voltage sensitive--the gain of this one goes from
~0 to 2E6 between 52 and 55 volts' bias.  (See
https://www.hamamatsu.com/resources/pdf/ssd/e03_handbook_si_apd_mppc.pdf>.)


Sooo, there's a bit of pressure to keep the bias very stable, but it
doesn't have to change very often.  Accordingly, I'm tentatively
planning to use a 12 to 16-bit PWM with good filtering.  It'll
obviously have to be buffered with a tinylogic gate running from a
stiff reference supply, to prevent voltage sags inside the LPC845 MCU
from spoiling the accuracy.

The '845 can run its PWM clocks at 7.5 MHz, so that would be an output
frequency of 114 Hz to 1.8 kHz. I'd need about 100 dB of filtering to
get the output ripple on the MPPC supply down to a millivolt or so, so
that's 3 RC sections with 33 dB attenuation each, i.e. corner
frequencies of 2.5 Hz to 40 Hz (TCs of 4 to 60 ms).  Not
horrible--100k*0.68uF at 16 bits, 40k and 0.1 uF at 12 bits.

Anything else besides buffering and filtering that I haven't thought
of that might limit the accuracy?  How good can you make a PWM, anyway?

Thanks

Phil Hobbs


Rather than PWM, have a look at pulse density modulation which will ease
the filtering requirement. Not sure if this is do-able in software, but
I have used FPGA implementations of this with great success.

Sort of a delta-sigma thing? You can put an M-bit delta-sigma extension
on an N-bit PWM pretty easily using a timer interrupt. I don't think
we could get the required accuracy bit-banging something like that.

Cheers

Phil Hobbs

You can also delta-sigma the LSB of a PWM to effectively add more
bits. That basically interpolates between two PWM levels.

I think that may have filtering advantages. I don't know if a uP can
reasonably do that; we did it in an FPGA.

I guess you could even PWM the LSB of a PWM.

AND a fast and a slow PWM?

You could certainly analog sum two PWMs, maybe before the filter. They
could run at a much higher frequency than a single PWM of the same
resolution.

but then you get the issue of how well analog matched the two outputs are



in hardware there's also the trick of inverting some or all of the bits
in the counter

Sorry, that's too hard to think about.

by inverting I meant reversing the bit order

i.e. 50% output becomes
hi-lo-hi-lo-hi-lo-hi-lo instead of hi-hi-hi-hi-lo-lo-lo-lo


That's even harder.

nah, swapping bits just means the counter counts in a different order

but amount of numbers larger/smaller than the set point is still
the same

i.e. it doesn't matter if you count to 1 to 256 in a random order, half
of the numbers are bigger than 128


We'd have to bitbang that, for one thing, and for another there would be
different numbers of transitions per cycle, which would hurt the
linearity on account of the slew artifacts.

Cheers

Phil Hobbs

What I've never understood about delta-sigma is that you can make 25%
duty cycle from

01001000 or from 00011000

but one has twice as many transitions as the other. Rise and fall
edges aren't perfect, so they won't make the same average voltage.
Since the codes vary in density with the output voltage, that would
seem to cause a linearity error and some excess noise. PWM should be
better because it always has two transitions per cycle.

I guess the people who design ICs can apply tricks to fix that to 20
or 24 bit level. I suspect that, using discrete parts, we can't.

Direct PWM may give better linearity perhaps, but worse noise because of the frequency distribution.

--

Rick C.

--- Get 2,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

 

[bitrex]

On 10/13/19 8:11 AM, Chris Jones wrote:

On 12/10/2019 08:17, Tim Williams wrote:
Do you need so many bits if you just add the 50V offset and DAC the
remaining 5ish volts?  Well, not too many less, about 3, but still.
That's closer to 12 than 16, or maybe even 8 than 12.  Use a 2.5 or 5V
PWM ref and add the offset with op-amps.
Makes a lot of sense.

As long as you have an op-amp or two in circuit, you might as well use
a 3-pole active filter to sharpen up the cutoff.  Lower ripple for a
given cutoff, faster response...

(Maybe a 4-pole, with the added pole being a small RC out front to
help arrest the sharp edges, to cover up the active filter not
handling edges so neatly.)
It might be worth exploring ways to put a zero in the filter response,
at the PWM frequency. Maybe need less poles then.

TI Filterpro includes an active low-pass filter prototype that's a
Bessel/Butterworth hybrid (I call it the "Bustleworth") that I like a
lot for filtering PWM, which provides a good compromise between the
linear phase response of the Bessel and the steeper slope of the
Butterworth.