4000 CMOS latch up

[Tony Williams]

In article <c9cejr023nm@drn.newsguy.com>,
Winfield Hill <Winfield_member@newsguy.com> wrote:

The SCR latchup we have been referring to always acts across
the rail-to-rail power-supply pins, not in the output to one
rail, etc.
[snip]

By shoot-through I mean't that both the high side
and low side of the o/p stage would be conducting
uncontrollably. This would draw current through
the supply pins and would be difficult to distinguish
from latchup (especially post mortem).

In the case of my LMC660CN opamp debacle (where
both o/p FETs would be On at the same time) I
suspected that one of the output FETs was initially
damaged or destroyed by whatever the event was and
this in turn took out the other output FET. Note the
40mA output current capability of an LMC660.

--
Tony Williams.

 

[legg]

On Sat, 29 May 2004 13:28:16 -0700, Jim Thompson
<thegreatone@example.com> wrote:

If you want to contemplate "tricky", I've designed some chips whose
outputs go tri-state when they are un-powered ;-)

You mean the output pin is high-z to it's unpowered positive supply
pin, providing the potential of supply isolation?

Perhaps more easily achievable when the powered 'on' performance of
the output in question is tri-state or 'open collector' construction
to begin with.

RL

 

[Fred Bloggs]

Winfield Hill wrote:

Tony Williams wrote...

Winfield Hill <Winfield_member@newsguy.com> wrote:


Let me tell a story. At my company, Sea Data, I designed and
made very complex battery-powered oceanographic instruments,
which were deployed on the deep-sea ocean bottom, operating
dozens of sensors and storing data for a year. One of the
sensors was a Benthos flash camera that could store hundreds of
shots, taken when my instrument determined that a bottom
photograph was needed. But unfortunately when I asked for a
flash, a CMOS IC in my instrument would trip into SCR latchup,
shorting the supply regulator, ending the experiment.

I had a similar experience with early LMC660CN opamps.
The output stage was very tender if naughties happened
to it..... instant shorted power supplies, overheating,
and DIL cases actually cracked.

There was no time to investigate (just shifted to TL084),
but my antennae suggested an induced shoot-through in
the output stage (rather than an SCR latchup).


The SCR latchup we have been referring to always acts across
the rail-to-rail power-supply pins, not in the output to one
rail, etc. If the "source" fault current comes from a high
voltage spike, as in the case of the flash, series resistors
may be little help. A pair of Schottky diodes to the supply
rails may not be enough given that their voltage drop can be
excessive at high currents; four diodes and a resistor may
be required. Sheesh! For short spikes, as mine were, adding
a capacitor can help. I don't remember my solution 25 years
ago, but I probably rewired the system to eliminate the fault
current spike, moving the camera's optocoupler to the endcap.

You must have had 100's pf of coupling between that HV line and the CMOS
output- and the diodes will not help if the output is H and you induce a
negative C x dV/dt that simultaneously yanks the CMOS pull-up low and
forward biases substrate to output- this may take only a few 10's mA, or
vice versa. Any attempt to shunt the high frequency current on the line
would probably run you into CMOS input minimum slew rate requirements at
the destination. That flash drive is not so critical that you could have
lifted the GND return off chassis- used twisted HV wire src/ret and put
a woven GND sleeve over it- usually a simple capacitance meter
measurement of a layout like that will alert you with a fairly large
static reading- just assume it's all going where it shouldn't then ask
yourself if this might be require some intervention. Also- the latchup
was just your more obvious fault- no telling how close you were coming
to glitching something else into the wrong state or mis-operation.

 

[Fred Bloggs]

Tony Williams wrote:

In article <c9cejr023nm@drn.newsguy.com>,
Winfield Hill <Winfield_member@newsguy.com> wrote:



The SCR latchup we have been referring to always acts across
the rail-to-rail power-supply pins, not in the output to one
rail, etc.

[snip]

By shoot-through I mean't that both the high side
and low side of the o/p stage would be conducting
uncontrollably. This would draw current through
the supply pins and would be difficult to distinguish
from latchup (especially post mortem).

In the case of my LMC660CN opamp debacle (where
both o/p FETs would be On at the same time) I
suspected that one of the output FETs was initially
damaged or destroyed by whatever the event was and
this in turn took out the other output FET. Note the
40mA output current capability of an LMC660.

Where were those outputs going?

 

[Fred Bloggs]

Jim Thompson wrote:

On Sat, 29 May 2004 13:19:54 -0700, John Larkin
jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:


On Sat, 29 May 2004 11:41:58 -0700, Jim Thompson
thegreatone@example.com> wrote:


On Sat, 29 May 2004 18:29:38 GMT, Spehro Pefhany
speffSNIP@interlogDOTyou.knowwhat> wrote:


On Sat, 29 May 2004 10:27:24 -0700, the renowned John Larkin
jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:


On Sat, 29 May 2004 07:41:57 -0700, Jim Thompson
thegreatone@example.com> wrote:


On 29 May 2004 05:23:32 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson

So the datasheet would say CAUTION: NEVER ALLOW PROTECTIVE DIODES TO
BE FORWARD BIASED

If the customers would just do that, they wouldn't be needed at all.
;-)

Best regards,
Spehro Pefhany

Tsk! Tsk! Tsk! Spehro, Now you're sounding like Win. Do you think
the diodes are there to clamp your signals? No! They are there for
ESD protection.

...Jim Thompson


Specifically, for *power off* ESD protection. Power on, they were MTBF
limiters.


John


If you want to contemplate "tricky", I've designed some chips whose
outputs go tri-state when they are un-powered ;-)

...Jim Thompson

Some "hot swap" stuff?...Hmmmm. Well everyone has had to handle dealing
with live inputs driving an unpowered dual power supply op amp- this
will cause a certain chip fault when you do try to bring the opamp power
supply up.

 

[Winfield Hill]

Tony Williams wrote...

Winfield Hill wrote:

The SCR latchup we have been referring to always acts across
the rail-to-rail power-supply pins, not in the output to one
rail, etc. [snip]

By shoot-through I mean't that both the high side and low side
of the o/p stage would be conducting uncontrollably. This
would draw current through the supply pins and would be
difficult to distinguish from latchup (especially post mortem).

SCR latchup is high-supply to low-spply, you're distinguishing
whether the output devices continue to place a big role after
latchup begins? I assume they would. During latchup the
supply voltage is crowbarred down to 1.2V, so who can say?

In the case of my LMC660CN opamp debacle (where both o/p
FETs would be On at the same time) I suspected that one
of the output FETs was initially damaged or destroyed by
whatever the event was and this in turn took out the other
output FET. Note the 40mA output current capability of
an LMC660.

In my experience the CMOS logic chips recovered and were still
functional after latchup (but of course I replaced them anyway).
I suppose they're simply more rugged than an LMC660, or perhaps
my supply had a lower current limit than yours?

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Jan Panteltje]

On a sunny day (30 May 2004 09:30:23 -0700) it happened Winfield Hill
<Winfield_member@newsguy.com> wrote in <c9d26v01ava@drn.newsguy.com>:

Tony Williams wrote...

Winfield Hill wrote:

The SCR latchup we have been referring to always acts across
the rail-to-rail power-supply pins, not in the output to one
rail, etc. [snip]

By shoot-through I mean't that both the high side and low side
of the o/p stage would be conducting uncontrollably. This
would draw current through the supply pins and would be
difficult to distinguish from latchup (especially post mortem).

SCR latchup is high-supply to low-spply, you're distinguishing
whether the output devices continue to place a big role after
latchup begins? I assume they would. During latchup the
supply voltage is crowbarred down to 1.2V, so who can say?

In the case of my LMC660CN opamp debacle (where both o/p
FETs would be On at the same time) I suspected that one
of the output FETs was initially damaged or destroyed by
whatever the event was and this in turn took out the other
output FET. Note the 40mA output current capability of
an LMC660.

In my experience the CMOS logic chips recovered and were still
functional after latchup (but of course I replaced them anyway).
I suppose they're simply more rugged than an LMC660, or perhaps
my supply had a lower current limit than yours?

Thanks,
- Win
In one design, long long time ago, when IBM PC had just been born,

I used a resisistor (100 Ohm or more do not remember) in series
with the supply of the chip, decoupled with a tantalum cap, so, if
the thing would latchup, the voltage would drop, and the current
would drop beneath the SCR hold value, and it would auto recover.
This would also prevent overheating of the chip...
You can only do that if it does not need to source any real current.
JP

 

[Winfield Hill]

Jan Panteltje wrote...

In one design, long long time ago, when IBM PC had just been born,
I used a resisistor (100 Ohm or more do not remember) in series
with the supply of the chip, decoupled with a tantalum cap, so, if
the thing would latchup, the voltage would drop, and the current
would drop beneath the SCR hold value, and it would auto recover.
This would also prevent overheating of the chip...
You can only do that if it does not need to source any real current.

That's an interesting idea. What was the latchup SCR's minimum
holding current?

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Tony Williams]

In article <40BA06D4.2030505@nospam.com>,
Fred Bloggs <nospam@nospam.com> wrote:

Where were those outputs going?

Supposedly only to chart recorders, but the customer
possessed a technician who liked to take the lid off
things and have a poke about inside. Adjusting trimpots
to 'improve the performance' was one of his 'skills',
and there were two channels of optical-input logarithmic
amplifiers in there for him to play with. ((

So I suspect he was doing something that took out the
LMC660CN opamps. All such problems disappeared when
I switched opamps..... probably I think now to a 324.
It ruined the log performance at the lower end, but
they didn't notice, and I stopped having to do a 120
mile round trip every time.

--
Tony Williams.

 

[Jan Panteltje]

On a sunny day (30 May 2004 17:26:40 -0700) it happened Winfield Hill
<Winfield_member@newsguy.com> wrote in <c9du400vrj@drn.newsguy.com>:

Jan Panteltje wrote...

In one design, long long time ago, when IBM PC had just been born,
I used a resisistor (100 Ohm or more do not remember) in series
with the supply of the chip, decoupled with a tantalum cap, so, if
the thing would latchup, the voltage would drop, and the current
would drop beneath the SCR hold value, and it would auto recover.
This would also prevent overheating of the chip...
You can only do that if it does not need to source any real current.

That's an interesting idea. What was the latchup SCR's minimum
holding current?

Thanks,
- Win
Don't remember, 20 years ago.. but few mA, perhaps 10?

You could test this with this method quite easily (non destructive), if
you still have some 4000 series gates, would be interesting to know.
JP

 

[Terry Given]

"Tony Williams" <tonyw@ledelec.demon.co.uk> wrote in message
news:4cb7a86e71tonyw@ledelec.demon.co.uk...

In article <40BA06D4.2030505@nospam.com>,
Fred Bloggs <nospam@nospam.com> wrote:

Where were those outputs going?

Supposedly only to chart recorders, but the customer
possessed a technician who liked to take the lid off
things and have a poke about inside. Adjusting trimpots
to 'improve the performance' was one of his 'skills',
and there were two channels of optical-input logarithmic
amplifiers in there for him to play with. ((

So I suspect he was doing something that took out the
LMC660CN opamps. All such problems disappeared when
I switched opamps..... probably I think now to a 324.
It ruined the log performance at the lower end, but
they didn't notice, and I stopped having to do a 120
mile round trip every time.

Tony Williams.

Customers can be a real pain in the arse. A favourite trick of people buying
AC motor controllers was to swap the input (which had inrush limiting prior
to the rectifier) with the output (whose diodes look just like a rectifier,
with no inrush limiting). Apply power, and it doesnt go. Inrush current
toasts IGBT diodes. discover problem, re-wire input & output to the right
places. Turn on - now have nice inrush control, all looks good. start the
motor and BOOM - those diodes were important after all. Return to
manufacturer demanding replacement for "DOA" drive. Service department
suspects this, customer denies it. R&D engineers dismantle IGBT module,
finding 1-3 dead diodes (which pretty much never happens, even when IGBTs
pass away) and 1-2 dead IGBTs. Customer foots the bill.

I did a failure review on a ups once, at DGs request. The battery charger
flyback was toast, the output rectifier was shorted, and a big piece of its
(live at Vbat) heatsink was gone. say what? Close examination of the unit
showed 2 splat marks on the edge of the enclosures flat metal lid. One which
lined up with the heatsink (which was in the middle of the box) and one with
a splat mark on the edge of the enclosure (which was at 0V wrt battery). The
customer had the lid off, and rested it (on edge) across the unit, touching
the live heatsink to the edge of the case, some 300mm away. They paid for
that fix, AND my time. apparently arses were kicked...

Cheers
Terry

 

[Terry Given]

"Jan Panteltje" <panteltje@yahoo.com> wrote in message
news:b7527dd42913d31412a7b2e7fc6ef231@news.teranews.com...

On a sunny day (30 May 2004 17:26:40 -0700) it happened Winfield Hill
Winfield_member@newsguy.com> wrote in <c9du400vrj@drn.newsguy.com>:

Jan Panteltje wrote...

In one design, long long time ago, when IBM PC had just been born,
I used a resisistor (100 Ohm or more do not remember) in series
with the supply of the chip, decoupled with a tantalum cap, so, if
the thing would latchup, the voltage would drop, and the current
would drop beneath the SCR hold value, and it would auto recover.
This would also prevent overheating of the chip...
You can only do that if it does not need to source any real current.

That's an interesting idea. What was the latchup SCR's minimum
holding current?

Thanks,
- Win
Don't remember, 20 years ago.. but few mA, perhaps 10?
You could test this with this method quite easily (non destructive), if
you still have some 4000 series gates, would be interesting to know.
JP

?! few volts/few mA = kohms.

Cheers
Terry

 

[Jan Panteltje]

On a sunny day (Tue, 1 Jun 2004 13:29:32 +1200) it happened "Terry Given"
<the_domes@xtra.co.nz> wrote in <3%Quc.12778$XI4.447808@news.xtra.co.nz>:

"Jan Panteltje" <panteltje@yahoo.com> wrote in message
news:b7527dd42913d31412a7b2e7fc6ef231@news.teranews.com...
On a sunny day (30 May 2004 17:26:40 -0700) it happened Winfield Hill
Winfield_member@newsguy.com> wrote in <c9du400vrj@drn.newsguy.com>:

Jan Panteltje wrote...

In one design, long long time ago, when IBM PC had just been born,
I used a resisistor (100 Ohm or more do not remember) in series
with the supply of the chip, decoupled with a tantalum cap, so, if
the thing would latchup, the voltage would drop, and the current
would drop beneath the SCR hold value, and it would auto recover.
This would also prevent overheating of the chip...
You can only do that if it does not need to source any real current.

That's an interesting idea. What was the latchup SCR's minimum
holding current?

Thanks,
- Win
Don't remember, 20 years ago.. but few mA, perhaps 10?
You could test this with this method quite easily (non destructive), if
you still have some 4000 series gates, would be interesting to know.
JP

?! few volts/few mA = kohms.
Yes I realized that when I wrote it, that is also why I wrote (cannot remember)

about that resistor value, still think it was 100 or there about though.

Perhaps the 'hold' effect also disappears as the voltage drops a lot?

Someone could try.
JP