4000 CMOS latch up

[Terry Given]

The actual text is left as an exercise for the reader?

Cheers
Terry

 

[Terry Given]

"Jim Thompson" <thegreatone@example.com> wrote in message
newst7fb0t3oo0hve0gmcj9l6fv48nkoclpn9@4ax.com...

On 28 May 2004 13:05:26 -0700, jpopelish@rica.net (John Popelish)
wrote:

John Popelish <jpopelish@rica.net> wrote in message
news:<40B66258.B21FA875@rica.net>...
Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs?
(snip)

I have been reading this thread with growing alarm, since no one
pointed out to me where on the data sheet I missed the specification
for maximum output pin voltage or current in the direction that pushes
the output pin voltage outside the rails voltage.

So I did a small experiment to get some idea how much trouble I might
be gettin myself into.

Unfortunately, I don't have much of a stock of new gates, but just my
collection of old gates I have been gathering for years.

I started with a CD4001BE quad NOR made by RCA with the additional
print M501 2WJND M0423. Perhaps this additional stuff means something
you one of you.

I connected a milliamp meter in series with whichever rail I was not
driving current into, with all the gate inputs tied together and to
the rail connected to the supply current meter. I fed current into
one output at a time from another supply, through a 1k resistor. I
measured the drop across the 1k to measure injected current, and also
measured the voltage between the output and the rail it was trying to
connect the output to.

Jim, whats the latching & holding current likely to be on these parasitic
SCRs? is the resistance of Johns milliammeter likely to keep the parasitic
current below said current(s)? I once got quite good at not turning
(adm,ittedly very large) SCRs on properly. And I once also bolloxed up a
perfectly good 1mA current source by putting a fluke 79 milliammeter in
series with it - the milliammeter resistance was not insignificant compared
to 1kohm.

After playing around with the supply voltage and finding no very
strong effefct in the 4 to 6 volt range that concerns me at this time,
I set the supply to 5 volts.

I attempted to find the injection current that would crank the supply
current up from a very low normal value to about .5 mA, because this
is where for this chip, the supply current really began to shoot up in
a very nonlinear way, indicating the onset of a positive feedback
mechanism between the power pins.

For currents pulling the outputs below the negative supply rail I
could only get to about -4 mA before the supply current reached .5 mA
(on the positive supply rail). This produced an output voltage of
about -.727 volts on the output pin, compared to the negative supply
rail. All 4 outputs were very similar.

Then I switched polarity and pulled the outputs above the positive
rail while measuring the current through the negative supply pin.
Because of the common between my multiple supplys, I had 5 volts less
supply to force current in this direction. So I drove it till I ran
out of voltage because I was too lazy to find a different current
shunt resistor.

I reached about +15mA into each of the outputs before the supply
currnt rose above about .4 mA (as far as I could go), and the supply
current was rising very much more proportionally to the output current
than it did for the negative current. The voltage on the output pins
was about +962 mV higher than the positive supply rail.

So, for this family and era of production, I tentatively conclude that
pulling an output below the negative rail is a lot more of a risk for
latching the chip than pulling the output above the positive rail.
Perhaps those of you with experience in the fabrication and structure
of this chip can explain why this is so.

The 4000-series parts are "single-well", that is the NMOS devices have
channel inducement in the substrate. Therefore, if you forward bias
the body diode of a NMOS (negative forced on output) you have currents
flowing throughout the substrate where it can interact with other NMOS
devices and produce current multiplication.

Forcing the output high, you are dealing with a PMOS device which has
a diffused well which is tied directly to VDD, thus no other paths for
current multiplication,


Then I replaced the chip with a much more modern (just bought it a
week ago) 74HC00 by T.I. code 41CDKHM. (Quad NAND with different
pinout)

Pulling the outputs low to -20 mA for an output voltage of -520 to
-541 mV below the negative rail, or positive to +15 mA for an output
voltage from +448 to +460 mV above the positive rail produced no
measurable supply current on my mA meter. Perhaps if I had the nerve
to go to high enough current to reach the voltages that produced
problems with the other chip, similar things might have happened, but
I didn't want to overheat anything, just yet.

Most likely an epitaxial process with isolated wells for both NMOS and
PMOS devices.

nice clarification. Are different manufacturers likely to use the same
process - IOW is this a latching vendor-substitute detector?

I need to purchase some modern 4000 series gates (by various
manufacturers) and find out if the process changes since my old RCA
chip was made have improved its horrible performance.


...Jim Thompson

Cheers
Terry

 

[Terry Given]

"Jon Elson" <jmelson@artsci.wustl.edu> wrote in message
news:40B7AAE2.3050104@artsci.wustl.edu...

John Popelish wrote:

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.

Everything appears to work fine, but I am worrying if some gates might
latch up by this current being driven through the N channel devices to
the negative supply rail. The chip will operate on a supply between 4
and 6 volts. All I see on the data sheet is a maximum current of +-
10 ma into any one input pin.



I can guarantee that it is possible, even if the voltage only is applied
to a
fully powered chip. I used all 6 sections of a 4069UB to drive an
isolated
power supply for FET driver bias. To simplify transformer winding, I
tried using multifilar wire, not thinking about the capacitance between
adjacent wire strands. (It came to several hundred pF for the full
winding.)
The 60+ V swing in under 100 nS of the power FETs was capable of injecting
enough current into the 4069 to latch it up, and it would explode. I
put 1N4148
diodes on it to clamp the current to the supply rails, and it kept the
chip from
latching up and self-destructing, but changing to separate winding
layers fixed
the problem without additional components. I think I was getting WAY
above the 10 mA you mention above!

Can you add some series resistance in the circuit? It might have
minimal effect
on the Piezo performance, but cut the peak current.

Jon

I once managed to "design" a +5V flyback converter compensation network that
gave about 25% overshoot on power-up. The Lattice ispLSI2032 EPLD I used in
my hardware got VERY upset, latched up and cooked. Most chips had the
numbers burned off, and the worst ones had a swollen case - about 1mm worth
of swelling (theres a bump in my package, dear liza dear liza). After
discovering that, I not only fixed the screw-up, but rigorously checked for
any over/under-voltage and cured with diodes + resistors a-la john.

smps chips also dont like having outputs pulled below V-. Nor do LM339s. It
didnt take many of these experiences before I decided to NEVER do that sort
of thing. And that includes capacitively coupling one gate to another.

Cheers
Terry

 

[Jim Thompson]

On Sat, 29 May 2004 12:24:45 +1200, "Terry Given"
<the_domes@xtra.co.nz> wrote:

"Jim Thompson" <thegreatone@example.com> wrote in message
newst7fb0t3oo0hve0gmcj9l6fv48nkoclpn9@4ax.com...
On 28 May 2004 13:05:26 -0700, jpopelish@rica.net (John Popelish)
wrote:

John Popelish <jpopelish@rica.net> wrote in message
[snip]
I connected a milliamp meter in series with whichever rail I was not
driving current into, with all the gate inputs tied together and to
the rail connected to the supply current meter. I fed current into
one output at a time from another supply, through a 1k resistor. I
measured the drop across the 1k to measure injected current, and also
measured the voltage between the output and the rail it was trying to
connect the output to.

Jim, whats the latching & holding current likely to be on these parasitic
SCRs? is the resistance of Johns milliammeter likely to keep the parasitic
current below said current(s)? I once got quite good at not turning
(adm,ittedly very large) SCRs on properly. And I once also bolloxed up a
perfectly good 1mA current source by putting a fluke 79 milliammeter in
series with it - the milliammeter resistance was not insignificant compared
to 1kohm.

While I know quite well what junctions are involved, I don't know what
current tips them off, or what the holding currents might be. It
varies a lot from manufacturer to manufacturer... every one of them
has their own proprietary ESD structure, and those structures are what
define the pin behavior.

[snip]

Then I replaced the chip with a much more modern (just bought it a
week ago) 74HC00 by T.I. code 41CDKHM. (Quad NAND with different
pinout)

Pulling the outputs low to -20 mA for an output voltage of -520 to
-541 mV below the negative rail, or positive to +15 mA for an output
voltage from +448 to +460 mV above the positive rail produced no
measurable supply current on my mA meter. Perhaps if I had the nerve
to go to high enough current to reach the voltages that produced
problems with the other chip, similar things might have happened, but
I didn't want to overheat anything, just yet.

Most likely an epitaxial process with isolated wells for both NMOS and
PMOS devices.

nice clarification. Are different manufacturers likely to use the same
process - IOW is this a latching vendor-substitute detector?

[snip]
Cheers
Terry

Dual-well processes are found on the more exotic chips, otherwise the
cross-talk gets out of hand at high speeds.

The stuff I work on is almost always dual-well, since I deal now
mostly with BiCMOS designs. My current design is on Atmel's "46K"
process... CMOS + 30GHz fT SiGe NPNs ;-) (A PECL toggle-flop at 2GHz
input only consumes 2mA @ 3.3V)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Rich Grise]

"Winfield Hill" <Winfield_member@newsguy.com> wrote in message

Jim Thompson wrote...
Winfield Hill wrote:
John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...
I object to your conclusion.
Win, Why do you object? It's correct.
Remember he's dealing with 4000 series parts, so the NMOS has as
its channel the inverted substrate.
I'm not objecting to the imbalance John observed, I'm objecting
to conclusions related to the final SCR latchup current. Yes,
the current may be increasing rapidly as he observed, but the
issue of ultimate interest is the actual latchup current. When
this point is reached, the supply will SCR down to about 1.2V.
Before that point the currents may be ugly, but will disappear
when the fault condition is removed.

Usually one can live with ugly. How ugly is the issue.

Apparently, a lot is still OK, because I've had to look at my own
face in the mirror every day for going on 50 years, and I'm still
alive. ;-)

Cheers!
Rich

 

[Winfield Hill]

Jim Thompson wrote...

Winfield Hill wrote:
Jim Thompson wrote...
Winfield Hill wrote:
John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion.

Win, Why do you object? It's correct.

Remember he's dealing with 4000 series parts, so the NMOS has as
its channel the inverted substrate.

I'm not objecting to the imbalance John observed, I'm objecting
to conclusions related to the final SCR latchup current. Yes,
the current may be increasing rapidly as he observed, but the
issue of ultimate interest is the actual latchup current. When
this point is reached, the supply will SCR down to about 1.2V.
Before that point the currents may be ugly, but will disappear
when the fault condition is removed.

Usually one can live with ugly. How ugly is the issue.

If I were personally doing the testing I'd call the limit the
point at which the current gain increases to unity.

But I engineer conservatively... why use a 2x4 when a Greek
column is available ?

I don't mean to be cranky, but we're not talking about conservative
engineering, we're talking about measuring a parameter. Despite my
considerable experience with CMOS logic SCR latchup, I haven't made
measurements the way we're discussing, but in a philosophical sense
consider this: The magnitude of the complete IC rail-rail current
may be considerably higher than the fault-mode pin-injection current
level when the SCR is finally triggered (i.e. gain much greater than
unity). That's what we need to know as a data point (afterwhich you
can practise conservative design). If the device has failed to SCR
latchup after the pin-current injection fault event, the circuit can
return to normal operation. So we'd like to know the latchup point.
Remember, this isn't an optimally-designed SCR we're talking about.

Let me tell a story. At my company, Sea Data, I designed and made
very complex battery-powered oceanographic instruments, which were
deployed on the deep-sea ocean bottom, operating dozens of sensors
and storing data for a year. One of the sensors was a Benthos flash
camera that could store hundreds of shots, taken when my instrument
determined that a bottom photograph was needed. But unfortunately
when I asked for a flash, a CMOS IC in my instrument would trip into
SCR latchup, shorting the supply regulator, ending the experiment.

The CMOS gate in question had no obvious relationship to the flash
signal, which was an optically-isolated circuit. Finally the cause
was traced to a flexible cable bundle between the electronics rack
and the bulkhead-penetrator connectors on the pressure-case endcap.
Triggered the camera caused a 2us capacitively-coupled current pulse
to a wire in the cable bundle that ultimately went to an output pin
of the CMOS logic chip suffering latchup.

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Jim Thompson]

On 29 May 2004 05:23:32 -0700, Winfield Hill
<Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Fred Bloggs]

John Popelish wrote:

Jon Elson wrote:

John Popelish wrote:


Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.

Everything appears to work fine, but I am worrying if some gates might
latch up by this current being driven through the N channel devices to
the negative supply rail. The chip will operate on a supply between 4
and 6 volts. All I see on the data sheet is a maximum current of +-
10 ma into any one input pin.




I can guarantee that it is possible, even if the voltage only is applied
to a
fully powered chip. I used all 6 sections of a 4069UB to drive an isolated
power supply for FET driver bias. To simplify transformer winding, I
tried using multifilar wire, not thinking about the capacitance between
adjacent wire strands. (It came to several hundred pF for the full
winding.)
The 60+ V swing in under 100 nS of the power FETs was capable of injecting
enough current into the 4069 to latch it up, and it would explode. I
put 1N4148
diodes on it to clamp the current to the supply rails, and it kept the
chip from
latching up and self-destructing, but changing to separate winding
layers fixed
the problem without additional components. I think I was getting WAY
above the 10 mA you mention above!

Can you add some series resistance in the circuit? It might have
minimal effect
on the Piezo performance, but cut the peak current.

Jon


I already had some dual series schottky diodes on the parts list, so I
put one of those pairs across each of the outputs. I had already
added a 1k resistor in series which kept the peak current below 6 mA,
but now that I see how badly this particular chip acted at 4 mA, I
decided to add the diodes, also.

Skip the direct drive and add two pairs of 2N4401/4403 push-pulls to
drive that thing- keep the diode clamps. End of problem-doubly.

 

[John Larkin]

On Sat, 29 May 2004 07:41:57 -0700, Jim Thompson
<thegreatone@example.com> wrote:

On 29 May 2004 05:23:32 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson

So the datasheet would say CAUTION: NEVER ALLOW PROTECTIVE DIODES TO
BE FORWARD BIASED, which in fact the CD4000A's should have had. RCA
sure didn't make an effort to warn us about this one. The 4009 was a
hair-trigger latching transient detector.

Like the ski run that had a sign: CAUTION: SIGN.

John

 

[Spehro Pefhany]

On Sat, 29 May 2004 10:27:24 -0700, the renowned John Larkin
<jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:

On Sat, 29 May 2004 07:41:57 -0700, Jim Thompson
thegreatone@example.com> wrote:

On 29 May 2004 05:23:32 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson

So the datasheet would say CAUTION: NEVER ALLOW PROTECTIVE DIODES TO
BE FORWARD BIASED

If the customers would just do that, they wouldn't be needed at all.
;-)

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Jim Thompson]

On Sat, 29 May 2004 18:29:38 GMT, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

On Sat, 29 May 2004 10:27:24 -0700, the renowned John Larkin
jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:

On Sat, 29 May 2004 07:41:57 -0700, Jim Thompson
thegreatone@example.com> wrote:

On 29 May 2004 05:23:32 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson

So the datasheet would say CAUTION: NEVER ALLOW PROTECTIVE DIODES TO
BE FORWARD BIASED

If the customers would just do that, they wouldn't be needed at all.
;-)

Best regards,
Spehro Pefhany

Tsk! Tsk! Tsk! Spehro, Now you're sounding like Win. Do you think
the diodes are there to clamp your signals? No! They are there for
ESD protection.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Joerg]

Terry Given wrote:

The actual text is left as an exercise for the reader?

Cheers
Terry




No, sorry, folks. My Netscape mail program became unstable and dumped

the text at random. I only knew after reading my own post on the NG.
Sometimes it blanked post, sometimes it didn't. So now I have dumped all
this mainstream software and use Mozilla. So far that works much better.

Regards, Joerg

http://www.analogconsultants.com

 

[John Larkin]

On Sat, 29 May 2004 11:41:58 -0700, Jim Thompson
<thegreatone@example.com> wrote:

On Sat, 29 May 2004 18:29:38 GMT, Spehro Pefhany
speffSNIP@interlogDOTyou.knowwhat> wrote:

On Sat, 29 May 2004 10:27:24 -0700, the renowned John Larkin
jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:

On Sat, 29 May 2004 07:41:57 -0700, Jim Thompson
thegreatone@example.com> wrote:

On 29 May 2004 05:23:32 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson

So the datasheet would say CAUTION: NEVER ALLOW PROTECTIVE DIODES TO
BE FORWARD BIASED

If the customers would just do that, they wouldn't be needed at all.
;-)

Best regards,
Spehro Pefhany

Tsk! Tsk! Tsk! Spehro, Now you're sounding like Win. Do you think
the diodes are there to clamp your signals? No! They are there for
ESD protection.

...Jim Thompson

Specifically, for *power off* ESD protection. Power on, they were MTBF
limiters.


John

 

[Jim Thompson]

On Sat, 29 May 2004 13:19:54 -0700, John Larkin
<jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:

On Sat, 29 May 2004 11:41:58 -0700, Jim Thompson
thegreatone@example.com> wrote:

On Sat, 29 May 2004 18:29:38 GMT, Spehro Pefhany
speffSNIP@interlogDOTyou.knowwhat> wrote:

On Sat, 29 May 2004 10:27:24 -0700, the renowned John Larkin
jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:

On Sat, 29 May 2004 07:41:57 -0700, Jim Thompson
thegreatone@example.com> wrote:

On 29 May 2004 05:23:32 -0700, Winfield Hill
Winfield_member@newsguy.com> wrote:

[snip]

OK, now let's talk about conservative design. Let's say our design
goal is to insure that any such fault-current pulses are 25x smaller
than the SCR-latchup level. We need to know this actual SCR level.
But if a test is performed which yields say 1/4 of the actual level,
then we're designing to 100x rather than 25x smaller currents, and
we may be needlessly jumping through very painful engineering hoops.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

One might argue to just follow the _pin_voltage_ limits_ on the data
sheet ;-)

...Jim Thompson

So the datasheet would say CAUTION: NEVER ALLOW PROTECTIVE DIODES TO
BE FORWARD BIASED

If the customers would just do that, they wouldn't be needed at all.
;-)

Best regards,
Spehro Pefhany

Tsk! Tsk! Tsk! Spehro, Now you're sounding like Win. Do you think
the diodes are there to clamp your signals? No! They are there for
ESD protection.

...Jim Thompson


Specifically, for *power off* ESD protection. Power on, they were MTBF
limiters.


John

If you want to contemplate "tricky", I've designed some chips whose
outputs go tri-state when they are un-powered ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Tony Williams]

In article <c99vc40mno@drn.newsguy.com>,
Winfield Hill <Winfield_member@newsguy.com> wrote:

Let me tell a story. At my company, Sea Data, I designed and
made very complex battery-powered oceanographic instruments,
which were deployed on the deep-sea ocean bottom, operating
dozens of sensors and storing data for a year. One of the
sensors was a Benthos flash camera that could store hundreds of
shots, taken when my instrument determined that a bottom
photograph was needed. But unfortunately when I asked for a
flash, a CMOS IC in my instrument would trip into SCR latchup,
shorting the supply regulator, ending the experiment.

I had a similar experience with early LMC660CN opamps.
The output stage was very tender if naughties happened
to it..... instant shorted power supplies, overheating,
and DIL cases actually cracked.

There was no time to investigate (just shifted to TL084),
but my antennae suggested an induced shoot-through in
the output stage (rather than an SCR latchup).

--
Tony Williams.

 

[Winfield Hill]

Tony Williams wrote...

Winfield Hill <Winfield_member@newsguy.com> wrote:

Let me tell a story. At my company, Sea Data, I designed and
made very complex battery-powered oceanographic instruments,
which were deployed on the deep-sea ocean bottom, operating
dozens of sensors and storing data for a year. One of the
sensors was a Benthos flash camera that could store hundreds of
shots, taken when my instrument determined that a bottom
photograph was needed. But unfortunately when I asked for a
flash, a CMOS IC in my instrument would trip into SCR latchup,
shorting the supply regulator, ending the experiment.

I had a similar experience with early LMC660CN opamps.
The output stage was very tender if naughties happened
to it..... instant shorted power supplies, overheating,
and DIL cases actually cracked.

There was no time to investigate (just shifted to TL084),
but my antennae suggested an induced shoot-through in
the output stage (rather than an SCR latchup).

The SCR latchup we have been referring to always acts across
the rail-to-rail power-supply pins, not in the output to one
rail, etc. If the "source" fault current comes from a high
voltage spike, as in the case of the flash, series resistors
may be little help. A pair of Schottky diodes to the supply
rails may not be enough given that their voltage drop can be
excessive at high currents; four diodes and a resistor may
be required. Sheesh! For short spikes, as mine were, adding
a capacitor can help. I don't remember my solution 25 years
ago, but I probably rewired the system to eliminate the fault
current spike, moving the camera's optocoupler to the endcap.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Spehro Pefhany]

On Sun, 30 May 2004 07:14:22 +0100, the renowned Tony Williams
<tonyw@ledelec.demon.co.uk> wrote:

In article <c99vc40mno@drn.newsguy.com>,
Winfield Hill <Winfield_member@newsguy.com> wrote:

Let me tell a story. At my company, Sea Data, I designed and
made very complex battery-powered oceanographic instruments,
which were deployed on the deep-sea ocean bottom, operating
dozens of sensors and storing data for a year. One of the
sensors was a Benthos flash camera that could store hundreds of
shots, taken when my instrument determined that a bottom
photograph was needed. But unfortunately when I asked for a
flash, a CMOS IC in my instrument would trip into SCR latchup,
shorting the supply regulator, ending the experiment.

I had a similar experience with early LMC660CN opamps.
The output stage was very tender if naughties happened
to it..... instant shorted power supplies, overheating,
and DIL cases actually cracked.

There was no time to investigate (just shifted to TL084),
but my antennae suggested an induced shoot-through in
the output stage (rather than an SCR latchup).

Hmm...did this happen with op-amp outputs going to the outside world?

I have a number of such applications where I've had no problems to
date (buffering voltage output DACs, conductivity probe drive, general
purpose analog outputs), and would very much like to keep it that way.

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Winfield Hill]

Spehro Pefhany wrote...

Hmm...did this happen with op-amp outputs going to the outside world?

I'd say we should be careful with CMOS opamp outputs.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Spehro Pefhany]

On 30 May 2004 07:11:27 -0700, the renowned Winfield Hill
<Winfield_member@newsguy.com> wrote:

Spehro Pefhany wrote...

Hmm...did this happen with op-amp outputs going to the outside world?

I'd say we should be careful with CMOS opamp outputs.

In conjunction with the typical decoupling circuit for load
capacitance, perhaps a relatively hefty 0.2A dual Si diode to the
supply rails would do the trick.

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Tony Williams]

In article <sbjjb098bdne5mbv0v68l9trgqrn2rikfv@4ax.com>,
Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote:

Hmm...did this happen with op-amp outputs going to the outside
world?

They were quad opamps with some outputs going outside.
Received back with the chip(s) totally destroyed and short
circuit from power-pin to power-pin.

I have a number of such applications where I've had no problems
to date (buffering voltage output DACs, conductivity probe drive,
general purpose analog outputs), and would very much like to keep
it that way.

No problems ever with (say) 324's or 084's just with
those LMC660CN opamps.

--
Tony Williams.