4000 CMOS latch up

John Popelish · May 27, 2004

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.

Everything appears to work fine, but I am worrying if some gates might
latch up by this current being driven through the N channel devices to
the negative supply rail. The chip will operate on a supply between 4
and 6 volts. All I see on the data sheet is a maximum current of +-
10 ma into any one input pin.

--
John Popelish

Joerg · May 27, 2004

Hi John,

My old Motorola CMOS book specs 25mA max for the outputs but isn't too
specific about conditions. This would be a case where I'd obtain info from
the manufacturer. Maybe a couple of Schottkys to either rail are enough to
take care of it but only the mfg can say.

Other chips such as this driver are more sturdy:

http://ww1.microchip.com/downloads/en/DeviceDoc/21425b.pdf

That one rates at 500mA for kickback.

Regards, Joerg

http://www.analogconsultants.com

Jan Panteltje · May 27, 2004

On a sunny day (Thu, 27 May 2004 17:49:12 -0400) it happened John Popelish
<jpopelish@rica.net> wrote in <40B66258.B21FA875@rica.net>:

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.
Its been a long time since I uses 4000 gates... Can't you add some diodes?

I have experienced latchup, for output, but not sure if that was from
going over pos or neg supply (has some cable on there, but added a fast
opamp driver to fix it) 1983!.

Terry Given · May 27, 2004

"Jan Panteltje" <panteltje@yahoo.com> wrote in message
news:c95s19$2v47$1@news.wplus.net...

On a sunny day (Thu, 27 May 2004 17:49:12 -0400) it happened John Popelish
jpopelish@rica.net> wrote in <40B66258.B21FA875@rica.net>:

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.
Its been a long time since I uses 4000 gates... Can't you add some diodes?
I have experienced latchup, for output, but not sure if that was from
going over pos or neg supply (has some cable on there, but added a fast
opamp driver to fix it) 1983!.

I wrote a dumb paper on this about 12 years ago, in a vain attempt to teach
students hwo to design circuits that actually work. When I did some
experiments, I found that 1990's 4000 series CMOS inputs were a lot harder
to latch up than the older stuff. I also found outputs latched almost as
easily on the new as the old. Probably because inputs usually have some form
of series R for so-called static-proofing. Outputs dont.

So I would argue that it is MORE likely to cause problems in the output than
the input.

Cheers
Terry

Joerg · May 27, 2004

Hi Terry,

Is there a copy of your paper on the web? It would be interesting to study data
about this topic. Often manufacturers are uneasy about making statements that
would go anywhere beyond what the datasheet says. With some notable exceptions,
that is.

Kudos to you for teaching student real stuff and not just gray theory. What do
you think made the attempt vain? Didn't they realize how important this is for
their career?

Regards, Joerg

http://www.analogconsultants.com

Terry Given · May 28, 2004

"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:40B68EF4.110A1819@removethispacbell.net...

Hi Terry,

Is there a copy of your paper on the web? It would be interesting to study
data
about this topic. Often manufacturers are uneasy about making statements
that
would go anywhere beyond what the datasheet says. With some notable
exceptions,
that is.

Kudos to you for teaching student real stuff and not just gray theory.
What do
you think made the attempt vain? Didn't they realize how important this is
for
their career?

Regards, Joerg

I dont even have a paper copy

It was part of an electronics experiment I
designed for a 3rd-year physics lab. IMO The cool bit was I built a
raster-scan display for an oscilloscope (yay for Z modulation), that drew
Karnaugh maps on-screen. And the whole damn thing was on veroboard (for a
while I had a thing about graphics cards, and designed several of my own, a
few of which actually worked

.

why in vain? most of these people still had difficulty with Ohms law. Very
good at maths, but lousy at circuits (sound familiar?). And no, they didnt
realise how important this stuff was for their career. I did, but I started
life as a technician, and I designed lots of circuits, most of which didnt
work in the field, for all the usual reasons, which I didnt learn about
until my eng. maths was good enough to understand what the good books were
telling me (yay for analog devices, Jim Williams etc)

Cheers
Terry

Robert Baer · May 28, 2004

John Popelish wrote:

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.

Everything appears to work fine, but I am worrying if some gates might
latch up by this current being driven through the N channel devices to
the negative supply rail. The chip will operate on a supply between 4
and 6 volts. All I see on the data sheet is a maximum current of +-
10 ma into any one input pin.

--
John Popelish

Most IC makers protect the inputs from negative excursions using the
simple expediency of palcing a diode beneath the bonding pads.
However, if an input is raised above the supply voltage, a sufficent
current times time (acts like a radioation dose) will cuse a "latchup"
problem; the input voltage will be ignored.
Take a problem part and bake it in your oven at 250F for an hour to
see if it is cured.
I hope i have remembered the numbers correctly; have not had to do
that for about 20 years.

Al · May 28, 2004

In article <40B6729E.F60FB2F8@removethispacbell.net>,
Joerg <notthisjoergsch@removethispacbell.net> wrote:

Hi John,

My old Motorola CMOS book specs 25mA max for the outputs but isn't too
specific about conditions. This would be a case where I'd obtain info from
the manufacturer. Maybe a couple of Schottkys to either rail are enough to
take care of it but only the mfg can say.

Other chips such as this driver are more sturdy:

http://ww1.microchip.com/downloads/en/DeviceDoc/21425b.pdf

That one rates at 500mA for kickback.

Regards, Joerg

http://www.analogconsultants.com

The biggest problem occurs when the input/outputs have voltage on them
before the IC is powered up. Due to the geometry of the internal
structures, SCRs are formed due to unintended biasing. And blooey when
device power is applied.

Al

--
There's never enough time to do it right the first time.......

John Larkin · May 28, 2004

On Fri, 28 May 2004 08:28:43 GMT, Robert Baer
<robertbaer@earthlink.net> wrote:

Most IC makers protect the inputs from negative excursions using the
simple expediency of palcing a diode beneath the bonding pads.

In many designs (notoriously CD4000A-series and LM324/339 types)
conduction of this very diode sprays charge all over rhe chip and
either makes everything go haywire or SCR-crowbars the power supply.

John

Jim Thompson · May 28, 2004

On Fri, 28 May 2004 19:31:17 GMT, Joerg
<notthisjoergsch@removethispacbell.net> wrote:

Why do you keep posting blanks ?

480)460-2350 | |
| E-mail Address at Website Fax

John Popelish · May 28, 2004

John Popelish <jpopelish@rica.net> wrote in message news:<40B66258.B21FA875@rica.net>...

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs?
(snip)

I have been reading this thread with growing alarm, since no one
pointed out to me where on the data sheet I missed the specification
for maximum output pin voltage or current in the direction that pushes
the output pin voltage outside the rails voltage.

So I did a small experiment to get some idea how much trouble I might
be gettin myself into.

Unfortunately, I don't have much of a stock of new gates, but just my
collection of old gates I have been gathering for years.

I started with a CD4001BE quad NOR made by RCA with the additional
print M501 2WJND M0423. Perhaps this additional stuff means something
you one of you.

I connected a milliamp meter in series with whichever rail I was not
driving current into, with all the gate inputs tied together and to
the rail connected to the supply current meter. I fed current into
one output at a time from another supply, through a 1k resistor. I
measured the drop across the 1k to measure injected current, and also
measured the voltage between the output and the rail it was trying to
connect the output to.

After playing around with the supply voltage and finding no very
strong effefct in the 4 to 6 volt range that concerns me at this time,
I set the supply to 5 volts.

I attempted to find the injection current that would crank the supply
current up from a very low normal value to about .5 mA, because this
is where for this chip, the supply current really began to shoot up in
a very nonlinear way, indicating the onset of a positive feedback
mechanism between the power pins.

For currents pulling the outputs below the negative supply rail I
could only get to about -4 mA before the supply current reached .5 mA
(on the positive supply rail). This produced an output voltage of
about -.727 volts on the output pin, compared to the negative supply
rail. All 4 outputs were very similar.

Then I switched polarity and pulled the outputs above the positive
rail while measuring the current through the negative supply pin.
Because of the common between my multiple supplys, I had 5 volts less
supply to force current in this direction. So I drove it till I ran
out of voltage because I was too lazy to find a different current
shunt resistor.

I reached about +15mA into each of the outputs before the supply
currnt rose above about .4 mA (as far as I could go), and the supply
current was rising very much more proportionally to the output current
than it did for the negative current. The voltage on the output pins
was about +962 mV higher than the positive supply rail.

So, for this family and era of production, I tentatively conclude that
pulling an output below the negative rail is a lot more of a risk for
latching the chip than pulling the output above the positive rail.
Perhaps those of you with experience in the fabrication and structure
of this chip can explain why this is so.

Then I replaced the chip with a much more modern (just bought it a
week ago) 74HC00 by T.I. code 41CDKHM. (Quad NAND with different
pinout)

Pulling the outputs low to -20 mA for an output voltage of -520 to
-541 mV below the negative rail, or positive to +15 mA for an output
voltage from +448 to +460 mV above the positive rail produced no
measurable supply current on my mA meter. Perhaps if I had the nerve
to go to high enough current to reach the voltages that produced
problems with the other chip, similar things might have happened, but
I didn't want to overheat anything, just yet.

I need to purchase some modern 4000 series gates (by various
manufacturers) and find out if the process changes since my old RCA
chip was made have improved its horrible performance.

Jim Thompson · May 28, 2004

On 28 May 2004 13:05:26 -0700, jpopelish@rica.net (John Popelish)
wrote:

John Popelish <jpopelish@rica.net> wrote in message news:<40B66258.B21FA875@rica.net>...
Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs?
(snip)

I have been reading this thread with growing alarm, since no one
pointed out to me where on the data sheet I missed the specification
for maximum output pin voltage or current in the direction that pushes
the output pin voltage outside the rails voltage.

So I did a small experiment to get some idea how much trouble I might
be gettin myself into.

Unfortunately, I don't have much of a stock of new gates, but just my
collection of old gates I have been gathering for years.

I started with a CD4001BE quad NOR made by RCA with the additional
print M501 2WJND M0423. Perhaps this additional stuff means something
you one of you.

I connected a milliamp meter in series with whichever rail I was not
driving current into, with all the gate inputs tied together and to
the rail connected to the supply current meter. I fed current into
one output at a time from another supply, through a 1k resistor. I
measured the drop across the 1k to measure injected current, and also
measured the voltage between the output and the rail it was trying to
connect the output to.

After playing around with the supply voltage and finding no very
strong effefct in the 4 to 6 volt range that concerns me at this time,
I set the supply to 5 volts.

I attempted to find the injection current that would crank the supply
current up from a very low normal value to about .5 mA, because this
is where for this chip, the supply current really began to shoot up in
a very nonlinear way, indicating the onset of a positive feedback
mechanism between the power pins.

For currents pulling the outputs below the negative supply rail I
could only get to about -4 mA before the supply current reached .5 mA
(on the positive supply rail). This produced an output voltage of
about -.727 volts on the output pin, compared to the negative supply
rail. All 4 outputs were very similar.

Then I switched polarity and pulled the outputs above the positive
rail while measuring the current through the negative supply pin.
Because of the common between my multiple supplys, I had 5 volts less
supply to force current in this direction. So I drove it till I ran
out of voltage because I was too lazy to find a different current
shunt resistor.

I reached about +15mA into each of the outputs before the supply
currnt rose above about .4 mA (as far as I could go), and the supply
current was rising very much more proportionally to the output current
than it did for the negative current. The voltage on the output pins
was about +962 mV higher than the positive supply rail.

So, for this family and era of production, I tentatively conclude that
pulling an output below the negative rail is a lot more of a risk for
latching the chip than pulling the output above the positive rail.
Perhaps those of you with experience in the fabrication and structure
of this chip can explain why this is so.

The 4000-series parts are "single-well", that is the NMOS devices have
channel inducement in the substrate. Therefore, if you forward bias
the body diode of a NMOS (negative forced on output) you have currents
flowing throughout the substrate where it can interact with other NMOS
devices and produce current multiplication.

Forcing the output high, you are dealing with a PMOS device which has
a diffused well which is tied directly to VDD, thus no other paths for
current multiplication,

Then I replaced the chip with a much more modern (just bought it a
week ago) 74HC00 by T.I. code 41CDKHM. (Quad NAND with different
pinout)

Pulling the outputs low to -20 mA for an output voltage of -520 to
-541 mV below the negative rail, or positive to +15 mA for an output
voltage from +448 to +460 mV above the positive rail produced no
measurable supply current on my mA meter. Perhaps if I had the nerve
to go to high enough current to reach the voltages that produced
problems with the other chip, similar things might have happened, but
I didn't want to overheat anything, just yet.

Most likely an epitaxial process with isolated wells for both NMOS and
PMOS devices.

I need to purchase some modern 4000 series gates (by various
manufacturers) and find out if the process changes since my old RCA
chip was made have improved its horrible performance.

480)460-2350 | |
| E-mail Address at Website Fax

Winfield Hill · May 28, 2004

John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion. Certainly it's useful to know how
much supply-rail current will flow during the approach to a fault
condition, and if this can ever occur in a design one should be
sure the supply can handle the unexpected additional current (in
the case of low-power supply rails, with short pulses of current,
an electrolytic across the rails may be sufficient).

But, what one really wants to know is just how much current is
required to induce true SCR latchup. If you properly set-up this
test you won't damage the part and you can repeat the test as many
times as you like. Use a current-limited power supply (say about
0.25A) with a very small output electrolytic, or create such a
beast. Increase the fault current until you observe the latchup.
This state is like a true SCR in that it'll force the supply pins
to be no more than 1.2V, drawing as much current as allowed, even
several amps. At 0.25A the part will get warm, but its operation
after cooling off will be unchanged. Turn off the supplies and
repeat the experiment. Have fun. Report back.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

Guy Macon · May 28, 2004

Winfield Hill <Winfield_member@newsguy.com> says...

John Popelish wrote:

So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion. Certainly it's useful to know how
much supply-rail current will flow during the approach to a fault
condition, and if this can ever occur in a design one should be
sure the supply can handle the unexpected additional current (in
the case of low-power supply rails, with short pulses of current,
an electrolytic across the rails may be sufficient).

But, what one really wants to know is just how much current is
required to induce true SCR latchup. If you properly set-up this
test you won't damage the part and you can repeat the test as many
times as you like. Use a current-limited power supply (say about
0.25A) with a very small output electrolytic, or create such a
beast. Increase the fault current until you observe the latchup.
This state is like a true SCR in that it'll force the supply pins
to be no more than 1.2V, drawing as much current as allowed, even
several amps. At 0.25A the part will get warm, but its operation
after cooling off will be unchanged. Turn off the supplies and
repeat the experiment. Have fun. Report back.

This was a long time ago, but I am pretty sure that when I tried it
it acted the same in both cases.

--
Guy Macon, Electronics Engineer & Project Manager for hire.
Remember Doc Brown from the _Back to the Future_ movies? Do you
have an "impossible" engineering project that only someone like
Doc Brown can solve? My resume is at http://www.guymacon.com/

Jon Elson · May 28, 2004

John Popelish wrote:

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.

Everything appears to work fine, but I am worrying if some gates might
latch up by this current being driven through the N channel devices to
the negative supply rail. The chip will operate on a supply between 4
and 6 volts. All I see on the data sheet is a maximum current of +-
10 ma into any one input pin.

I can guarantee that it is possible, even if the voltage only is applied

to a
fully powered chip. I used all 6 sections of a 4069UB to drive an isolated
power supply for FET driver bias. To simplify transformer winding, I
tried using multifilar wire, not thinking about the capacitance between
adjacent wire strands. (It came to several hundred pF for the full
winding.)
The 60+ V swing in under 100 nS of the power FETs was capable of injecting
enough current into the 4069 to latch it up, and it would explode. I
put 1N4148
diodes on it to clamp the current to the supply rails, and it kept the
chip from
latching up and self-destructing, but changing to separate winding
layers fixed
the problem without additional components. I think I was getting WAY
above the 10 mA you mention above!

Can you add some series resistance in the circuit? It might have
minimal effect
on the Piezo performance, but cut the peak current.

Jon

Jim Thompson · May 28, 2004

On 28 May 2004 14:06:04 -0700, Winfield Hill
<Winfield_member@newsguy.com> wrote:

John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion.
[snip]

480)460-2350 | |
| E-mail Address at Website Fax

John Popelish · May 28, 2004

Winfield Hill wrote:

John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion. Certainly it's useful to know how
much supply-rail current will flow during the approach to a fault
condition, and if this can ever occur in a design one should be
sure the supply can handle the unexpected additional current (in
the case of low-power supply rails, with short pulses of current,
an electrolytic across the rails may be sufficient).

Well, the supply current was increasing so rapidly by the time ir
reached .5 mA (4 mA of output current caused .5 mA of supply current.
4.1 ma of output current caused 1 mA of supply current, etc.) that
there was no practical reason for me to find out the exact latch
current, since I want to stay away from any possibility of this
happening, and I don't have a very exhaustive sample, here (1 unit).

But, what one really wants to know is just how much current is
required to induce true SCR latchup. If you properly set-up this
test you won't damage the part and you can repeat the test as many
times as you like. Use a current-limited power supply (say about
0.25A) with a very small output electrolytic, or create such a
beast. Increase the fault current until you observe the latchup.
This state is like a true SCR in that it'll force the supply pins
to be no more than 1.2V, drawing as much current as allowed, even
several amps. At 0.25A the part will get warm, but its operation
after cooling off will be unchanged. Turn off the supplies and
repeat the experiment. Have fun. Report back.

If I can find the time, I may go back and play some more.

--
John Popelish

John Popelish · May 28, 2004

Jon Elson wrote:

John Popelish wrote:

Is current injected into the outputs of 4000 series CMOS more or less
likely to cause latch up that current driven into inputs? I have
built a piezo driver that bridges the piezo between two nor gates.
The sound is turned off by driving one of the inputs on each gate
high. Alternating pulses are applied ot the outer input of each of
the gates. When I pull the enable pair low, the gates take turns
producing positive pulses. But I see that when one gate pulls down,
the other output is driven a volt or so below the negative rail by the
capacitive current through the piezo.

Everything appears to work fine, but I am worrying if some gates might
latch up by this current being driven through the N channel devices to
the negative supply rail. The chip will operate on a supply between 4
and 6 volts. All I see on the data sheet is a maximum current of +-
10 ma into any one input pin.

I can guarantee that it is possible, even if the voltage only is applied
to a
fully powered chip. I used all 6 sections of a 4069UB to drive an isolated
power supply for FET driver bias. To simplify transformer winding, I
tried using multifilar wire, not thinking about the capacitance between
adjacent wire strands. (It came to several hundred pF for the full
winding.)
The 60+ V swing in under 100 nS of the power FETs was capable of injecting
enough current into the 4069 to latch it up, and it would explode. I
put 1N4148
diodes on it to clamp the current to the supply rails, and it kept the
chip from
latching up and self-destructing, but changing to separate winding
layers fixed
the problem without additional components. I think I was getting WAY
above the 10 mA you mention above!

Can you add some series resistance in the circuit? It might have
minimal effect
on the Piezo performance, but cut the peak current.

Jon

I already had some dual series schottky diodes on the parts list, so I
put one of those pairs across each of the outputs. I had already
added a 1k resistor in series which kept the peak current below 6 mA,
but now that I see how badly this particular chip acted at 4 mA, I
decided to add the diodes, also.

--
John Popelish

Winfield Hill · May 28, 2004

Jim Thompson wrote...

Winfield Hill wrote:

John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion.

Win, Why do you object? It's correct.

Remember he's dealing with 4000 series parts, so the NMOS has as
its channel the inverted substrate.

I'm not objecting to the imbalance John observed, I'm objecting
to conclusions related to the final SCR latchup current. Yes,
the current may be increasing rapidly as he observed, but the
issue of ultimate interest is the actual latchup current. When
this point is reached, the supply will SCR down to about 1.2V.
Before that point the currents may be ugly, but will disappear
when the fault condition is removed.

Usually one can live with ugly. How ugly is the issue.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

Jim Thompson · May 28, 2004

On 28 May 2004 16:21:41 -0700, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Jim Thompson wrote...

Winfield Hill wrote:

John Popelish wrote:
[ snip ]
So, for this family and era of production, I tentatively conclude
that pulling an output below the negative rail is a lot more of
a risk for latching the chip than pulling the output above the
positive rail. ...

I object to your conclusion.

Win, Why do you object? It's correct.

Remember he's dealing with 4000 series parts, so the NMOS has as
its channel the inverted substrate.

I'm not objecting to the imbalance John observed, I'm objecting
to conclusions related to the final SCR latchup current. Yes,
the current may be increasing rapidly as he observed, but the
issue of ultimate interest is the actual latchup current. When
this point is reached, the supply will SCR down to about 1.2V.
Before that point the currents may be ugly, but will disappear
when the fault condition is removed.

Usually one can live with ugly. How ugly is the issue.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

If I were personally doing the testing I'd call the limit the point at
which the current gain increases to unity.

But I engineer conservatively... why use a 2x4 when a Greek column is
available ?

480)460-2350 | |
| E-mail Address at Website Fax

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